CpE 323 –

Microprocessor Systems

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PRESIDENT RAMON MAGSAYSAY STATE UNIVERSITY
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CpE 323 – Microprocessor Systems
First Edition, 2025

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Learning Module Development Team

Assigned
Title Author
Chapter
Structural Components of
Chapter 1:
Microprocessor/Microcontroller
Chapter 2: Data Representation and Number Systems
Chapter 3: Fetch-Decode-Execute
Dionisio M. Martin Jr.
Chapter 4:
Chapter 5:
Chapter 6:
Chapter 7:

Evaluators:

Dr. Marlon James Dedicatoria, Program Chair

Engr. Ferndinand Tabligan, Program Chair
Engr. Gilbert Deboma, Dean
Course Overview
Introduction

The Microprocessor Systems course is a four-unit professional course which offers an in-
depth exploration of microprocessors and their application in embedded systems. It provides
students with the foundational knowledge required to understand, program, and interface
microprocessors with various peripherals.

This course provides a comprehensive introduction to microprocessor architecture,

programming, and embedded system design. It combines theoretical learning with practical,
hands-on experience to prepare students for working in the rapidly evolving fields of
electronics, embedded systems, and automation.

By the end of the course, students will gain practical skills in designing, programming, and
debugging microprocessor-based systems used in a wide range of modern technologies such as
robotics, automation, communication devices, and consumer electronics.

Course General Objectives

At the end of the semester, 85% of the students have attained 90% level of understanding for
being aware in the computer engineering, locally and globally.

1. Understand the structure and architecture of microprocessor systems.

2. Learn how to program and interface microprocessors with peripherals.
3. Explore microprocessor components, such as ALU, control unit, registers, memory,
and I/O systems.
4. Develop skills in assembly language programming and higher-level languages for
microprocessor systems.
5. Understand microprocessor communication protocols (e.g., I2C, SPI, UART).
6. Implement real-time systems and control applications using microprocessor-based
systems.

Course Details:

 Course Code: CpE 323

 Course Title: Microprocessor Systems
 No. of Units: 4-unit lecture
 Classification: Lecture with Laboratory-based
 Pre-requisite / Co-Requisite: Logic Circuit and Design
 Semester and Academic Year: 2nd Semester, AY 2025-2026
 Schedule: BSCpE 3A – Monday and Wednesday, 9:00 AM - 10:30 AM
BSCpE 3B – Tuesday and Thursday, 12:30 PM - 2:00 PM
 Name of Faculty: Dionisio M. Martin Jr.
 Contact Details
 Email: dmmartinjr@[Link]
Mobile Number: 0939-906-0585
FB Account: Dionisio Martin Jr.
 Consultation
Day: MWF
Time: 1:00-2:00PM

Learning Management System

The University LMS will be used for asynchronous learning and assessment. The link and class
code for LMS will be provided at the start of class through the class’ official Facebook Group.

 Edmodo
 Google Classroom
 University LMS

Assessment with Rubrics

Students will be assessed in a regular basis thru quizzes, assignments, individual/group outputs
using synchronous and/or asynchronous modalities or submission of SLM exercises. Rubrics
are also provided for evaluation of individual/group outputs.

Major examinations will be given as scheduled. The scope and coverage of the examination
will be based on the lessons/topics as plotted in the course syllabus.
 0323

Module Overview
Introduction

The Microprocessor Systems course introduces students to the fundamental concepts of

microprocessors and their role in embedded systems. It covers the architecture, operation,
programming, and applications of microprocessors, equipping students with the knowledge
and skills to work with microprocessors in real-world projects.

Microprocessors form the backbone of modern electronics, from simple household devices to
complex industrial control systems. As the demand for embedded systems continues to grow,
understanding how microprocessors work, how they are programmed, and how they interface
with external systems is crucial for engineering students. The Microprocessor Systems course
prepares students for careers in electronics, automation, robotics, and embedded system design
by providing the foundation needed to work with real-time systems and hardware interfaces.

The course emphasizes practical application, enabling students to design, build, and
troubleshoot microprocessor-based systems. It integrates theoretical learning with laboratory
sessions and project work, where students can apply their knowledge to solve real-world
problems.

Table of Contents

Chapter 1: Structural Components of Microprocessor/Microcontroller

Chapter 2: Data Representation and Number Systems
Chapter 3: Fetch-Decode-Execute
Chapter 4:
Chapter 5:
Chapter 6:
Chapter 7:
Microprocessor Systems

Chapter 3

Fetch-Decode-
Execute
Chapter 3

Fetch-Decode-Execute
Introduction

The fetch-decode-execute cycle describes the basic operation of modern computer systems. It
is important to understand the components of the processor and the data bus, address
bus and control bus and how this interact to one another for the computer operation.

Programs, for example those that allow a user to play a video game, use a spreadsheet, debug
a program, or check your emails, are made up of thousands of instructions. To run a program
these instructions must be fetched, decoded, and executed.

These stages form the fetch-decode-execute cycle, fetch-execute cycle or instruction cycle –
because these are repeated over and over again for every instruction of every program that is
run inside a computer.

Specific Objectives

At the end of the lesson, the students should be able to:

- describe how the fetch-decode-execute cycle enables a CPU to process instructions and
manage program execution.
- recognize and define the roles of the registers, ALU and CU in executing instructions.
- describe each stage of the cycle in the process of fetching an instruction from memory,
decoding it to determine the required operation, and executing it using the ALU or
registers.
- demonstrate the FDE Cycle in a simple program in a real CPU simulation to step
through and analyze the fetch-decode-execute cycle in action.

Duration

Chapter 3: Fetch-Decode-Execute = 2 hours

(1.5-hours discussion;
0.5-hour assessment)

_____________________________________________

COMPONENTS OF THE CPU

CPU – is responsible for processing all data within the computer

– is made up of a number of components including:
o Arithmetic and Logic Unit (ALU)
o Control Unit (CU)
o Registers are temporary storage/memory locations inside the CPU which are
used for a single specific purpose. They have a faster access speed than RAM/
 secondary storage. There are a number of registers in the CPU:
a. Program Counter (PC)
b. Accumulator (ACC)
c. Memory Address Register (MAR)
d. Memory Data Register (MDR)
e. Current Instruction Register (CIR)

Diagram of Components Within the CPU

Component Function
This performs any arithmetic calculations (e.g. adding binary) or any logic
Arithmetic and Logic Unit (ALU) comparisons (using AND, OR, NOT)
The ALU is made up of several components
This is where instructions are decoded. The CU also controls the data within
Control Unit
the CPU and how it moves around
Program Counter (PC) This stores the address in memory of the next instruction to be fetched
This is where values are stored temporarily, either after they’ve been inputted
Accumulator (ACC)
or loaded, or after being calculated in the ALU
This is where addresses are stored, either for where data is being sent in
Memory Address Register (MAR)
memory, or where it is being fetched from
This is where data/instructions are stored, either before it sent to memory, or
Memory Data Register (MDR)
after being fetched
When an instruction has been fetched from memory it is loaded here before
Current Instruction Register (CIR)
being split into opcode and operand. After this, it will be decoded.

The ALU is made up of several components:

 Arithmetic circuit. This carries out any arithmetic (addition, subtraction,
multiplication or division)
 Logic circuit. This carries out operations like AND, OR, NOT, XOR
 Registers. These are additional registers to those mentioned above and can store data
 Status flags. This includes overflow flags (if the value is too large for the register) or
could include a zero flag (to tell if the answer is 0 easily)
 Buses. These are used to transport data around the ALU and to other parts of the CPU
 FETCH-DECODE-EXECUTE

Fetch-Decode-Execute Cycle – is the process that the CPU goes through repeatedly to process
instructions.
– have 3 stages:
o Fetching an instruction from memory - supplying the address and receiving
the instruction from memory
o Decoding the instruction - interpreting the instruction and then reading and
retrieving the required data from their addresses
o Executing the instruction - the CPU carries out the required action
– is the cycle that the central processing unit (CPU) runs through billions of times
per second to make a computer work

The Fetch-Decode-Execute Cycle Stages

a. Fetch stage
 During the fetch stage of the cycle, the program counter holds the address of the next
instruction to be fetched from memory
 The address of the next instruction or data to be fetched is copied into the memory
address register (MAR)
 The address of the instruction or data is then sent along the address bus and awaits a
signal from the control bus
 The signal sent along the control bus is sent from the control unit (CU) to the main
memory
 The data or instructions received from main memory is fetched to the memory data
register (MDR) via the data bus
 A copy of the instruction or data is stored in the current instruction register (CIR)
 The program counter (PC) increments by 1 so it is pointing to the next instruction to be
executed
b. Decode stage
 During the decode stage of the cycle, the CPU needs to work out what is required from
the instruction
 This is done as the instruction is split into two parts:
o Opcode - what the instruction is
o Operand - what to do it to
 This could be either data or an address where the data is stored
 c. Execute stage
 During the execute stage of the cycle, the CPU will carry out the instruction that was
fetched
 Some examples that would take place at this stage are:
1. Performing a calculation
2. Storing a result or data back in main memory (RAM)
3. Going to main memory to fetch data from a different location

The figure below represents the flow of the Fetch-Decode-Execute cycle:

Registers Involved in Fetch-Decode-Execute Cycle

The figure below illustrates the process of the Fetch-Execute cycle for an instruction,
highlighting the role of each register involved in the process:

During the Fetch-Decode-Execute Cycle, the following steps happen:

 Fetch
o The PC is loaded with 0
o The value from the PC (0) is copied to the MAR
o The data from the MAR (0) is sent across the address bus with the instruction to
read the data sent across the control bus
o The data from that location in memory (0) is sent down the data bus to the MDR
o The PC is incremented by 1
 Decode
 o The data is sent from the MDR to the CIR where it is split into the opcode and
operand
o This is sent to the CU to be decoded
 Execute
o Which registers are used here will depend on the instruction being executed
a. If a value is being inputted (IN) the ACC will store the value
b. If a value is being outputted (OUT) this will be the value currently in
the ACC
c. If a value is loaded from RAM (LDA) this will be sent across the data bus
from RAM (in the address location in the MAR) to the MDR
d. If a value is to be stored (STA) it will take the value from the ACC, send it
to the MDR and then send it across the data bus to RAM (to the address
location in the MAR)
e. If a value is being added to or subtracted from another value (ADD/SUB)
f. If the code is to branch (BRA/BRZ/BRP), the comparison will take place in
the ALU

_____________________________________________

References/Additional Resources/Readings

[Link]

[Link]

[Link]
hardware/computer-architecture/the-fetch-decode-execute-cycle/
Activity Sheet
ACTIVITY 3

Name: ___________________________ Course/Year/Section: ___________ Score: _________

Direction: Encircle the letter of the best answer.

1. Which register holds the address of the next instruction to be fetched during the fetch-decode-
execute cycle?
a) MDR b) PC c) CIR d) MAR
2. During the execute phase of the fetch-decode-execute cycle, what happens if the instruction
requires data from memory?
a) The ALU automatically calculates the result
b) The MDR retrieves the data from memory
c) The CU skips the fetch phase for the next instruction
d) The instruction is stored in the PC
3. Which of the following statements best describes the function of the MAR?
a) It stores data temporarily before being sent to memory
b) It holds the address of the next instruction or data to be fetched
c) It performs logical operations on the fetched data
d) It decodes the instruction before execution
4. What role does the CIR play in the instruction cycle?
a) It stores the decoded instruction until execution
b) It holds the address of the next instruction to be executed
c) It transfers data from the ALU to memory
d) It temporarily holds the instruction that has just been fetched
5. What is the significance of the opcode in an instruction during the decode stage?
a) It specifies the memory location where the data is stored
b) It determines the operation that needs to be performed
c) It points to the next instruction in the sequence
d) It signals the CPU to fetch the next instruction
6. What happens to the PC after an instruction is fetched?
a) It decrements by 1 b) It is reset to zero
c) It increments by 1 d) It is copied to the MAR
7. The CU is responsible for which of the following functions?
a) Performing arithmetic calculations
b) Storing temporary data during execution
c) Directing data flow and managing control signals
d) Storing the results of executed instructions
8. During the Fetch stage, what is the role of the MAR?
a) Holds the instruction address b) Stores fetched data
c) Decodes instruction d) Performs calculations
9. How does the fetch-decode-execute cycle contribute to CPU performance?
a) It reduces memory usage by fetching only essential instructions
b) It ensures a continuous flow of instructions for processing
c) It speeds up the execution by skipping the decode phase when necessary
d) It minimizes power consumption by reducing the number of executed instructions
10. During the execution stage, which of the following components is primarily responsible for
performing arithmetic and logical operations?
a) CU b) MAR c) ALU d) CIR
11. What happens if the CIR fails to store the fetched instruction?
a) Slower execution b) Wrong instruction runs
c) PC fixes error d) System restarts
12. Suppose a microprocessor has a damaged ALU. What kind of instructions would fail to execute
properly?
a) Instructions that involve reading data from memory
b) Instructions related to arithmetic and logical operations
c) Instructions that control the flow of execution
d) Instructions related to fetching data from the hard drive
13. A programmer notices that a CPU executes instructions but does not update the PC. What might
be the result?
a) The same instruction may execute repeatedly, leading to an infinite loop.
b) The CPU will skip instructions and execute only every other command.
c) The fetch-decode-execute cycle will operate normally without any effect.
d) The CPU will randomly select instructions to execute.
14. If a system has a slow MDR, what would be the most noticeable effect?
a) The CPU would take longer to fetch and execute instructions.
b) The system would skip certain instructions.
c) The CU would compensate by increasing clock speed.
d) The PC would store incorrect addresses.
15. If the CU incorrectly decodes an instruction, which of the following scenarios is most likely to occur?
a) The CPU will execute an unintended operation, possibly leading to errors.
b) The CPU will execute the correct instruction but in the wrong order.
c) The instruction will be skipped entirely.
d) The system will automatically correct the mistake in the next cycle.
16. If the PC is not incremented correctly, what would be the most immediate effect?
a) The system will restart the fetch-decode-execute cycle from the beginning.
b) The CPU will fetch and execute the wrong instruction.
c) The MAR will correct the error automatically.
d) The instruction cycle will be skipped entirely.
17. During an instruction execution, the CPU is unable to retrieve data from memory. Which component
is most likely at fault?
a) ALU b) MAR c) CIR d) CU
18. If a processor has an inefficient Fetch-Decode-Execute cycle, how might this impact system
performance?
a) The system may experience slow response times or delays in execution.
b) The system will execute instructions more quickly but inaccurately.
c) The system will permanently store the fetched instructions in memory.
d) The CPU will compensate by increasing its clock speed.
19. If a CPU is executing a program and suddenly encounters an instruction it cannot decode, what
would be the most probable response?
a) The CPU will automatically skip to the next instruction.
b) The CPU will halt or trigger an error message.
c) The CPU will attempt to guess the intended operation.
d) The PC will correct the instruction before execution.
20. A computer system's performance is degrading due to excessive data movement. Which
optimization strategy can improve the Fetch-Decode-Execute cycle?
a) Reducing the number of registers in the CPU
b) Using cache memory to store frequently accessed instructions
c) Increasing the time delay between fetch and execute phases
d) Disabling the use of the ALU
Direction: Match the items in column A to their descriptions in column B. write only the letter of your
choice on the space provided.
A B
_____ 1. Address Bus a. Holds the instruction currently being executed.
_____ 2. ACC b. Temporarily stores fetched instructions or data.
_____ 3. ALU c. Stores the next instruction’s memory address.
_____ 4. CIR d. Controls the CPU's execution of instructions.
_____ 5. CU e. Performs arithmetic and logical operations.
_____ 6. Fetch-Decode-Execute Cycle f. A sequence of steps used by the CPU to process instructions.
_____ 7. MDR g. Temporarily stores results of arithmetic operations.
_____ 8. Opcode h. The operation part of an instruction.
_____ 9. Operand i. The data or memory location on which an operation is performed.
_____ 10. PC j. Transfers memory addresses between components.

Direction: Give the complete terms for the following abbreviated words.
1. ACC
2. ALU
3. CIR
4. CPU
5. CU
6. GPR
7. MAR
8. MDR
9. PC
10. RAM

Direction: Rearrange the operations below in the order they are performed during the fetch stage of the
fetch-decode-execute cycle.
Problem 1:
A – The contents of the PC are copied to the MAR
B – The fetched instruction is transferred to the processor using the data bus
C – The contents of the MDR are copied to the CIR
D – At the same time, the contents of the PC are incremented by one
E – The contents of the MAR are used to access the correct location in memory
F – The fetched instruction is saved in the MDR

Problem 2:
A – Perform the addition of two numbers.
B – Fetch the instruction that specifies the addition.
C – Decode the instruction to identify the operation type (addition).
D – Store the result in a specified register.
E – Increment the program counter.

Problem 3:
A – Fetch the instruction to load data from memory to a register.
B – Load the data from the specified memory address into the register.
C – Decode the instruction to understand it is a load instruction.
D – Increment the program counter to point to the next instruction.
E – Perform the operation of loading the data into the register.