Group ' Attempt any SIX questions. (6x5=30) 11, Subtract: 675.6 - 4564 using both 10's and 9's complement, 5) Ans: Taking Integer part only A=675andB Shek sksé Discard +, Result = 219.2 ‘ Again. Taking fraction part only A=6andB Discard» @2 Using Ys complement Taking Integer part only A = 675 and b= 456 9's complacent =) BekAgain Taking Fraction part only Aw6and B=4 %s complement of B =¥; =x 5 26 n = 2 *. -Result= 2192 m What is universal logic gate? Realize NAND and NOR as an logic gates. It Ans: University Gates A universal gate is a gate which can implement any Booléan without need to use any other gate type. The NAND and NOR gates | universal gates. In practice, this is advantagoous since NAND and gales are economical and easier to fabricate and are the basic gates in all IC digital logic families In fact, an AND gate is 1 implemented as a NAND gate followed by an inverter not the other ra around. Likewise. an OR gate is typically implemented as a NOK followed by an inverter not the other way around. NAND Gate as.a Universal Gate To prove that any Boolean function can be Implemented using NAND gates, we will show that the AND. OR, and NOT operations be performed using only these gates. F Implementing an Inverter Using only NAND Gate The figure shows two ways in which a NAND gate can be used as inverter (NOT gate). 1. All NAND input pins connect to the input signal A gives output A’. AAY =A’ ° tla ae &) 2 One NAND input pin is connected to the input signal A while all other input pins are connected to logic 1. The output will be fl a A . 1B ! (b)Implementing ANDU sing only NAND Gates An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND gate with its output complemented bya NAND gate inverter). j ” cae de : an {A = = * & Implementing OR Using only NAND Gates An OR gate can be replaced by NAND gates as shown in the figure (The OR gate ts replaced by a NAND gate with all its inputs complemented by NAND gate inverters). A A (AB) =A+B Mlustration of NAND gate as.a universal gate (a) Thos, the NAND gate is a universal gates because it can implement the AND, OR and NOT functions. NOR Gate is as Universal Gate To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND, OR, and NOT operations can be performed using only these gates. . implementing an Inverter Using, only NOR Gate The figure shows two ways in which a NOR gate can be used 4s. an inverter (NOT gate}. 1, _ All. NOR input pins connect to the input signal A gives an output A’. Ayes “t a 2 One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be A’. 0) -A' . Te +0)-A larch a A (b) Implementing OR Using only NOR Gates An OR gate can be replaced by NOR gates a8 shown in the figure (The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter)13. Ans: F = BCD’ + BCD’ + ABCD’ + BCD’ + A'BOD by NOR gate inverters) 7 Iustration of NOR gate as a universal gate A A A 5B —_ B; B 8 (a ‘Thus, the NOR gate is a universal gates in ceit can implement the A! OR and NOT functions. Simplify (using K-map) the given Boolean function F in both SOP POS using don't care conditions A: 7 F=B'CD' + BCD’ + ABCD’ + B'CD' + A'BOD |e F= (C+). (A +), 8 +B), B+C+ Dd)14. Define encoder: Draw logic encoder. Ans: Encoder diagram and trath table of octal-to-binary fies] An encoder is a device, cireult, transducer, software program, algorithm or person that converts information from one format or cade to another ‘The purpose of encoder is standardization, speed, secrecy: security, oF saving space by shrinking size. Encoders are combinational logic circuits and they are exactly opposite of decoders. They accept one or mors inputs and generate a multibit output code. Encoders perform exactly reverse operation than decoder. An encoder hg M input and N output lines. Out of M input lines only one medvated at a time and proxtuces equivalent code on output N lines. Ifa device output code has fewer bits than the input code has, the device usually called an encoder. L. Octal to binary encoder Gctal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3to-8 decoder does. At any one time, only ont Octal-to-binary encoder. For an 8-to-3 binary encoder with inputs lotr outputs YoY: are: Yo *h+h+ht+l Y% th+h+h+h Yo = ht ls + le th Table: Truth Table of octal to binary encoder" Figure: Logic Diagram of octal to binary encoder 15. What is D flip-flop? Explain clocked RS flip flop with its logic diagram and truth table. — fied] Ans: D Flip Flop D flip is actually a slight modification of the above explained clocked SR flip-flop. From the figure you can see that fhe D input is connected to the $ input and the complement of the D input is connected to the R input, The D input is passed on to the flip lop when the value of CP is 1’ When CP is HIGH, the flip flop moves to the SET state. If it is ‘0, the flip flop switches to the CLEAAR state. As long as the clock input C = 0, the SR latch has both inputs equal to 0 and it can't change its state regardless of the value of D. When C is 1, the latch is placed in the set or reset state based on the value of D. 1£D = 1, the Q output goes to 1. if D = 0, the Q outpui goes to 0. Clocked $-R Flip Flop * Itis also called a Gated S-R flip flop, + The problems with S-R flip flops using NOR and NAND gate is the invalid stated,© This problem can be overcome by using a bitable SR flip-flop that can change outputs when certain invalid states are met, regardless of the condition of either the Setor the Reset inputs. * For this, a clocked S-R flip flop ia designed by adding two AND neither gates fo a basic NOR gateflip flop. © The cireuit diagram and truth table is shown below. The circuit of the S-R flip flop using NAND gated and its truth table is shown below. 0 Nochange 1 Q=Q rest state . 1 1 0 Qt; set state ® s 0 X X Nochange o 0 1 1 1 Indeterminate (b) Function table Figure: Clocked $-R Flip Flop A clock Pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is °Y, the ontputs of both the AND Fates remain ‘0 As soon a pulse is given the value of CP turns ‘1’, ‘This makes the values at S and R to pass through the NOR Gate flip flop. But when the values of both S and R values turn ‘I’, the HIGH value of CP causes them to turn to ‘0! for a short moment. As soon as the pulse is remove, the flip flop state becomes intermediate. Thus either of the two states may be caused, and it depends on whether the set or reset input of the flip-flop remains a ‘I’ longer than the transition to ‘0’ at the end of the pulse. Thus the invalid states can be eliminated. Excitation Table of the SR Latchthe excitation behaviour of the sequential circuits, These are used in synthesis (design) of sequential circuits, which we Shall see latter, The excitation of the SR latch is as follows: Excitation Table Note:Indeterminate = not used K-map for Q,-: Qu-1=5+R.Q, 16. Design MOD-5 counter with state and timing diagram. [24142] Ans: Step 1: Determine the number of flip flop needed Flip flop required are 3 Step 2: Type of flip flop to be used: JK flip flop‘QCc(MsB) i QB ‘QA (LSB) Step 6: Timing Diagram 1 On Op Qc17. Design a 4-bit serial into parallel-out shift register with timing diagram. [342] Ans: Serial In - Parallel Out Shift In serial In-Parallel out shift register, data input is done serially from one of the left most/right most flip-flop. But data output is done simultaneously though all the flip-flop in a single clock pulse. In SIPO shift register, if n bit data is to input (load) and to receive all bits at the output we will require 'p + 1' clock pulse, Figure below illustrate the logic diagram of a serial in shift right parallel out shift register where serial data input is provided through the Dy input line of FF, and the parallel] output is transferred through the Qe Qu Q: Qs output lines of the flip-flops. FF, FF), FF; and FF) respectively. We should note that the output lines of the respective flip-flop will be enabled only when the register is completely loaded Le. after the register is loaded in a next clock pulse the content of a register are transferred simultaneously and the register will be cleared in a single clock pulse. A construction of a four-bit serial in - parallel out register is shown below. a Q, a a Figure: A 4-bit serial ir/parallel out shift registers In the table below, we can see how the four-bit binary number 100] is shifted to the Q outputs of the register. Table: Shift 0 pea g E | ef I> obvi i" § i Figure 2 Output Waveform of m-bit Right-Shift SIPO Shirt Register.Group "Co Attempt any TWO questions, 18. Write difference between PLA and PAL. Design a PLA circuit given functions. FI (A, B,C) = £@, 3,5) F(A, B, C)= E00, 4,5, 7). Design PLA program table also. Ans: Difference between PAL and PLA The availablity of PAL is less prolific | The availablity of PLA im more The flexibility of PAL functions | The implemented in PAL is large ‘The speed of PAL is slow D flip is actually a slight modification of the above explained clocked SR flip-flop. From the figure you can see that the D input is sonnected to the S input and the complement of the D input is connected to the R input. ‘The D input is passed on to the lip flop when the value of CP is ‘I! When CP is HIGH, the flip flop moves to the SET state. If itis , the flip flop switches to the CLEAAR state,etn a on ee As long as the clock input C = 0, the SR lateh has both inpats equal to 0 and it can’t change its state regardless of the value of D. When C is 1, the latch is placed in the set or reset state based on the value of D, If D= 1, the Q output goes to 1. If D = 0, the Q output goes to 0. Figure: D Flip Flop using NAND GateMaster-Slave Flip Flop Cirenit Before knowing more about the master-slave flip lop you have know more on the basics of a J-K flip op and S-R flip flop/. know more about the flip flops, click an the link below, Master-slave flip flop is designed using two separate flip flops. Ou of these, one acts as the aster and the other as.a slave. The figure of master-slave J-K flip flop is shown below. 5 From the below. figure you can see that both the J-k flip flops Presented in a series connection. The output of the master J-K flip flap fed to the input of the slave J-K flip flop. The output of the slave J-k fli flop is given as a feedback to the input of the master J-K flip flop. clock pulse [CLK] is given to the master J-K flip flop and it is through a NOT Gate and thus inverted before passing it to the slave J-K flip flop. (b) Block diagram Figure: Master-Slavé Flip-flop20. Wi When Clock = 1, the master J-K flip flop gets disabled. The clock input of the master input will be the opposite of the slave input. So the master flip flop output will be recognized by the slave flip Nop only when the dock value becomes. Thus, when the clock pulse males a transition from 1 to 0, the locked outputs of the master flip flop are fed through to the inputs of the slave flip-flop making this flip flop edge or pulse~ To understand better take a look at the timing diagram Flip-flop output can change Figure: Timing Diagram of Master-Slave Flip-Flop ‘Thus, the circuit accepts the value in the input when the clock is HIGH, and passes. the data to the output on the falling-edge of the clock signal. This makes the Master-Slave }-k flip flop a Synchronous device as it only passes data with the timing of the clock signal. Write down the difference between asynchronous and synchrounous counter. Design a 4-bit binary ripple counter along with its circuit, state and timing diagram. {1+71 Ans: ‘The following table shows the difference between the Asynchronous and Synchronous Counter:_Asynchronous/Ripple Counter _Syechroncas Count Flip flop are connected in such als There fs no connection bet output of the first flip clock of next flip-flop. Standard logic package availa for synchronous. The following is a 4-bit asynchronous binary counter and its tin any diagram for one cycle. It works exactly the same way as a 2-bit or 3b asynchronous binary counter mentioned above, except it has 16 «1 due to the fourth flip-flop.Working of asynchronous up coun exh below Let assume tat the 4 outputs of the lip flops ae italy (0. When he risng ge the clk ple is appli othe FO then he cpt QO wil chang log and thet hack pul change te (0 ouput log 0. This means the oop te of the cock pulse ges (change fron for ony. Aa the (fof FRO sonnet othe dock input of FF then the clock input of nd plop wil cme 1, hiss the ott fF by hgh ih» 1), whch indices the val 20 ns way the ext cok pulse will make the QO bere high agi. Go now both Qh and (are gh ths results in making the 4 bit outpat HOU Now if we apply the out lock pul twill make the Qh an (to low slat an hg the FF Ste output wl ce 02 Ag this circuit is 4 bit up counler, the outptssequenceof binary vals from, {,23...15 dou