Module 4
Memory System-Basic Concepts
The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
For example, a computer that generates 16-bit addresses is capable of
addressing up to 216 = 64K (kilo) memory locations.
Machines whose instructions generate 32-bit addresses can utilize a memory that
contains up to 232 = 4G (giga) locations.
The number of locations represents the size of the address space of the computer.
Memory System-Basic Concepts
The connection between the processor and its memory consists of address, data, and
control lines, as shown in Figure
Memory System-Basic Concepts
A useful measure of the speed of memory units is the time that elapses between
the initiation of an operation to transfer a word of data and the completion of that
operation. This is referred to as the memory access time.
Memory cycle time, is the minimum time delay required between the
initiation of two successive memory operations, for example, the time between
two successive Read operations.
The processor of a computer can usually process instructions and data faster
than they can be fetched from the main memory. Hence, the memory access time
is the bottleneck in the system. One way to reduce the memory access time is to
use a cache memory.
Memory System-Basic Concepts
Cache Memory is a small, fast memory inserted between the larger, slower main
memory and the processor. It holds the currently active portions of a program and
their data.
Virtual memory is another important concept related to memory organization.
With this technique, only the active portions of a program are stored in the main
memory, and the remainder is stored on the much larger secondary storage device.
Main Memory/Primary Memory
◼ It is the memory used to store programs and data during the
computer operation.
◼ The principal technology is based on semiconductor integrated
circuits.
◼ It consists of RAM and ROM chips.
◼ RAM is the main, volatile memory used for active, temporary
data storage, ROM is a non-volatile type of primary memory that
stores essential startup(BIOS) instructions.
◼ RAM chips are available in two form static and dynamic.
6
RAM-Internal Organization of Memory Chips
Organization of bit cells in a memory chip- 16x8 Organization
Figure is an example of a very small memory circuit consisting of 16 words of 8 bits each.
Organization of bit cells in a memory chip- 16x8 Organization
of 128 memory cells.
The memory circuit in the previous Figure stores 128 bits and requires 14 external
connections for address(4), data(8), and control lines(2). It also needs two lines for
power supply and ground connections. (2). Totally 16 ext. connections.
Consider now a slightly larger memory circuit, one that has 1K (1024)
memory cells.
This circuit can be organized as a 128 × 8 memory, requiring a total of 19
external connections. address(7), data(8), and control lines(2), power supply
and ground connections. (2). Totally 19 ext. connections.
The same number of cells can be organized into a 1K×1 format
address(10), data(1), and control lines(2), power supply and ground connections.
(2). Totally 15 ext. connections
Organization of a 1K × 1 memory chip.
The required 10-bit address is divided into two groups of 5 bits each to form the row and
column addresses for the cell array. A row address selects a row of 32 cells, all of which
are accessed in parallel. But, only one of these cells is connected to the external data
line, based on the column address.
Static Memories
Memories that consist of circuits capable of retaining their state as long as
power is applied are known as static memories
A static RAM cell.
Dynamic RAMs
Static RAMs are fast, but their cells require several transistors. Less expensive and
higher density RAMs can be implemented with simpler cells. But, these simpler cells
do not retain their state for a long period, unless they are accessed frequently for Read
or Write operations. Memories that use such cells are called dynamic RAMs
(DRAMs).
A single-transistor dynamic memory cell.
Internal organization of a 32M × 8 dynamic memory chip
Design of 256-Megabit DRAM chip, using 32M × 8 organization
Fast Page Mode
When the DRAM in the previous figure is accessed, the contents of all 16,384 cells in the
selected row are sensed, but only 8 bits are placed on the data lines, D7−0. This byte is
selected by the column address, bits A10−0.
A simple addition to the circuit makes it possible to access the other bytes in the same
row without having to reselect the row.
Each sense amplifier also acts as a latch. When a row address is applied, the contents of
all cells in the selected row are loaded into the corresponding latches. Then, it is only
necessary to apply different column addresses to place the different bytes on the data
lines.
All bytes in the selected row can be transferred in sequential order by applying a
consecutive sequence of column addresses under the control of successive CAS signals.
be transferred at a much faster rate than can be achieved for transfers involving random
addresses. The block transfer capability is referred to as the fast page mode feature.
Synchronous DRAMs
Structure of Larger Memories
To design memory of 2M words of 32 bits each using 512K × 8 static memory chips
Given To Design
219 is almost 512K
512K*8= 4096K 2M*32=64M
512K*8*16=64M
Hence include 16 no. of 512K × 8 static memory chips
Structure of Larger Memories
Memory Hierarchy
Very fast memory can be
implemented using
static RAM chips.
Main memory can be
built with dynamic RAM
technology.