Direct Memory Access (DMA)
DMA is a process of communication for data transfer between memory and input/output,
controlled by an external circuit called DMA controller, without involvement of CPU.
8085 MP has two pins HOLD and HLDA which are used for DMA operation.
First, DMA controller sends a request by making Bus Request (BR) control line high. When
MP receives high signal to HOLD pin, it first completes the execution of current machine
cycle, it takes few clocks and sends HLDA signal to the DMA controller.
After receiving HLDA through Bus Grant (BG) pin of DMA controller, the DMA controller
takes control over system bus and transfers data directly between memory and I/O without
involvement of CPU. During DMA operation, the processor is free to perform next job
which does not need system bus.
At the end of data transfer, the DMA controller terminates the request by sending low signal
to HOLD pin and MP regains control of system bus by making HLDA low.
Advantages & Disadvantages of DMA
Advantages
• DMA allows a peripheral device to read from/write to memory without going through the
CPU.
• DMA allows faster processing since the processor can be working on something else while
the peripheral can be populating memory.
• DMA enables more efficient use of interrupts.
• High transfer rates.
• DMA capable device can communicate directly with memory.
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Disadvantages
• Cost of DMA hardware.
• Data has to be stored in continuous memory locations.
• DMA controller is slow in comparison to CPU.
Application of DMA
• DMA has been a built-in feature of PC architecture since the introduction of the original
IBM PC.
• PC-based DMA was used for floppy disk I/O in the original PC and for hard disk I/O in
later versions.
• PC-based DMA technology, along with high speed bus technology, is driven by data
storage, communications, and graphics needs-all of which require the highest rates of data
transfer between system memory and I/O devices.
• Applications areas are: cinemas, theatres, hotels, railway stations, shopping centres, trade
shows, museums & many more.
DMA Data Transfer Modes
DMA (Direct Memory Access) is a method of data transfer between a peripheral device
and the main memory without the intervention of the CPU. There are three types of DMA
transfer modes:
a) Single transfer mode: In this mode, the DMA controller transfers a single block of data
from the source to the destination. Once the transfer is complete, the DMA controller
releases the control of the bus.
b) Burst transfer mode: In this mode, the DMA controller transfers a block of data in bursts.
The DMA controller takes control of the bus and transfers data for a fixed number of cycles
or until the entire block is transferred. Once the transfer is complete, the DMA controller
releases the control of the bus.
c) Cycle Stealing transfer mode: In this mode, the DMA controller steals CPU cycles to
transfer data. When a peripheral requests a transfer, the DMA controller temporarily halts
the CPU and takes control of the bus to transfer data. Once the transfer is complete, the
DMA controller releases the control of the bus, and the CPU resumes its operation.
Each mode has its own advantages and disadvantages. Single transfer mode is the simplest
and most reliable mode, but it is also the slowest. Burst transfer mode is faster than the
single transfer mode but requires more hardware support. Cycle stealing mode is the fastest
mode but can interfere with the CPU's operation, and it is also the most complex mode to
implement. The choice of DMA transfer mode depends on the specific requirements of the
application.
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8237 DMA Controller and Interfacing
8237 is a programmable DMA controller present in 40 pin package.
8237 has a 4 channels with channel capable of transferring 64kb.
It must interface with two types of devices : the MPU and peripherals such as floppy
disks.
DMA plays two roles in a system : It is an I/O to the microprocessor (slave mode) and
it is a data transfer processor to peripherals such as floppy disks (master mode).
Many of its signals that are input in the I/O mode become outputs in the processor
mode.
It also needs additional signals lines to communicate with the address 64 k data bytes
and these signals must be generated externally by using latches and buffers.
The 8237 is complex device.
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Block diagram of 8237 DMA controller
Fig: The block diagram of 8237 DMA controller
The 8237 A contains three blocks of control logic.
Timing Control: It generates internal timing and external control signal for the 8237A.
Program Command Control: It decodes various commands given to 8237A by the
microprocessor before servicing a DMA request. It also decodes the 'Mode
control word, which is used to select the type of DMA during the
servicing.
Priority Encoder: It resolves the priority between DMA channels requesting services
simultaneously.
The 8237 contains 344-bits internal memory in the form of registers.
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8237 Pin Configuration
DMA Signals
CLK: System clock
̅̅
𝐂𝐒̅̅: Chip select (decoder output)
RESET: Clears registers, sets mask register
READY: 0 for inserting wait states
HRQ: DMA request out to MP to control system buses
HLDA: Hold Acknowledgement by MP
DREQ3 – DREQ0: DMA request input for each channel
DB7-DB0: Data bus pins
̅̅̅̅̅
𝐈𝐎𝐑: Bidirectional pin used during programming
and during a DMA write cycle
̅̅̅̅̅̅: Bidirectional pin used during programming
𝐈𝐎𝐖
and during a DMA read cycle
̅̅̅̅̅̅
𝐄𝐎𝐏: End of process is a bidirectional signal used as input to
terminate a DMA process or as output to signal
the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address enable signal
ADSTB: Address strobe
̅̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐑: Memory read output used in DMA read cycle
̅̅̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐖: Memory write output used in DMA write cycle
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Interfacing 8237 DMA Controller with 8085.
The DMA is used to transfer data bytes between I/O (such as Floppy disk) and system memory
̅̅̅̅̅ ,
(or from memory to memory) at high speed. It includes 8 data lines, four control signals (𝐼0𝑅
̅̅̅̅̅̅
𝐼𝑂𝑊 , ̅̅̅̅̅̅̅̅̅
𝑀𝐸𝑀𝑅 , and ̅̅̅̅̅̅̅̅̅̅
𝑀𝐸𝑀𝑊 ), and eight address lines (A7-A0).
However, it needs 16 address lines to access 64K bytes. Therefore, an additional 8 lines must
be generated as shown in Figure 1 below.
When a transfer begins, the DMA places the low-order byte on the address bus and the high-
order byte on the data bus and asserts AEN (Address Enable) and ADSTB (Address Strobe).
These two signals are used to latch the high-order byte from the data bus; thus, it places the 16-
bit address on the system bus.
After the transfer of the first byte, the latch is updated when the lower byte generates a carry
(or borrow). Figure 1 shows two latches: one latch (373 # 1) to latch a high-order address from
the data bus by using the AEN and ADSTB signals, and the second latch (373 #2) to
demultiplex the 8085 bus and generate the low-order address bus by using the ALE (Address
Latch Enable from the 8085) signal.
The AEN signal is connected to the ̅̅̅̅
𝑂𝐸 signal of the second latch to disable the low-order
address bus from the 8085 when the first latch is enabled to latch the high-order byte of the
address.
Figure 1
Figure 1: Interfacing 8237A with 8085