Practical Question

The document outlines three design tasks for a Chip Design Associate module in Verilog. Task 1 involves creating a parameterized N-bit adder, Task 2 requires designing a 4-to-2 priority encoder, and Task 3 focuses on writing a D Flip-Flop with an asynchronous reset. Each task specifies functionality requirements and verification methods, with allocated points for completion.

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Practical Question

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mrkngyt00

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Module

REGN NO.: LEVEL: Code:

CHIP DESIGN ASSOCIATE (O LEVEL) PR 2

Q1. Design a parameterized N-bit adder in Verilog using a parameter for bit-
width and verify its functionality for 4-bit and 8-bit cases.

(25)

Q2. Design a 4-to-2 priority encoder using Verilog HDL.

• The encoder should take a 4-bit input (in[3:0]) where in[3] has the
highest priority and in[0] the lowest.
• Output a 2-bit binary code (out[1:0]) representing the position of
the highest-priority asserted input.
• If no inputs are high, output should be 00.
(25)

Q3. Write Verilog code for a D Flip-Flop with an asynchronous active-high reset.
The flip- flop should sample the input D on the rising edge of the clock clk,
and reset the output Q to 0 immediately when the reset rst is asserted.
Verify the design by performing both behavioral and post-synthesis
simulations, and confirm the flip-flop behaves correctly in both cases.

(30)

-------oooo-------

__________

O LEVEL/PR-2 Page 2 Set-01/01-26

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Practical Question

Uploaded by

Practical Question

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Module

REGN NO.: LEVEL: Code:

CHIP DESIGN ASSOCIATE (O LEVEL) PR 2

Q2. Design a 4-to-2 priority encoder using Verilog HDL.

O LEVEL/PR-2 Page 2 Set-01/01-26

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