WHAT IS LOGIC GATE ?

A logic gate is a device that acts as a building block for digital circuits. They perform basic logical
functions that are fundamental to digital circuits. Most electronic devices we use today will have
some form of logic gates in them. For example, logic gates can be used in technologies such as
smartphones, tablets

HOW THE LOGIC GATES FUNCTION ?

In digital electronics, a gate is defined as an electronic circuit having only one output but two or
more input. These electronic circuits consist of p-n junction diodes, transistors and resistors. Gates
work with only two voltage levels at their input and output terminals with respect to ground or
common, ie., the input and output voltages can have only two values. These values are typically
chosen to be 0 Volt (zero volt) and some positive dc voltage value, say +5 Volt. For the 0 Volt logic
level, it is customary to use the term that has two or more LOW (or the letter L) and the symbol 0
(zero). While referring to the positive voltage level, we use the term HIGH (or the letter H) or the
number 1 (one). A signal appears at the output of a gate only for certain combinations of the input
signals. This leads to a number of different types of gates. Gates enable us to perform several tasks
which involve logical decision making, hence the nomenclature logic gates.

CLASSIFICATION OF LOGIC FAMILY :-

Logic families are mainly classified as Bipolar Logic Families and Unipolar Logic Families.

Bipolar Logic Families :- It mainly uses bipolar devices like diodes, transistors in addition to
passive elements like resistors and capacitors. These are sub classified as saturated bipolar logic
family and unsaturated bipolar logic family.
Saturated Bipolar Logic Family :- In this family the transistors used in ICs are driven into
saturation. For example:
Transistor-Transistor Logic (TTL)
Resistor-Transistor Logic (RTL)
Direct Coupled Transistor Logic (DCTL)

Diode Transistor Logic (DTL)

High Threshold Logic(HTL)
Integrated Injection Logic (IIL or I 2 L)

Unsaturated bipolar logic family :- In this family the transistors used in IC is not driven into
saturation. For example:
Schottky TTL
Emitter Coupled Logic(ECL)

Unipolar Logic Families :- It mainly uses Unipolar devices like MOSFETs in addition to passive
elements like resistors and capacitors. These logic families have the advantages of high speed and
lower power consumption than Bipolar families. These are classified as:

PMOS or P-Channel MOS Logic Family

NMOS or N-Channel MOS Logic Family
CMOS Logic Family

FEATURES OF LOGIC FAMILIES :-

TTL - Transistor-Transistor Logic: Standard logic family; used for the longest time.

ECL - Emitter Coupled Logic: Suitable for systems requiring high-speed operations.
MOS - Metal Oxide Semiconductor Logic: Suitable for systems with high component density.
CMOS - Complementary Metal Oxide Semiconductor Logic: Suitable for systems with low power
consumption (VLSI circuits). Gradually becomes the dominant logic family.

CMOS :-
CMOS or Complementary Metal Oxide Semiconductor is a combination
of NMOS and PMOS transistors that operates under the applied electrical field. The structure of
CMOS was initially developed for high density and low power logic gates.

The NMOS and PMOS are the types of Metal Oxide Semiconductor Field Effect Transistors (MOSFET).
The CMOS transistors are used in various applications, such as amplifiers, switching circuits, logic
circuits, Integrated circuit chips, microprocessors, etc.
The importance of CMOS in semiconductor technology is its low power dissipation and low operating
currents. Its manufacturing requires fewer steps as compared to the Bipolar Junction transistors.

As discussed, CMOS is a combination of NMOS and PMOS transistors. Let's discuss a short description
of the NMOS and PMOS transistor before beginning with CMOS.

NMOS

The symbol of the NMOS transistor is shown below:

The n-channel MOSFET is called NMOS. It has a substrate of p-type, which consists of majority carriers
holes. The n-channel consists of majority carriers electrons. The flow of electrons is fast as compared
to holes. Hence, NMOS transistors are more rapid than PMOS transistors.

PMOS

The symbol of the PMOS transistor is shown below:

The p-channel MOSFET is called PMOS. It has a substrate of n-type, which consists of majority carriers
electrons. When a negative voltage is applied to the gate end of the PMOS, it repels the electrons.
The attraction of holes results in the formation of the channel called the p-channel. The channel is
formed between the source and drain.

The slow flow of holes makes the current controlled process of PMOS easy as compared to NMOS
transistors.

CMOS Logic Gates :-

CMOS logic gates are manufactured using the combination of NMOS and PMOS field-effect
transistors. In the case of NMOS logic gates, we generally use NMOS depletion type transistors as the
load resistance. In CMOS logic gates, we use a complementary structure in which one transistor acts
as a load to the other transistor.

The NMOS transistors are designed to work as positive logic elements, while PMOS works as negative
logic elements. It means that both the transistors in a CMOS perform complementary logic functions.

Features of CMOS Logic Gates :-

The features of CMOS Logic Gates are listed below:

o Reduced cost as it requires only a single power supply.

o Large logic swing.
o Large fan-out capability.
o Very high noise margin.
o Lower propagation delay
o High speed as compared to NMOS transistors.
 o Lower power dissipation.
o Excellent temperature stability.
o Less packaging density.

Types of CMOS logic gates :-

The Complementary Metal Oxide Semiconductors are categorized as:

o CMOS Inverter
o CMOS NAND
o CMOS NOR
o CMOS Operational Amplifiers

CMOS Inverter :-

The CMOS inverter is formed by connecting the PMOS and NMOS transistors in cascade, as shown
below:

CMOS INVERTER

The top of the CMOS inverter is the PMOS transistor, while the bottom transistor is NMOS. The
positive voltage of +VDD at the gate input of the NMOS transistors will turn it ON, while the same
positive voltage at the gate input of the PMOS transistor will keep it OFF. Similarly, the voltage of 0
volts at the gate input of the NMOS transistors will keep it OFF, while the same 0 at the gate input of
the PMOS transistor will turn it ON.
It means that NMOS transmits logic 1 or VDD, and PMOS transmits logic 0.

CMOS NAND :-

CMOS NAND is a combination of NMOS NAND and PMOS NOR. It consists of an NMOS NAND gate
with the PMOS NOR as its load. CMOS NAND gate can also include a PMOS NOR with the NMOS NAND
as its load. It means that NMOS and PMOS transistors' combination in the desired manner forms a
CMOS logic gate.

The circuit diagram of CMOS NAND is shown below:

The input terminal of the transistors is A and B, as shown above. If A = 0 and B = 0, the NMOS
transistors will remain off, and the two PMOS transistors will conduct.

Consider the NOR table shown below:

A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

It clearly shows that the output is 1 when the two inputs are 0. Hence, PMOS NOR will conduct. The
output Y will be:

Y = logic 1 = VDD
Similarly, when both the input is 1, the NMOS NAND will conduct, and PMOS NOR will remain OFF.
But, the output will be 0 because the power will pass to the ground.

Consider the CMOS NAND table shown below:

A B CMOS NAND

0 0 1

0 1 1

1 0 1

1 1 0

CMOS NOR

CMOS NOR logic gate is a combination of NMOS NOR and PMOS NAND. The circuit diagram is shown

When both the input A and B are 0, NMOS NOR will remain OFF, and PMOS NAND will conduct. It
means that transistors T1 and T2 will be OFF, while T3 and T4 will conduct. Thus, the output will be
logic 1 when the voltage VDD reaches through the conduction of transistors T3 and T4.

CMOS NOR will conduct only when both the inputs are 0 as discussed above. At all the other input
conditions, the output will be 0, as listed below:
 A B CMOS NOR

0 0 1

0 1 0

1 0 0

1 1 0

CMOS Operational Amplifiers

The CMOS structures can also be used as an amplifier when the operating point is fixed in the active
region.

Let's consider an example of a CMOS differential amplifier using constant current sources.
Advantages of CMOS
Let's discuss the advantages of the Complementary Metal Oxide Semiconductor, which are listed
below:

o Very low power dissipation

There is no continuous current path from the positive terminal of the transistor to its
negative terminal throughout the circuit except the switching instants. Hence, it has the
least amount of power dissipation.
o Reduced circuit complexity
CMOS requires fewer components, due to which the circuit complexity reduces.
o Produces very less heat
CMOS produces significantly less heat as compared to other transistors, such as NMOS and
TTL (Transistor-Transistor Logic). Other transistors have some standing current even in the
unchanged state, while CMOS does not have.
o Low static power Consumption
In an ideal state, CMOS dissipates almost zero or no power as compared to other circuits. It
means that it only dissipates power while switching. The lesser dissipation results in lower
power consumption. Hence, CMOS has very low static power consumption.
o Temperature stability
CMOS family is stable in a wider temperature range compared to other logic circuits, such as
TTL. The operating range of CMOS is around -55 degrees Celsius to 125 degrees, while TTL is
25 to 70 degrees Celsius.
o Improved Noise immunity
Noise immunity refers to the ability of a system to function in the presence of noise
interference. CMOS has the highest noise immunity as compared to the circuit of logic
families. Hence, it is highly preferred in high noise automotive applications.
o High fan-out
Fan out specifies the input gates driven by the output of the other gate. It means the
highest number of input gates of a particular type to which the output can be connected.
The fan-out feature measures the load driving ability of a logic gate. Thus, CMOS has a high
fan out.
Applications of CMOS
The applications of CMOS are listed below:

o Integrated Circuits
CMOS consumes less current than other logic devices, such as TTL. Hence, the use of CMOS
in the Integrated Circuit applications forms the production of ICs that has lower
consumption and low dissipation.
o Chip designing
The use of CMOS in chip designing allows the high-density logic functions to be integrated
on a chip.
o Microprocessor designing
CMOS requires current only during the switching state. It means that CMOS uses the power
efficiently. Hence, CMOS is used in most modern processors, such as microprocessors.
o ASIC designing
It stands for Application Specific Integrated Circuits. CMOS is considered the standard
transistor for the fabrication of chips. Hence, it is used in ASIC designing.
o CPU Memories
The two major advantages of CMOS are high noise immunity and low static power
consumption. Due to this, it is used in the CPU (Central Processing Units) Memories.

Programmable Logic Devices :-

Programmable Logic Devices PLDs are the integrated circuits. They contain an array of AND gates &
another array of OR gates. There are three kinds of PLDs based on the type of array s, which has
programmable feature.

 Programmable Read Only Memory

 Programmable Array Logic
 Programmable Logic Array
The process of entering the information into these devices is known as programming. Basically, users
can program these devices or ICs electrically in order to implement the Boolean functions based on
the requirement. Here, the term programming refers to hardware programming but not software
programming.
Programmable Read Only Memory PROM
Read Only Memory ROM is a memory device, which stores the binary information permanently. That
means, we can’t change that stored information by any means later. If the ROM has programmable
feature, then it is called as Programmable ROM PROM. The user has the flexibility to program the
binary information electrically once by using PROM programmer.
PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block
diagram of PROM is shown in the following figure.

Here, the inputs of AND gates are not of programmable type. So, we have to generate 2 n product
terms by using 2n AND gates having n inputs each. We can implement these product terms by using
nx2n decoder. So, this decoder generates ‘n’ min terms.
Here, the inputs of OR gates are programmable. That means, we can program any number of required
product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore,
the outputs of PROM will be in the form of sum of min terms.

Example
Let us implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function is having three variables X,
Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two
functions. The corresponding PROM is shown in the following figure.
Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of
all these min terms. But, only the required min terms are programmed in order to produce the
respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections.

Programmable Array Logic PAL

PAL is a programmable logic device that has Programmable AND array & fixed OR array. The
advantage of PAL is that we can generate only the required product terms of Boolean function instead
of generating all the min terms by using programmable AND gates. The block diagram of PAL is
shown in the following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those
inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each OR gate
will be of fixed type. Hence, apply those required product terms to each OR gate as inputs. Therefore,
the outputs of PAL will be in the form of sum of products form.

Example
Let us implement the following Boolean functions using PAL.
A=XY+XZ′
A=XY′+YZ′
The given two functions are in sum of products form. There are two product terms present in each
Boolean function. So, we require four programmable AND gates & two fixed OR gates for producing
those two functions. The corresponding PAL is shown in the following figure.
The programmable AND gates have the access of both normal and complemented inputs of
variables. In the above figure, the inputs X, Y, Z & Z′ are available at the inputs of each AND gate. So,
program only the required literals in order to generate one product term by each AND gate. The
symbol ‘X’ is used for programmable connections.
Here, the inputs of OR gates are of fixed type. So, the necessary product terms are connected to
inputs of each OR gate. So that the OR gates produce the respective Boolean functions. The symbol
‘.’ is used for fixed connections.
Programmable Logic Array PLA
PLA is a programmable logic device that has both Programmable AND array & Programmable OR
array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those
inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are also programmable. So, we can program any number of required
product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore,
the outputs of PAL will be in the form of sum of products form.

Example
Let us implement the following Boolean functions using PLA.
A=XY+XZ′
B=XY′+YZ+XZ′
The given two functions are in sum of products form. The number of product terms present in the
given Boolean functions A & B are two and three respectively. One product term, Z′X is common in
each function.
So, we require four programmable AND gates & two programmable OR gates for producing those
two functions. The corresponding PLA is shown in the following figure.

The programmable AND gates have the access of both normal and complemented inputs of
variables. In the above figure, the inputs X’, Y, Y′, Z & Z′, are available at the inputs of each AND gate.
So, program only the required literals in order to generate one product term by each AND gate.
All these product terms are available at the inputs of each programmable OR gate. But, only program
the required product terms in order to produce the respective Boolean functions by each OR gate.
The symbol ‘X’ is used for programmable connections.
Field Programmable Gate Array (FPGA) :-
FPGA stands for Field Programmable Gate Array which is an IC that can be programmed to perform
a customized operation for a specific application. They have thousands of gates. In the field of VLSI
FPGAs have been very popular. Languages such as VHDL and Verilog are used to write the code for
FPGA programming.
Architecture :
It consists of thousands of fundamental elements called Configurable Logic Blocks (CLBs) which are
surrounded by a system of programmable interconnects known as a fabric, which directs signal
between CLBs and I/O blocks interface between the FPGA and external device.

Logic Block consists of Multiplexers, Full Adders, D flip flop, a lookup table (LUT) which is the basic
building block of the FPGA. LUTs determines the output for any given source of input. LUTs with 4-6
input bits are widely used and can even go up to 8 bits after experiments. D flip flop stores the
output of LUT.
Types of FPGA
Based on their applications FPGA are classified as :

Low-End FPGAs –
They consume less power than the other two and are less complex as no of gates are less.

Mid-Range FPGAs –
They consume more power than low-end FPGAs and have more number of gates, so more complex.
They provide a balance between performance and cost.

High-End FPGAs –
They have a large gate density, so are more complex than mid-range. Their performance is better
than low-end and mid-range FPGAs be Some High-End FPGAs
Advantages :-
FPGAs provide better performance than a general CPU as they are capable of handling parallel
processing.
FPGAs are reprogrammable.
They are cost-efficient.
FPGAs allow you to finish the development of your product in a very short time, so they are
available in the market in a shorter time.

Disadvantages :-
They have high power consumption and programmers do not have any control over power
optimization.

The programming of FPGA is not as simple as C programming.

They are only used where the production volume is low.

Applications :-
FPGAs are used in defense equipment for image processing in SDRs, for ASIC prototyping, for high-
performance computers, in wireless communication such as WiMAX, WCDMA, etc. and in various
equipment used for diagnosis and therapy in the medical field. They are also used in consumer
electronics like flat panel displays, residential set-top boxes, etc.

VLSI Design Flow :-

Very Large Scale Integration(VLSI) is the process of making Integrated Circuits (ICs) by combining a number
of components like resistors, transistors, and capacitors on a single [Link] Design is an iterative cycle.
Designing a VLSI Chip includes a few problems such as functional design, logic design, circuit design, and
physical design. The design is verified for accuracy by the process of simulation. If any design errors are
found at any stage of verification, at least one of the previous design steps must be repeated to correct the
error during the process of designing.

Description of VLSI Design Flow Chart:

1. System specification: The objective of the desired final product is written in this step. During
system specification, the designated cost of the system, its performance, architecture, and how the
system will communicate with the external world are to be determined. During this step, the design
specification should be provided by the users or clients.

2. Architectural design: The basic architecture of the desired design must meet the system
specifications of the desired design. The architecture of the desired design is decided and the layout
for the same is designed by design engineers. Architectural design includes the integration of
analog and mixed-signal blocks, memory management, internal and external communication,
power requirements, and choice of process technology and layer stacks
 Figure :- VLSI Design Flow

3. Functional design or Behavioural design: It consists of refining the design specification of the
desired design in order to design the functional behavior of the desired system. The main objective
of this is to generate design a high-performance architectural design within the cost requirements
posed by the specifications.
4. Logic Design: In this step, the structure of the desired design is added to the behavioral
representation of the desired design. The main specifications to be considered for logic design are
logic minimization, performance enhancement, and testability. Logic design must also consider the
problems associated with test vector generation, error detection, and error correction. Many logic
synthesis tools have been developed for the automation of the process of logic design.

5. Circuit Design: In this step, the logic blocks of the desired design are replaced by the electronic
circuits, which are consists of electronic devices such as resistors, capacitors, and transistors. Circuit
simulation of the desired design is done at this stage, in order to verify the timing behavior of the
desired system. Kirchhoff’s laws are used to know the behavior of the electronic circuit in terms of
node voltages and branch circuits. The result of integrodifferential equations is then solved in
discrete- time. SPICE is a well-known program for circuit simulation.

6. Physical Design: In this step, the actual layout of the desired system is done, where all the
components will be placed in the circuit and all these components are interconnected. The actual
layout of the desired system can affect the area, correctness, and performance of the final desired
product. The correctness of the chip is also controlled by the physical design. A circuit design that
passes the test of a circuit simulator may be faulty after it has been packaged. This is because of
geometric design rule errors. These design rules must be followed to ensure the correctness of the
chip fabrication. Errors such as short circuits, open circuits, open channels, etc may result if the
design rules are not respected.

7. Fabrication: After the actual layout and verification of the desired design, the design is sent for
manufacturing. The handoff of the desired design to the manufacturing process is called tapeout.
Generation of the data for manufacturing is referred to as streaming out. The desired design is onto
the different layers of the design using the photolithographic process. ICs are manufactured on
round silicon wafers with a diameter from 200mm to 300mm, these ICs are then tested and are
marked as either functional or defective ICs.

8. Packaging and Testing: After fabrication of desired design, functional chips are then packed.
Packaging is configured early in the desired design process and the application along with the cost
and form factor requirements. Packaged types may include Dual In-Line Packaged (DIPs), Pin Grid
Array (PGAs), and Ball Grid Arrays (BGAs). After a die is positioned in the package cavity, its pins are
connected to the pins of the package, e.g., with wire bonding or solider bumps (flip-chip). The
package of the desired design is then sealed and then sent to the end-users or clients.
What is HDL?
HDL stands for Hardware Description Language. It is a programming language that is used to
describe, simulate, and create hardware like digital circuits (ICS). HDL is mainly used to discover the
faults in the design before implementing it in the hardware.
The main advantage of HDLs is that it provides flexible modeling capabilities and can express the
large complex designs (>107 gates).
Today, there are many HDLs available in the market, but VHDL and Verilog are the most popular
HDLs.

HDLs are indeed similar to programming languages but not exactly the same. We
utilize a programming language to build or create software, whereas we use a
hardware description language to describe or express the behavioral characteristics
of digital logic circuits.
We utilize HDLs for designing processors, motherboards, CPUs (i.e., computer chips),
as well as various other digital circuitry.

What is VHDL?
VHDL stands for Very High-Speed Integration Circuit HDL (Hardware Description Language). It is an
IEEE (Institute of Electrical and Electronics Engineers) standard hardware description language that
is used to describe and simulate the behavior of complex digital circuits.
The most popular examples of VHDL are Odd Parity Generator, Pulse Generator, Priority Encoder,
Behavioral Model for 16 words, 8bit RAM, etc.
VHDL supports the following features:
o Design methodologies and their features.

o Sequential and concurrent activities.

o Design exchange
o Standardization
o Documentation
o Readability

o Large-scale design
o A wide range of descriptive capability
Why VHDL?
VHDL is used for the following purposes:
1. For Describing hardware

2. As a modeling language
3. For a simulation of hardware
4. For early performance estimation of system architecture
5. For the synthesis of hardware

Advantages of VHDL :-
A list of advantages of VHDL is given below:
It supports various design methodologies like Top-down approach and Bottom-up approach.
It provides a flexible design language.
It allows better design management.
It allows detailed implementations.

It supports a multi-level abstraction.

It provides tight coupling to lower levels of design.
It supports all CAD tools.
It strongly supports code reusability and code sharing.

Disadvantages of VHDL:-
A list of disadvantages of VHDL is given below:
It requires specific knowledge of the structure and syntax of the language.
It is more difficult to visualize and troubleshoot a design.
Some VHDL programs cannot be synthesized.
VHDL is more difficult to learn.

What is Verilog?
Verilog is also a HDL (Hardware Description Languages) for describing electronic circuits and
systems. It is used in both hardware simulation and synthesis.
The most popular examples of Verilog are network switch, a microprocessor, a memory, a simple
flip-flop, etc.

Difference between VHDL and Verilog

VHDL Verilog

It allows the user to define data types. It does not allow the user to define data types.

It supports the Multi-Dimensional array. It does not support the Multi-Dimensional array.

It allows concurrent procedure calls. It does not allow concurrent calls.

A mod operator is present. A mod operator is not present.

Unary reduction operator is not present. Unary reduction operator is present.

It is more difficult to learn. It is easy to learn.

Basic Elements of VHDL :-

There are the following three basic elements of VHDL:

1. Entity

The Entity is used to specify the input and output ports of the circuit. An Entity usually has one or
more ports that can be inputs (in), outputs (out), input-outputs (inout), or buffer.

Entity Declaration

You can declare an entity using the following syntax:

o Simplified syntax

entity entity_name is entity orgate is

port ( port(
port_1_name : mode data_type; a : in std_logic;
port_2_name : mode data_type; b : in std_logic;
....... c : out std_logic
 Port_n_name : mode datatype );
); end orgate;
end entity_name;

2. Architecture Declaration

An architecture can be declared using the following syntax:

architecture architecture_name of entity_name is

begin
(concurrent statements )
end architecture_name;

Example:

architecture synthesis of andgate is

begin
c <= a AND b;
end synthesis;

3. Configuration
A configuration defines how the design hierarchy is linked together. It is also used to associate
architecture with an entity.

Rules for writing Port name:-

1. Port name consist of letters, digits, and underscores.
2. It always begins with a letter.
3. Port name is case insensitive.

Modes of Port
1. in - Input port
2. out - Output port
3. inout - Bidirectional port
4. buffer - Buffered output port
Types of Modeling styles in VHDL :-

There are mainly three types of modeling styles in VHDL:

1. Data Flow Modeling:-

In this modeling style, the flow of data through the entity is expressed using concurrent (parallel)
signal. The concurrent statements in VHDL are WHEN and [Link] them, assignments
using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct [Link], a special
kind of assignment, called BLOCK, can also be employed in this kind of code.
In concurrent code, the following can be used −

 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement

Implementation of Dataflow Modeling – Below is the implementation of the above logic in the
VHDL language (Dataflow Modeling).

VHDL Code for OR gate

-- Header file declaration

library IEEE;
use IEEE.std_logic_1164.all;

-- Entity declaration

entity orGate is
port(A : in std_logic; -- OR gate input
B : in std_logic; -- OR gate input
Y : out std_logic-- OR gate output
);
end orGate;

-- Architecture definition
architecture orLogic of orGate is
begin
Y <= A OR B;
end orLogic;
2. Behavioral Modeling :-
In this modeling style, the behavior of an entity as set of statements is executed sequentially in the
specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed
sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements placed outside
it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it, we
can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and they are
supposed to be used in sequential code only. VARIABLE can never be global, so its value cannot be
passed out directly.
Implementation of VHDL code for an OR gate using the behavioral modeling style:
VHDL code for OR Gate
-- Entity declaration
entity ORGate is
Port (
-- Input ports
input_signal1 : in std_logic;
input_signal2 : in std_logic;
-- Output port
output_signal : out std_logic
);
end ORGate;

-- Architecture (Behavioral)
architecture BehavioralArch of ORGate is
begin
-- Process for OR gate behavior
process(input_signal1, input_signal2)
begin
-- OR gate logic using IF-THEN-ELSE statement
if input_signal1 = '1' or input_signal2 = '1' then
output_signal <= '1';
 else
output_signal <= '0';
end if;
end process;
end BehavioralArch;

[Link] Modeling :-
In this modeling, an entity is described as a set of interconnected components. A component
instantiation statement is a concurrent statement. Therefore, the order of these statements is not
important. The structural style of modeling describes only an interconnection of components (viewed
as black boxes), without implying any behavior of the components themselves nor of the entity that
they collectively represent.
In Structural modeling, architecture body is composed of two parts − the declarative part (before the
keyword begin) and the statement part (after the keyword begin).
Implementation of VHDL code for an OR gate using Structural modeling style:
VHDL code for OR Gate
-- OR gate component declaration
entity ORGate is
Port (
-- Input ports
input_signal1 : in std_logic;
input_signal2 : in std_logic;

-- Output port
output_signal : out std_logic
);
end entity ORGate;

-- OR gate component implementation

architecture StructuralArch of ORGate is
begin
-- OR gate instantiation
ORGate_inst : entity [Link]
port map (
input_signal1 => input_signal1,
 input_signal2 => input_signal2,
output_signal => output_signal
);
end architecture StructuralArch;

VHDL objects :-

VHDL uses the following three types of objects:

1. Constants

Constant is an object which can only hold a single value that cannot be changed during the whole
code.

Example: constant number_of_bytes integer:=8;

2. Variables

A variable also holds a single value of a given type. The value of the variable may be changed during
the simulation by using variable assignment operator.

Variables are used in the processes and subprograms.

Variables are assigned by the assignment operator ":=".

Example:

variable index: integer :=0;

3. Signals

Signals can be declared in architecture and used anywhere within the architecture. Signals are
assigned by the assignment operator "<=".

Example:

Signal sig1: std_logic;

Sig1 <= '1'

Data Types in VHDL :-

Data Types are the abstract representation of stored data.

There are the following data types in VHDL -

1. Scalar Types

o Integer
Integer data types are the set of positive and negative whole numbers.
o Floating point
Floating point data types are the set of positive and negative numbers that contain a decimal
point.
o Enumeration
Enumeration data type is used to increase the readability of the code.
o Physical
Physical data type describes objects in terms of a base unit, multiples of base unit, and a
specified range.

2. Composite Types

o Arrays
Arrays are used to hold multiple values of the same types under a single identifier
o Record
Records are used to specify one or more elements, and each element has a different name
and different type.

VHDL Operators :-

VHDL Operators are used for constructing the expressions.

There are the following types of operators in VHDL:

1. Logical Operators

Logical Operators are used to control the program flow. When the logical operators combined with
signals or variables, then it is used to create combinational logic.

VHDL supports the following logical operators:

o and
o or
o nand
o nor
o xor
o xnor
 o not

2. Relational Operators

In VHDL, relational operators are used to compare two operands of the same data type, and the
received result is always of the Boolean type.

VHDL supports the following Relational Operators:

o = Equal to
o /= Not Equal to
o < Less than
o > Greater than
o <= Less than or equal to
o >= Greater than or equal to

3. Arithmetic Operators

Arithmetic Operators are used to perform arithmetic operations. These operators are numeric types,
such as integer and real.

VHDL uses the following Arithmetic Operators:

o + Addition
o - Subtraction
o * Multiplication
o / Division
o & Concatenation
o mod Modulus
o rem Remainder
o abs Absolute Value
o ** Exponentiation

4. Shift Operators

In VHDL, shift operator is used to perform the bit manipulation on the data by shifting and rotating
the bits of its first operand right or left.

VHDL supports the following Miscellaneous Operators:

 o Sll (shift logical left)
o Srl (shift logical right)
o Sla (shift arithmetic left)
o Sra (shift arithmetic right)
o Rol (rotate left)
o Ror (rotate right)

Synthesis and Simulation VHDL

Simulation :-

1. Simulation is the process of testing the behavior and functionality of the digital circuit model before
actual synthesis and physical implementation.

2. It involves simulating the VHDL code using specialized tools known as VHDL simulators.

3. During simulation, test vectors (input stimuli) are applied to the design, and the responses (output
waveforms) are observed.

4. The simulation helps verify the correctness of the design and ensures that it meets the desired
functionality and timing requirements.

5. There are two main types of simulation: functional simulation (to verify the correctness of the
design's functionality) and timing simulation (to verify the timing constraints).

Synthesis :-
1. Synthesis is the process of converting a high-level description of a digital circuit (usually written
in VHDL) into a gate-level representation.
2. The goal of synthesis is to map the behavioral or RTL description of the design into a netlist
consisting of standard cells (e.g., AND gates, flip-flops, etc.) from the target technology library.
3. The output of the synthesis process is typically a file in a format that represents the gate-level
netlist, such as a Verilog or EDIF (Electronic Design Interchange Format) file.
4. The synthesized netlist is used for physical implementation, where it will be placed and routed to
generate the final layout for manufacturing.
5. The synthesis tool optimizes the design based on various constraints, such as area, power, and
timing.
Finite State Machine (FSM):-
In digital electronics, FSM stands for "Finite State Machine." It is a mathematical model used to
design and describe sequential logic circuits, such as counters, shift registers, and controllers. FSMs
are widely used in various digital systems and electronic devices, ranging from simple circuits to
complex applications like microprocessors and communication protocols.
An FSM consists of a set of states, a set of inputs, a set of outputs, and a set of rules that define the
transition from one state to another based on the current state and input. The FSM operates in
discrete time, and its behavior is determined by the current state and the input at each clock cycle.
There are two main types of FSMs:-
[Link] Machine
[Link] Machine

Mealy State Machine :-

When the outputs depend on the current inputs as well as states, then the FSM can be named to be
a mealy state machine. The following diagram is the mealy state machine block diagram. The mealy
state machine block diagram consists of two parts namely combinational logic as well as memory.
The memory in the machine can be used to provide some of the previous outputs as combinational
logic inputs.

Figure :- Mealy State Machine Block Diagram

Based on the current inputs as well as states, this machine can produce outputs. Thus, the outputs
can be suitable only at positive otherwise negative of the CLK signal. The mealy state machine’s state
diagram is shown below

.
The state diagram of mealy state machine mainly includes three states namely A, B, and C. These
three states are tagged within the circles as well as every circle communicates with one state.
Conversions among these three states are signified by directed lines. In the above diagram, the
inputs and outputs are denoted with 0/0, 1/0, and 1/1. Based on the input value, there are two
conversions from every state.

Generally, the amount of required states in the mealy machine is below or equivalent to the number
of required states in Moore state machine. There is an equal Moore state machine for every Mealy
state machine. As a result, based on the necessity we can employ one of them.

Moore State Machine :-

When the outputs depend on current states then the FSM can be named as Moore state machine.
The Moore state machine’s block diagram is shown below. The Moore state machine block diagram
consists of two parts namely combinational logic as well as memory.

Figure:- Moore State Machine Block Diagram

In this case, the current inputs, as well as current states, will decide the next states. Thus, depending
on further states, this machine will generate the outputs. So, the outputs of this will be applicable
simply after the conversion of the state.

The Moore state machine state diagram is shown below. In the above state, the diagram includes
four states like a mealy state machine namely A, B, C, and D. the four states as well as individual
outputs are placed in the circles.
In the above figure, there are four states, namely A, B, C & D. These states and the respective outputs
are labeled inside the circles. Here, simply the input worth is marked on every conversion. In the
above figure includes two conversions from every state depending on the input value.

Generally, the amount of required states in this machine is greater than otherwise equivalent to the
required number of states in the mealy state machine

Generally, the number of required states in this machine is more than otherwise equivalent to the
required states in MSM (Mealy state machine). For every Moore state machine, there is a
corresponding Mealy state machine. Consequently, depending on the necessity we can utilize one of
them.
There is an equal mealy state machine for every Moore state machine. As a result, based on the
necessity we can employ one of them.

Finite State Machine Applications :-

The finite state machine applications mainly include the following.

FSMs are used in games; they are most recognized for being utilized in artificial intelligence, and
however, they are also frequent in executions of navigating parsing text, input handling of the
customer, as well as network protocols.
These are restricted in computational power; they have the good quality of being comparatively
simple to recognize. So, they are frequently used by software developers as well as system designers
for summarizing the performance of a difficult system.

The finite state machines are applicable in vending machines, video games, traffic
lights, controllers in CPU, text parsing, analysis of protocol, recognition of speech, language
processing, etc.
Advantages of Finite State Machine :-

The advantages of Finite State Machine include the following.

 Finite state machines are flexible
 Easy to move from a significant abstract to a code execution
 Low processor overhead
 Easy determination of reachability of a state
Disadvantages of Finite State Machine:-

The disadvantages of the finite state machine include the following

 The expected character of deterministic finite state machines can be not needed in some
areas like computer games
 The implementation of huge systems using FSM is hard for managing without any idea of
design.
 Not applicable for all domains
 The orders of state conversions are inflexible.
Fan-In And Fan-Out :-
In digital electronics and computer hardware design, "fan-in" and "fan-out" are terms used to
describe the input and output capabilities of a logic gate or a digital circuit.

1. Fan-In:

Fan-in refers to the number of input signals that a logic gate or a circuit can accept. In other words,
it represents the maximum number of input lines that can be connected to a particular gate. For
example, a 2-input AND gate has a fan-in of 2 because it can accept two input signals.

2. Fan-Out:
Fan-out, on the other hand, refers to the number of similar gates or loads that a logic gate's output
can drive or supply. It indicates the maximum number of gate inputs that can be connected to the
output of a specific gate without causing issues like signal degradation or reduced performance. For
example, if the output of an AND gate can drive three other gate inputs, the fan-out of that AND
gate is 3.