UNIT 1 INSTRUCTION SETS

Structure
1.0 Inlroduclion
1.1 Objectives
1.2 Instruction Set Characteristics
1.2.1 Oj~crandData Types
1.2.2 Number of Addresses in an Instniction
1.2.3 Operation Types
1.3 Addressing Schemes
1.3.1 Irnrncdiate Addressing
1.3.2 Dirccl Addrcssing
1.3.3 Indirect Addressing
1.3.4 Rcgistcr Addressing
1.3.5 Register Indirect Addressing
1.3.6 Displaccrnent Addrcssing
1.3.7 Stack Addressing Scheme
1.4 Instruction Format Design
1.4.1 Instruction Length
1.4.2 Allocation of Bits
1.4.3 Variable Length of Instructions
I .5 . Example of Instruction Set
1.6 Summary
1.7 Model Answers

1.0 INTRODUCTION
In the previous block, we have discussed about structure of the computer and the data
representation. One term which we have commonly used is the instruction. In this respect,
fcw questions which still need to be answered is : What is an instruction? What are its
components? How is the instruction executed by the CPU? This unit is an attempt to answer
~hc:first two questions. While, the third question is a complex one and is explained in the
later units. In this unit we havc discussed in details about the instructions, their types, the
operands. We will also discuss about the various addressing schemes which are popular
among various PC's and how the effective address is calculated for these schemes. In
addition we are also trying to highlight the basic design issues related to the instruction in the
unil. We havc prcsented here the instruction set of IBM Systemn70 as an example.
However, you car1 study the delails on the other instruction sets for example VAX machine
from the further readings. We have not included discussions on the instruction set of popular
lNTEL microprocessor. One of Lhis microprocessor instruction set is discussed in the
Block 3 of this course. Other related microprocessors instruction set can also be studied
from the further readings.

OBJECTIVES
At the end of this unit a student should be able to:
discuss about various elements of an instruction
distinguish various types of instructions
differentiate various types of operands
define a classification of computers on the basis of number of addresses in
instruction sets
discuss about various operations which are performed by the instru&ons
identify various addressing schemes
calculate effective address for various schemes
d~scussabout the instruction formats design characteristics
1.2 INSTRUCTION SET CHARACTERISTICS
Till now we have discussed about instruction in an abstract way. Now let us discuss in
details various characteristics of instructions. But let us first discuss what is the significance
of instruction set? One hing which should be kept in mind is that the instruction set is an
boundary which is looked upon in a same fa~hionby a computer designer and the
programmer. From thc computcr designer's point of vicw, the instruction set provides the
functional requirements of thc CPU. In fact, for implementing the CPU design, one of the
main task is to implcmcnt the instruction set for that CPU. However, from the-uscr point of
view machine instructions or Assembly instructions are nccdcd for low level programming.
In addition, a user should also be aware of registers, the data types supported by the machine
and the functioning of the ALU. We will be discussing about the registers in unit 2 and about
the ALU in unit 3 of this block.

Explanation on the machine instruction sct gives extensive details about the CPU of a
machine. In fact, the operations which a CPU can pcrform can be detcrmincd by the
machine instructions. Now, Ict us answer somc introductory qucstions about the instruction
set.

What is an instruction set?

An instruction set is a collection of all the inslructions a CPU can execute. Thcrefore, if we
define all the instructions of a computer, wc can say we have defined the instruction set.
Each instruction consist of sevcral elcmcnts. An instruction element is a unit of information
required by the CPU for execution.

What are the elements of an instruction?

An instruction have the following elements:
an operation code also termed as opcode which specifies the operation to be
performed.
A reference to the operands on which data processing is to be performed. For
example, an address of an operand.
A reference to the opcrands which may store the results of data processing
operation performed by the instruction.
A reference for the ncxt instruction, to be fetched and executed.
The next instruction which is to be executed is normally the ncxt instruction following the
current instruction in the memory. Thcrcfore, no explicit reference to the next instruction is
provided. If, we donot want this normal flow of execution then? You will find the answer
to this question in this unit.
An important aspect, of the references to operands and results is: where are those operands
located ? In the mcmory or in the CPU registers or in the VO device. If the opcrands are
located in the registers thcn an instruction can be executed faster than that of opcrands
located in the memory. The main reason here is that memory access time is higher in
comparison to the register access time.

How is an instruction represented?

Instructions are represented as sequence of bits. An instruction is divided into number of
fields. Each of these fields corresponds to a constituent element of instruction. A layout of
instruction is termed as instruction format. For example, following is the instruction format
for IAS computer. It uses four bits for opcode and only two operand references are provided
here. No explicit reference is provided for the next instruclion to be executed.

0 3 4 9 10 15

Reference to Reference
Opcode operand to operand

I 4 bits

Most significant bit

6 bits 6 bits
1
Least significant bit

Figure 1 : A sample lnstrudlnn format

 In most instruction sets, many instruction formats are used. An instruction first is read into
an instruction register(IR), then the CPU decodes the instruction and extracts the required
operands on the basis of references made through the instruction fields and processes it.
Since the binary representation of the instruction is difficult to comprehend and is seldom
used for representations. We will be using symbolic representation to these instruction in
this unit along with the comments wherever desired.

What are the types of Instructions?

I The insuuctions can be categorised under the following categories:
1 Data Processing Instructions: These instructions are used for arithmetic and logic
operations in a machine. Examples of Data Processing Instructions are: Arithmetic,
!I boolean, shift, character and string processing instructions, stack and register,
manipulation instructions, vector instructions etc.
Data StorageIRetrievalInstructions: Since the data processing operations rn
normally performed on the data stored in CPU registers. Thus, we need an
instruction to bring data to and from memory to registers. These are called Data
storage/remieval instructions. Examples of data storage and retrieval instructions
are: Load and store instructions.
Data Movement Instructions: These are basically input/ output instructions.
These are required to bring in programs and data from various devices to memory
or to communicate the results to the Input/Output devices. Some of these
instructions can be: Start Input/Output,Halt InputDutput. TEST InputDutput etc.
Control Instructions: These instructions are used for testing the status of
computation through Processor Status Word (PSW). This register will be discussed
in greater details in unit 2. Another of such instruction is the branch instruction used
for transfer of control. We will discuss in more details abo- instructions.
Miscellaneous Instructions: These instructions doesnot fit in any of i k a b y e
category. Some of these instruction are: interrupt or supervisory call, swapping,
return from interrupt, Halt instruction or some privileged instruction of operating
systems.

What are the factors which play important role for selectionldesigningof instruction set
for a machine?
Instruction set design is the most complex yet int,resting and very much analysed aspect of
computer design. The instruction set plays important role in design of the CPU as it &fines
many functions of it. Since instruction sets are the means by which a programmer can
control the CPU,therefore, users view must be considered while designing the instruction
set. Some of the important design issues relating to instruction design are:
How many and what operations to be provided?

3
.-
s
What are the operand data types to be provided?
What should be the Instruction format? This includes issues like: instruction length.
number of address, length of various elements of instructions etc.
What is the number of registers which can be refef~lcedby an instruction and how
are they used?

f What are the modes of specifying an operand address?

We will try to analyse these issues in some details in this and subsequent sections. Howevtx,
we have kept the level of discussion very general. A specif= example of instruction set is
given at the end of this unit

1.2.1 Operand Data Types

An operand data type specifies the type of data on which a particular operation can be
performed. For example, for an arithmetic operation numbers are to be used as data [Link]
general the operands which can be used in an instruction can be categorised in four general
categories. These are:
Addresses
Numbers
7
CPU OrganlsPUan Characters
Logical data
Addresses: Addresses are treated as a form of data which is used in calculation of actual
physical memory address of an operand. In most of the cases, the addresses provided in
instruction are operand references and not the actual physical memory addresses.
Numbers: All machines provide numeric data types. One special feature of numbers used
in computers is that they are limited in magnitude, and hence the underflow and overflow
may occur during arithmetic operations on these numbers. The maximum and minimum
magnitude is fixed for an integer number while a limit of precision of number and exponent
exist in the floating point numbers. The three numeric data types which are common in
computers are:

- Fixed point numbers or Integers (signed or unsigned)

- Floating point numbers

- Decimal numbers

All the machines provide instructions for performing arithmetic operations on fixed point
and floating point numbers. Many machines provide arithmetic instructions which perform
operations on packed decimal digits.
Characters: Another very common data type is the character or string of characters. The
most widely used character representation is ASCII (American National Standard Code of
Information Interchange). It has 7 bits for coding data pattern which implies 128 different
characters. Some of these characters are control characters which may be used in data
communication. The eighth bit of ASCII may be used as a parity bit. One special mention
about ASCII which facilitateconversion of a 7 bit ASCII and a 4 bit packed decimal number,
is that the last four digits of ASCII number are binary equivalent of digits 0-9.
That is
Decimal Binary ASCII

Figure 2 :Dedmal dlgits In ASCll

The other important code is Extended Binary Coded Decimal Interchange Code (EBCDIC).
This is a 8 bit code and is compatible with packed decimal in a similar way as that of ASCII.
The digits 0 through 9 in this can be represented as 1111 0000 through 1111 1001.
Logical Data: In general a data word or any other addressable unit such as byte, half word
etc. are treated as a single unit of data. But can we consider a n-bit data unit consisting of n
items of 1 bit each? If we treat each bit of a n-bit data as an item then it can be considered to
be logical data. Each of these n items can have a value 0 or 1.
What are the advantages of such a bit oriented view of data? The advantages of such a vim
will be:
We can store an array of boolean or binary data items most efficiently.
We will be in a position to manipulate the bits of any data item.
But where do we need to manipulate bits of a data item? The example of such a case is
shifting of significand bits in a floating point operation or for converting ASCII to packed
decimals where we need only the 4 right most bits of ASCII's byte.
Please note that for extracting decimal from ASCII, first the data is treated as logical data
and then can be used in arithmetic operations as numeric data. Thus, the operation
performed on a unit of data determines the type of the unit of data at that instance. This
 statement may not be true for a high level language, but holds good for machine level
language.
Check Your Progress 1
State true or false.
Q1. An instruction set is meant only for the programmer and is not needed at the time of
implementation of a machine?
True F a n
42. Explicit operand references are must for an instruction?
True (1F& n
Q3. You can use only one instruction format for an instruction set of a machine.

Q4. Data movement instructions are used for bringing in data from the memory to CPU
registers.
True 1 ~alrr
Q5. Numbers represented in computers are limited in magnitude.
True ) n
" r Q6. A data value in a machinc lmguage can be treated as of one type only.
True j( False n
1 1.2.2 Number of Addresses in an Instruction
The fewer number of adhesses in an Instruction lo reduced length of instructions,
however, it also limits lh?ranqe of functton *hatcdn ?sperformed by the instructions. In a
sense this implie. t k t a machine instr~~uonset hawng less number of addresses have longer
programs, which means longer execution m e . Howeger, more addresses may lead to more
complex decoding and prwesslng circuits.
Most of the instruc :ions donot require more than three operand addresses. In instructions
having fewer addrsses than three, normally some of the operand locations are implicitly
pefined. Many computers have a range of instructions of different length and number of
addresses. The followinp table gives an cxample ~f zero, one, two and three address
instruction along with their interpretaiions.
Number of Addresses Inst1 uction Interpretation
3 ADD A,B,C Operation A = B+C is executed
Two plausible interpretations
(i) AC = A + B
(ii) A = A + B. In this case the
original content of operand
location A is lost
ADD A AC = AC+A
A is added to accumulator
ADD Top of Stack contains the addition
of top two values of the stack.
AC is a accumulator register.
A,B,C are operand locations.
Figure 3 : Example dzero, one, two and three address Instruction

The register architecture, that is a general classification which is based on register set of the
computer, is sometimes classified according to the number of addresses in instructions.
These classificationsare:
Kvaluation-StackArchitecture: These machines are Zero address machines and their
9
CPU Ogsnlsation operands are taken from top of the stack implicitly. The ALU of such machine directly
references a stack which can be implemented in main mcmory or regis~rsor bob. These
machine contains instructions like PUSH and POP to load a value on stack and store a value
in the memory respectively. Please note that PUSH, POP are not zero address instructions but
contain one address.
The main advantages of such an architectureare:
very short instructions
since stacks are normally made within CPU in such an architecture machine, the
operands are close to the ALU, thus fast execution of instructions.
excellent support for subroutines.
While, the main disadvantages of this architecture are:
not very general in nature, in comparison to other architectures.
difficult to program for applications like text and string processing.
One example of such a machine is Burroughs B6700. However, these machines are not very
common today because of the general nature of machines desired. The stack machines uses
Polish notahons for evaluation of arithmetic expression. Polish notation was i n d u c e d by a
Polish logician Jan Lukasiewicz. The main theme of this notation is that an arithmetic
expression AxB can be expressed as:
either x AB (Prefix notation)
or ABx (Suffix or reverse polish notation)
In stacks we use suffix or reverse polish notation for evaluating expressioii. The rule here is
to push all the variable values on the top of stack and do the operation with the top elements
of stack as an operand is encountered. The priority of operand is kept in mind for generation
of reverse polish notation. For example, an expression AxB+CxD/E will be represented in
reverse polish notation as:

Thus, the execution program for evaluation of F = AxB+CxD/E will be:

PUSH A /Transfer the value of Aon to the top of stack /

PUSH B /Transfer the value of B on to the top of stack /
MULT /Multiply. It will remove value of A and B from the stack and multiply A x B /
PUSH C /Transfer C on the top of stack /
PUSH D /Transfer D on the top of stack /
MULT /Remove values of C & D from the stack and multiply C x D /
PUSH E Kransfer E on the top of stack /
DIV 1Cx D/E /
ADD /Add the top two values on the stack /
POP F /Transfer the results back to memory location F /

Flpm 4 :Sample program lor evaluating AxB+CxDIE using zero address instructions

Please note that PUSH and POP are not zero-address instructions.
The execution of the above program using stack is represented diagrammatically in figure 5.
Accumulator Machines: These machines contain a special register called accumulator
which holds the results of arithmetic, logical or shift operations. The accumulator is an
implicit address. The instructions in such machines are normally one-address instructions.
The basic advantage of the one address machines is that the instructions are shorter than 2
and 3 addressed machines. However, de performance of these machines are somewhat slow
because these machine require frequent memory accesses. These machines are made by
various vendors.
For example, a program for evaluating the expression F=AxB+CxD/E written in this
Accumulator based machine is given in figure 6.
 PUS14 C

DIV ADD POP F

Stack empty

Assumption : TOS is top of stack which is pointing to an empry location

Figure 5 : Evaluation using a stack

/Transfer A to Accumulalor/
/Multiply Accumulator with B, keep the result of /
/multiplication in B/
/Store the intermediate result temporarily in a location T/
/Transfer C to Accumulator /
/Accumulator = Accumulator X Dl
/Accumulator = ~c'cumulator/E/
/Accumulator = Ac%umulator+ T/
/Store the Accumulator value to location F/
Figure 6 : Sample program for evaluating AxBtCxDIE using one address instructions

General Purpose Register Set Machines: Many computers have bcen designed having set
of registers termed as general purpose registers. Thesc general-purpose regisler machines
normally have multiple address instructions. In these machines any of the register of the
register set can be used as accumulator or an address register or an index register or a stack
pointer, or even (in some cases)as a program counter. In such machines, each instruclion
specifies itself,about the use of register. Some examples of such computers are IBM syslem
370 & Digital VAX families.
The instructions in such machines can specify as many Register operands as desired.
Therefore, several oprations can be performed solely on regislers. This may increase the
program execution speed as register references are faster than memory references. For the
purpose of flexibility and ability to use multiple registers, these computers may use two and
three address instructions. Some of these computers have instructions for Register to mcrnory
transfer, and memory to memory transfer. Since number of registers are few, thcrcfoe, the%
instructions are normally shorter.
The program for F = AxB + CxDE for 2 address and 3 address machines will look llke
MOVE T,A /MoveTA/ MULT F, A, B / F=AxB /
T, B / Multiply T=WB / MULT T, C, D / T=CxD /
MOVE F,C /MoveF C / DIV T,T,E /T=T/E/
F, D / Multiply F=FxD / ADD F,F,T / F=F+T/
F, E / Divide F=F/E / 11
ADD F, T 1 Add F=F+T/
Figure7 :Sample program fw evaluating F=AxB+CxD/E using two and three address instructions

Special-PurposeRegister Set Machines

The main problem with the above type of machine is: too much of generality. In several
machines, sets of registers may be used for only special purposes. For example, one set of
register may be used as index registers, another set for holding arithmetic operands etc.
computers like CDC6000/7000family fall under this category.
Many a machines fall in between of the above two categories. They have some special
purpose and some general purpose register sets. These machines are now a days quite
popular.

1.23 Operation Types

Different computers use a wide variety of opcodes and number of addresses. Some of the
operations which are specifled on one machine may not exist on a second machine.
However, certain category of operations exist on all the machines. We will try to provide
details on some of the typical categories of operation. Broadly the operations specified in
instructions irrespective of number of addresses in an instruction, can be categorised as:

- Data Transfer operations

- Arithmetic operations
- Logical [Link] operations
- Conversion operations
- InuutKlutput operations

- System control operations

- Transfer of control operations

Data Transfer Operations: This is the most fundamental type of operation. A data transfer
instruction need ro furnish the following information:
The location of source and destination operands (This could be memory or regismr
or stack-top). This will be more clear after you go through the next subsection.
The length of data transfer
The mode of addressing for each operand. These addressing modes are discussed in
greater details in the next section.
Some of the common data transfer operations are:
Operation Description
MOVE or TRANSFER Transfers a word or a block of data from source to
destination.
STORE Transfers a word from the processor to a specified location
in the main memory.
LOAD or FETCH Brings a word from a location of main memory to the
processor.
EXCHANGE Exchanges the contents of the source with the destination.
CLEAR or RESET Transfers a word containing all 0's to the destination.
SET 'Itansfen a word containing aU 1's to the destination.
PUSH Transfers a word from a source to top of stack.
POP Transfer a word from the top of stack to a destination.
Figure 8 : Common data transfer operations

For all these instructions the choice of source or destination can be a location in the main
memory or a register or the top of stack. This location can be indicated either in opcode or in
the specification of an operand.
 Arithmetic Operations: Almost all the machines provlde the four basic arithmetic
I operations on signed fixed point integers. Some machines provide operations on floating
point and packed decimal numbers. Some other arithmetic operations such as absolute of a
number, negation of a number, incrementing or decrementing a number are also included as
instructions in several machines. The execution of an arithmetic instruction requires bringing
in the operands in the operational registers such that the data can be processed by the ALU.
I The arithmetic operations which can be provided in a machine in general be:
! ADD, SUBTRACT, MULTIPLY, DIVIDE
i
ABSOLUTE, NEGATE, INCREMENT, DECREMENT
i
Logical and Shift Operations: The logical operations are based on boolean operations
performed on binary data. Some of the logical operations are: AND, OR, NOT,
Exclusive-OR.
In addition to these bitwise logical operations, machines provide a variety of shifting
operations. A shift operation is performed either in the left or to the right. In a shift
operation, all the bits move towards the left or right as desired. (Please refer to figure 9).

Bit in Bit out

(for right shift) (for right shift)
(Right shift)
I t

I
(left shift)
Bit out Bit in
(for left shift) (for l d t shift)

I Flgure 9 :Shift operrtlons schemaUc for 8 bit register

The following are some observations about shift operations.

-
In logical lejilright shift the "bit in" is a 0 bit.
Arithmetic shift is same as logical shift except for the sign bit which is not shifted.
A circular shift uses the "bit out" bit as the "bit in" bit.
The main usage of these shifts are:
The logical shift is used in extracting fields from a word. How?
The arithmetic shift if performed on numbers represented in signed 2's complement
notation cause multiplication by 2 or division by 2 depending on left or right
arithmetic shift, provided there is no overflow or underflow.
The circular shift preserves all the bits.
Conversion Operations: The conversion operations are needed to convert the fonnat of the
data. For example changing format from decimal to binary or ASCII to EBCDIC or vice
versa. In general the two conversion operation are:
TRANSLATE This instruction translates a given piece of data depending on a
table of correspondence
CONVERT It convert. the contents of a word from one format to other.
Let us give an example of each of these. A common example for TRANSLATE instruction is
conversion of ASCII to EBCDIC. This can be achieved by creating a table which is 256 byte
long. We can call it as an array of EBCDIC equivalent values. Each index of this array
represent the ASCII value, while the content of that location is the equivalent EBCDIC. For
example, if 00110011 in ASCII is equivalent to 11001100 then
ARRAY location 00110011 contains 11OO1100
that is TRANS [00110011] = 11001100
However, the convert instruction converts the format based on certain rule for example,
decimal to binary.
13
CPU Organisation InputiOutput Operations: There 1s a lo1 of variety as far as input/output operations are
concerned as they depend on the type of input/output such as programmed 110, DMA, etc.
We have given some 110 operations in the Unit 4 of Block 1. However, some of the common
input/output instructions are:
READ (or INPUT) This command is used for transferring data from inpur/output
module or part to a destination which may be the main memory
or processor register.
WRITE (or OUTPUT) This command transfers data from a specified source to input1
output module.
TEST UO It transfers the inpur/output systems status information to a
specified destination.
System Control Operations: The system control operations generally come under the
category of privileged instructions, that is, these instructions are executed only when the
processor is in certain privileged state or the processor is executing a program which is
stored in a special privileged area of memory. In general, these instructions are used by the
operating system. A typical syslem control instruction is OSCALL. This instruction causes
the interruption of execution of current program and passes the control to the operating
system.
I'ransfer of control Operations: In general, in a program execution the next insrniction in
sequence is executed next. However, in certain cases such as looping, decision making and
subroutine call, the next instruction to be executed may not be the next instruction in
sequence. The instructions that disturb the normal flow of instruction execution are called
transfer of control instructions. The most common transfer of control instructions which are
found in instruction sets are:

- Branch
- Skip
- Subroutine Call
Branch Insrrucrion: A branch instruction causes a jump,to the new instruction to be
executed. A branch instruction is also known as jump instruction. This instruction has one
operand, that is, the address of the instruction to which branch is desired. The branch
instruction, in general, is used as a conditional branch instruction that is the branch is made
only if a specified condition is satisfied otherwise the next instruction in the normal sequence
is executed.
But how is the condition tested? Most of the machines provide a 1 bit or a multiple-bit
conditional code, which in certain cases can be treated as a user visible register (we will
discuss more about user visible registers in unit 2 of this block). For example, a typical
machine performing on an arithmetic operation can set a 2 bit condition code to either zero,
positive, negative or overflow condition. On such a machine, we can have the conditional
jump instructions as:
Conditional Meaning Instruction Meaning
Code (C.C)
00 Resultant is positive BRP X Branch to memory location
X if the result is positive
01 Resultant is negative BRN X Branch to memory location
X if the resultant is negative
10 Resultant is Zero BRZ X Branch to X if resultant is Zero.
11 Overflow has occurred BRO X Branch to X if overflow
has occurred.
All these branches may be implemented by assigning Program counter (PC) the address of
the location to which branch is desired.
Figure 10 :Example of conditional branch lnstrudlons

As the changes in condition code may Lake place on execution of each instruction,
Therefore, the branch instruction will depend on the most recent instruction which have
modified the condition codc. All thc abovc four branches takes place when a condition, is
fulrillcd, othenvisc h e next instruction in scqucnce is cxecuted. Another type of condltional
 Instruction Sets
branch instruction which has the condition in itself can be devised for a three address
instruction. For example:
BUN R1,R2,C (Branch to a memory location address 'C' if contents of R1 is not
equal to contents of R2.)
Here the condition is tested and branch is determined in a single instruction. Please note that
branch can take place to a higher address or to a lower address. How branching can be used
for looping is discussed in block 3 of this course.
Skip Insfrucfion:This instruction skips the next instruction to be executed in sequence. In
other words this instruction increments the address of "next instruction to be executed" (in
many computers it is the program counter) by one instruction length. Skip instruction can
also be used with conditions, for example, IS2 instruction skips the next instruction only if
the condition codc indicates that the resultant of the most recent operation is zero. This
instruction along with branch instruction is used for implementing looping structures.
Subroufine Call: A subroutine is a self contained user program which contains the code
often used repeatedly in a large program. This program is incorporated in a bigger program.
For more details on subroutine, you can refer to Course 2, Block-1, Unit- 1.

I
A subroutine is called explicitly by a program statement. This is explained in the following
figure:

100 Flow of Control

100
101

execution

102
103

execution

300 RETURN 104

and so on

Assumption for the present flow of control: N o transfer of

control instruction in the subroutine.

Figure 11 :Subroutine Call

Two most important instructions related to subroutine call are CALL and RETURN
statements. CALL causes jump to the first instruction of subroutine, however, this jump
must remember from where it has started as RETURN brings the control back to the
instruction following the CALL instruction. The logic of subroutine call is similar to that of
Interrupt processing. The subroutine call is implemented in many cases by storing the
contents of Program Counter (PC) which in fact is the pointer to the return address.
But where do we store the return address? In general, the return address can be stored in a
register or memory location specifically used for this purpose. In such a system the
following stcps will be fol!owcd on encountering a subroutine call.
 Store thc contcnt of PC in a predetermined memory location or register. Let us, call
this rcgister or mcmory location as R
Transfer the starting address of the subroutine which has been called in the PC
Execute the subroutine
On encountering RETURN statement of this subroutine load the contents of R into
the PC.
A second approach cm be to store the return address at the start of the subroutine. For
example, a call instruction CALL X will initiate the following steps:
Store the contents of PC into memory location X.
Place address X+l in the PC, as subroutine statements starts from this memory
location only, as the Xth location is reserved for storing the return address
Execute the subroutine
On encountering RETURN statement, load the contents stored in memory location
XtothePC.
However, the+ two approaches are not valid when more than one person want to execute the
same subroutine simultaneously, and also when a subroutine calls itself. The reason is that in
both the cases the location whcre the return address is stored will be rewritten by the new
calling address, in turn, canceling the previously stored address.
Thus, a very general approach utilising stacks is used for subroutinecall. The return address
on a subroutine call is pushed on the top of the stack. On encountering a RETURN
statement the POP operation is used to retrieve the most recent return address. This methou
also works for recursive subroutine calls.
Another important aspect of subroutine call is the parameter passing. With a subroutine call,
in general. parameters are passed. There are three approaches for parameter passing
Parameter passing through registers
Parameter passing through memory location just after the call instruction location.
The return address in such a scheme should be the memory location after thesr:
memory based parameters.
Use of stacks for parameter passing in addition to return address.
The drawback of the first approach is that proper utilisation of registers is to be ensured by
the calling program. The second method fails in cases where variable number of parameters
are to be passed. The third approach is quite general in nature. Stacks are used for not only
storing the return address but are also used for storing the parameters which are to be passed
to the subroutine which is called. The stacks are discussed in greater details in Course-4.

Check Your F'rogress 2

1. Match the following pairs:
(a) Zero address instruction (i) General purpose register set
(b) One address instruction (ii) Stacks
(c) Two address instruction (iii) Accumulator machine
2. What are the advantages and disadvantages of evaluation-stackarchitecture?

3. Match the following:

(i) MOVE (a) Data transfer operation
(ii) WRITE (b) VO operation
(iii) LOAD (c) Conversion operation
(iv) READ (d) System control operation
(v) TRANSLATE
4. How a subroutinecall is different from branching?
 Instruction Sets
......................................................................................................................
5. What are the three mcthods for calling a subroutine?

1.3 ADDRESSING SCHEMES

As discussed earlier, the main function of a computer is to execute instructions. An
instruction contains an operation codc (opcode) and operand(s) in the coded form. The
opcode field specify the operation to be carried out and the operand(s) field specify the
location of the operand(s) in the memory. An operand may be specified as the part of the
instruction, or the reference of the memory location where the value is stored may be given.
The term 'addressing schemes' refers to the mechanism employed for specifying operands.
The arrangement of opcodes and operands and their numbers within the instructions
dctermines the form or the format of an instruction. We will discuss more about addressing
formats in the next section.
The choice of addressing schemes and instruction formats are governed by the efficiency,
(time as well as space) economy and programming flexibility considerations. All the
available machines in the market today, therefore, employ more than one addressing
schemes. In the subsequent sections, we describe the most common addressing schemes and
show how the contents of operand (address) are mapped to the physical memory location
where the operand being addressed is actually stored.
I q the description that follows the symbols A, A1,A2,....,etc. denote the content of an
operand field. Thus A, may refcr to a data or a memory address. In case the operand field is a
register address, then the symbols R, R1,R2,... etc., are used. If C denotes the contents
(,cilherof an operand field or a register or of a memory location), then (C) denotes the
content of the memory location whose address is C.
I he byrnbol EA (Effective Address) refers to a physical address in a non-virtual memory
cnvlronment and refers to a register in a virtuaI memory address environment. This register
address 1s then mapped to physical memory address. What is a virtual address? Von
Ncumann had suggested that the execution of a program is possible only if the program and
data is residing in memory. In such situation the program length along with data and other
\pace needed for execution cannot exceed the total memory. However, it was found that at
thc time of execution, the complete portion of data and instruction is not needed as most of
thc time only few areas of program are being referenced. Keeping this in mind a new idea
was put forward where only a required portion is kept on the memory while the rest of the
program and data reside in secondary storage. The data or program portion which is stored
on secondary storage is brought to memory whenever needed and the portion of memory
which IS not needed is returned to the secondary storage. Thus, a program size bigger than
'he actual physical memory can be executed on that machine. This is called virtual memory.
Thc virtual memory has been discussed in greater details in Block-2 of Course-2.
Th: typicality of virtual addresses are that:
they .are longer than the physical addresses as total addressed memory in virtlial
memory is more than the actual physical memory
if a virtual addressed operand is not in the memory then the operating systgpl brings
that operand to the memory.
The symL*olsD, Dl, Dz, ...,etc. refer to actual operands to be used by instructions for their
execution. Now let us discuss about the various addressing schemes.

1.3.1 Immediate Addressing

Under this addressing scheme, the actual operand D is A, the content of the operand field: i.e.

'This addressing mode is used to initialise the value of a variable. The advantage of this
mode is that no additional memory accesses are required for executing the instruction.
However, as the size of instruction and operand field are limited, the type of data specified
under this addressing scheme also get restricted.
1 CPU Organisation 1.3.2 Direct Addressing
Under thls addressing scheme, the content A of the operand field specify EA, the effective
address of the operand: i.e.
EA = A and
D = @A)
The second statement implies that the data is stored in the memory location specified by
effective address. In this addressing scheme only one memory reference is required. This
simple addressing scheme provides a limited address space. If the address field has n bits
then the address space available is 2" memory locatigns.

1.3.3 Indirect Addressing

Under this addressing scheme the effective address EA and the contents of the operand field
are related by
EA = (A) and
D = @A)
The disadvantage of this addressing scheme is that it requires two memory references to
fetch the operand. The first memory reference is used to fetch the effectiveaddress from the
memory and second for fetching the operand using EA. In this scheme the addressed space is
determined by word length. In many machines multiple level of indirection may be used
where EA = (... (A) ...) gives the relationship between A and EA. In such a case a bit
(generally the most significant bit) in the word address specifies the indirection. If this bit is
'1'. then the contents of the word represent the address of the address of the operand and if it
is '0'then the contents of the field represent the address of the operand. If the size of the
address field is n then the address space available under multiple indirection addressing
scheme is 2"-'.

1.3.4 Register Addressing

In this addressing scheme, the instruction specifies the address of the register containing the
operand:
EA = R
D = (EA)
Please note that EA here is a register address and not a memory address. The advantage here
is that only a few bits are needed to address the operand. For example, for a machine having
16 general purpose registers only 4 bits are needed to address a register.
In some cases the address of the register containing the operand may not be explicitly
specified but is understood implicitly. This is generally the case where one of the operands is
in a specialregistercalled the Accumulator.
Register access is faster than memory access. So register addressing provides faster
instruction execution. However, this statement is valid only if the registers are employed
efficiently. For example, if an operand is moved into a register and processed only once and
then returned to memory, then no saving occurs, however if an operahd is used repeatedly
after bringing into register then we have saved few memory references. Thus the task of
using register efficiently deals with the task of finding what operand values should be kept in
registers such that memory references are minimised. Normally, this task is done by a
compiler of a high level language while translatir~gthe program to machine language.

1.3.5 ~ e ~ i s t Indirect
er Addressing
Under this addressing scheme the operand field specifies the registers which contains the
address of the operand.
EA = (R) and
D = (EA)
The address capability of register indirect addressing scheme is determined by the size of the,
register.
I
I 1.3.6 Displacement Addressing
This is a very powerful addressing scheme. It combines both the direct addressing as well as
the register indirect addressing schemes. Here the content A of the operand field is related to
i
EA by
I

The register address R may be specified explicitly or implicitly in the instruction. Depending
I
upon the use and the implementation this address scheme may be known as:
Indexed Addressing Scheme: This addressing scheme is generally used to address me
consecutive locations of memory (which may store the elements of an m y ) . The
t interpretation of the expression €A = A+@) is as follows:
The contents of the operand field A is taken to be the address of the initial or the reference
location (or the first element of array). The contents of register R gives the @lacement
with respect to the reference location. For example, to address of an element Bi of an array
B1, B2,....B,, with each element of the array stored in two consecutive locations, and the
starting address of the array being 101, the operand field A shall contain the number 101 and
i the register R will contain the value of the expression (i-1) x 2. Thus, for the first element of
the array the register will contain 0. For addressing 5th element of the array, the A=101
where as register will contain (5-1) x 2 = 8. Therefore, the address of 5th element of array
B5=101+8=[Link] B5, however, is stored in location 109 and [Link] address any other
element of the array, changing the content of the register (let us call it index register) will
suffice. As the index register are used for iterative applications, therefore, an index register
is incremented or decremented after each reference to it. In several systems this operation is
performed automatically during the course of an instruction cycle. This feature is known as
autoindexing. Autoindexing can be autoincrementing or autodecrementing. The choice of
register to be used as an index register differs from machine to machine. Some machine
employ general purpose registers for this purpose while other machines may specify special
purpose registers referred to as index registers.
Another related addressing scheme which couples the indirect addressing with indexing are
also utilised by several systems. Here, there are two possibilities:
Indexing is performed after indirection (postindexing):
In this scheme the memory address specified by opcode address the location that contains a
direct address which is to be indexed. That is:
DA = (A)
€A = DA+ (R)
D = @A)
( DA is Direct address )

Indexing performed before indirection (Preindexing):

This means that the a d h s s generated after doing indexing is the address of the location of
operand. That is
IA = A + @ )
EA = (IA)
D = @A)
( IA is indexed address )

In normal circumstances both pre-indexing and post-indexing are not used in an instruction
set simultaneously.
Base Addressing Scheme: This addressing scheme is generally employed to relocate the
programs in the memory specially in a multiprogramming environment Relocation is
discussed in details in course 2, block 2. Here the register R, referred to as Base Register
contains the initial address in the memory (referred to as the base address) of the program
segment being relocated. The operand field A contains the displacement of an instruction 01
data with respect to the base address. In this case:
€A = A + (B) ; D = (EA)
(B) refers to the contents of a base register B.
The contents of the base register may be changed in the privileged mode only, i.e. in the user
mode the contents of the base register cannot be changed.
CPU Ogmlsatla The base addressing scheme while on one hand provides the enhanced addressable space on
the other hand it provides protection of users from one another.
In a base addressing scheme the address of an index addressed element is given by:
EA = A + (B) + (I), where B and I are base register and index register respectively.
Like index register a base register may be a general purpose register or a special register
reserved for base addressing.
Relative Addressing Scheme: In this addressing scheme, the register R is the program
counter (PC) containing the address of the current insuuction being executed. The operand
field A contain the displacement (positive or negative) of an instruction or data with respect
to the current instruction. This addressing scheme have advantages if the memory references
are nearer to dle current insuuction being executed.

1.3.7 Stack Addressing Scheme

This is not a very common addressing scheme. In this addressing scheme, the address of an
operand is not specified explicitly. It is implied. The operand is found on the top of a stack,
In some machines the top two elements of stack and top of stack pointer is kept in the CPU
registers, while rest of the elements may reside in the memory. Figure 12 sums up the
operating principles of all these addressing schemes. ,

Main memory Main memory Main memory

Inswclion Inslruaion

1 Instruction I

R Operand

(a) Immediate addressing

I Operand

@) Direct addressing
Address of operand

(c) Indirect addressing .

Main memory
Main memory

Instruction
Instruction

Opt-d operand
- &. .
d
.
#
-_
Operand c Register Set
Register Set

(d) Register addressing (e) Register Indirect

Instruction

Top cf stack
Register Set

(g) Stack Addressing

(f) Displacement

" T I E 12 :Basic rddredng modes

 \ -
instruction Scls
In scncral not all of thc abovc motics arc uscd for all applicat~[Link], somc of the
common arcas whcre compilers ol high lcvcl languagcs usc thcm arc:

Autoindex modc + for pushing or popping lhc paramctcrs of a procedures.

Direcl mode + Normally used for global variables (used a litlle bit less han local
variablcs)

Rcgistcr + For holding local variables of procedures (frequently used)

Indcx + Accessing iterative local variables such as arrays

I Immcd~atc

Register indircct
-;,

-;,
For moving constants, initialisation of variables

For holding pointers to structure in programming languages such

as records in pascal

I
I
I
I
I
Check Your Progress 3
1. F~ndout the memory rcferences required to get h e data for h e following addressing
modcs:
D~rcctaddrcss~ng

lndircct addressing
Rcgis~crindircct addressing
I~nmcdiateaddressing

7 . st;1tc UUC or false

(a) Im~ncdiatcaddressing is best suited for sloring floating point numbers.

I
True False T
I
(b) Indircct addressing require fewer memory accesses than that of index addressing

True 1 1 False I 1
(c) Index addressing is used for addressing arrays.

T r u e r 1 False I[
3. What are h e differences between preindexing and postindexing?

4. What are the differences between base and relative addressing schemes?

1.4 INSTRUCTION FORMAT DESIGN

As discussed earlier an instruction consist of an opcode and one or more operands which are
addressed implicitly or explicitly. An instruction format is used to define the layout of the
bits allocated to hese elements of instructions. In addition, the instruction format explicitly
or implicitly indicates the addressing modes used for each operand in that instruction.

As far as the designing of instruction format goes, it is a complex art. The computers have a
variety of instructions designed for them in last so many years. We will discuss in this
section about the design issues for instruction sets of the machines. We will discuss only
point wise details of thcse issues.
CPU Organisation 1.4.1 Instruction Length
Significance: It is the most basic issue of the format design. It determines the richncss and
flexibility of a machine.
Basic Tradeoff: Smaller instruction (less space) Vs desire for more powerful instruction
repertoire.
Normally programmer desire:
more Opcode and operands: as it results in smaller programs.
more Addressing modes: for greater flexibility in implementing functions like table
manipulations, multiple branching.
However, a 32 bit instruction although will occupy aouble the space and can be fetched at
double the rate of a 16 bit instruction, but can not be doubly useful.
Factors which must be considered for deciding about instruction length
Memory Size If larger memory range is to be addressed, then more bits may
be required in address field.
Memory organisation : If the addressed memory is virtual memory then memory
range which is to be addressed by the instruction is larger than
physical memory size.
Memory Transfer length : Instruction length should normally be equal to data bus 4
(in bus system is equal length or multiple of it.
to the data bus length)
Memory transfer : The data transfer rate from the memory ideally should be
equivalent to the Processor speed. It can become a bottleneck
if processor executes instructions faster than the rate of fetching
the instructions. One solution for such problem is to use cachc
memory or another solution can be to keep instruction shor~.
Normally an instruction length is kept as a multiple of length of a character (that is 8 bits),
and equal to the length of fixed point number. The term word is often used in this context.
Usually the word size is equal to the length of fixed point number or equal to
memory-transfer size. In addition. a word should store integral number of characters. Thus,
word size of 16 bit, 32 bit, 64 bit are be coming very common and hence the similar length of
instructions are normally being used.

1.4.2 Allocation of bits

The tradeoff here is between the number of opcode versus the addressing capabilities. An
interesting development in this regard is the development of variable length opcode. An
opcode has a minimum length and then depending on the instructions which require fewer
operands or less powerful addressing mode, the opcode can be changed.
Let us discuss the factors which are considered for selection of addressing bits:
Number of addressing modes: The more are the explicit addressing modes the more
bits are needed f a mode selection. However, some machines have implicit modes of
addressing.
Number of operands: Fewer number of operand references in an instruction although
require less bits yet result in longer programs. Now a days many of the machines are
having two operand references in an instruction. Each of these operands may need a
mode indicator field of its own or both the operands may have the same addressing
mode indicator f ~ l dthat
, is the same addressing mode.
Register addressing versus memory addresses: If more and more registers can be
used for operand references then instructions are bound to be smaller as number of
registers is far less than the memory size, therefore, they require only few bits in
comparison to the bits needed for the memory addresses. In general, the number of user
visible registers provided is 8 to 16. This number is found to be an optimum number of
registers by several studies.
Register Sets: Even in the case of register address as the trend is moving from a large
number of general purpose registers to two or more sets of registers, for specialized data
 Instruction Sets
storage. For example, one special register set can store only the data for calculation,
while the other can store only the addresses. This results in further decrease in the sue
of instruction bits for register addressing. [Link], in case a machine has 16 general
purpose registers then a register address of it require at least 4 bits, however, if these 16
registers are used as two specialized sets of registers than one of the 8 registers need to
be addressed at a time, thus requiring only 3 bits for register addressing mode.
Range of address: The range of main memory addresses which need to be addressed
directly or indirectly are involved for having a specific number of bits in instructions.
For example, if direct addressing is used then the addressed memory determines directly
the number of instruction bits required. However, in displacement index addressing
schemes it is the offset which can control the number of bits desired in the instruction.
Granularity of address: As far as memory references are concerned, granularity
implies whether an address is referencing a byte or a word at a time. This is more
relevant for machines which have 16 bit, 32 bit and higher bits words. Byte addressing
although may be better for character manipulation, however, requires more bits in an
address. For example, memory of 4K words (1 word = 16 bit) is to be addressed directly
then it requires:
WORD Addressing = 4 K words
= 212 Words
* 12 bits are required for word addressing.
Byte Addressing = 212Words
= 2'3~ytes
13 bits are required for byte addressing.

1.4.3 Variable-length of Instructions

With the better understanding of computer instruction sets, the designers came up with the
idea of having a variety of instruction formats of different length. What could be the
advantages of such a set? The advantages of such a scheme are:
Large number of operations can be provided which have different lengths of
insmctions.
Flexibility in addressing scheme can be provided efficiently and compactly.
However, the basic disadvantage of such a scheme is to have a complex CPU. However with
the advances in technology and increase in basic understanding about the CPU designing
may reduce the overheads required for added complexity of such a scheme. However, one
condition which still holds for length of instructions is that all the possible instruction lengths
should be multiple of word size.
An important aspect about these variable length instruction is: " The CPU is not aware about
the length of next instruction which is to be fetched". This problem can be handled if each
instruction fetch is made equal to the sue of the longest instruction. Thus, sometimes in a
single fetch multiple instructions can be fetched.
After discussing so much above various concepts, now let us look at the instruction set of
IBM SB70 machine in the next section.

i h e c k Your Progress 4

!Statetrue or false.
1. A long instruction can be executed faster than short instructions.

TNe 1 1 False
2. Virtual addresses require more bits for the address part of instruction in comparison to
non-virtual addresses.
TN~ ( False
3. The speed gap between processor and memory suggests that instruction size should be
as big as possible.
True 1 False
: CPU organisation 4. In general, the instruction length is kept equal to the size of floating point storage
format.
True n False n
5. Large number of operand addresses in instruction leads to smaller programs.
1(
True False
6 Register addresses for specialised register set machines is smaller than that of the
machines having general purpose register set.
True False
7. A machine using direct addressing mode having a memory addressing capability of 8 K
bytes, require 13 bits for byte addressing.
True False
8. In a variable length instruction format, an instruction fetch must fetch the words equal
to the size of smallest instruction.
True False

1.5 EXAMPLE OF INSTRUCTION SET

In this section we will look at the instruction set of a very important vendor the IBM. We
have not included instruction set details of any of the INTEL microprocessor in this unit.
One such microprocessor architecture is given in the block 3 of this course. The other
instruction sets can be studied by you from the further readings.
IBM 370 Architecture: The IBM S1370 is a popular architecture. Let us discuss about the
features provided in this architecture.
Data types: It provides the following data types:
Data type Allowed Length Characteristics
Binary Integers 16 and 32 bits Unsigned i.e. non-negative numbers or signed
binary integer in signed 2's complement
notation.
Floating point 32,64 and 128 bits A 7 bit exponent with all the formats.
Decimal numbers 1 to 16 bytes Rightmost 4 bits are used for sign. Thus,
1 to 3 1 digit decimal number can be
represented. Arithmetic on these packed
decimal integers is provided.
Binary logical 8.32 and 64 bits and Logic operations are defined for the data
variable length logic units of the given length.
data till 256 byte
Character 8 bits EBCDIC are used.
Operation Types: Although the IBM/370 principal operation manual classifies the machine
instructions in six broad categories, yet for the sake of simplicity they have been separated
according to function by Stallings. This classification categories the instruction type in 12
categories:
Instruction Type Description .. .

Fixed point arithmetic One register is used for storing one of the operand
Instructions and theresult, while the second operand can be in
another register or in memory. It provides operations
in either as unsigned 16 or 32 bit integer operands or
16 or 32 bit 2's complemented integer numbers.
Logical Instruction Provided bitwise AND, OR and XOR operations.
General Register Provides 8 shift instructions pairing the following
Shifting Instructions options:
 (1) Lcft or right shil't
(2) Usc of single or double rcgistcr
(3) Signcd or logical shift
For example, two of the eight shirt instructions will be
a left, single register, logical shift instruction and a left,
double register, signed shift instruction. A second
operand is used in the instruction to specify the
amount of shift. The shift instruction effects either a
single register or this can effect an even-odd register
pair. The arithmetic shift instruction leaves the sign
bit intact.
General Register - load Provided transfer operations as:
and store Instructions - Register to register transfer
i - Register to memory transfer
- Memory to register transrer

Compare Instructions It perfoms the comparing and testing functions.

A condition code of 2 bit is set by the instruction.
Branching Instructions The value of conditional code determines the branch.
A special instruction called Branch and link is used
for subroutine call and return. The user need to
specify the register to be used for storing return address.
Convetsion Instructions Converts various forms of data for example, from
decimal to binary
Decimal Instructions Provided for providing operations on decimal data.
These instructions include arithmetic operations,
shifting operations and unpacking operations.
Floating point Instructions Add, subtract, multiply and divide instructions are
provided on 4 byte. 8 byte and 16 byte floating point
numbers.
Special purpose control These instruction causes a control passing. Example
Instructions of one such instruction is supervisory call which causes
an interrupt that results in passing the control to the
operating system.
Privileged UO Instructions These instructions are used for starting InputDutput
using a VO channels. One such command is start 110.
qrivileged System Control These instructions are issued only by the operating
Instructions system for controlling registers and data structures
which are needed by the operating system.

IBM 370 Addressing

In IBM 370 memory is addressable at byte level. However, all the addresses are virtual
addresses. In the system SP70 the length of virtual address is 24 bits whereas, the length in
case of IBM Sf370 XA it is 31 bits. In this system only three basic addressing modes are
supported. These are:
Immediate Addressing : It is a 1 byte operand, prov~dedwithin the instruction.
Register Addressing : In this mode a register operand is addressed. This register
operand can be in one of the 16 32-bit general purpose register or 4 64-bit floating
point registers. A register address consist of 4 bits as we have 16 general purpose
registers. However for the sake of consistency, even if we are referencing floating
point register which can be referenced by 2 bits (4 floating point registers), 4 bits
are used.
Displacement Addressing: In this mode the operand is stored in the virtual memory.
Here two type of formats are used :
The base register fomat: The operand reference in such scheme consist of two
components:
The displacement provided in the instruction
CPU Organls~llon The 4 bit register address, his register is one of h e general purpose register
and will bc uscd ss 3 b ~ s register.
c Howcvcr, only LAC right mob1 24 bits of
a 32 bit register are used for computing address in ISM 1360 whereas only
rightmost 31 bits are used in IBM 370 XA model. A register address 0
specifies that no register has been used and the displacement becomes the
direct address of memory location in that case.
Use of index register along with the base register:
In this scheme the instruction reference consist of the displacement, a four bit
reference to a general purpose register to be used as base register and a
general purpose register to be used as index register. The feature of
autoindexing is also provided.
Let us summarise the addressing modes used in IBML370.
Addressing Mode Calculation of egecrive address
Immediate Operand = A
Register EA = R
Displacement :
Base Register EA = A+(B)
Index on base register EA = A+(B)+(I)
I -+ Indicates address of index register. It will be 4 bit long.
B -+ Indicates address of the base register. It will be 4 bit long.

Figure 13 :Summary of D M V370 Addressing Modes

The addressing schemes provided by this system although are simple and easy yet a
programmer must understand how to use the segments in IBM systemL370. This discussion
is beyond the scope of this unit. You can refer to further readings for more derails.

Instruction Format
We will present a simplified tabular representation for the instruction format of IBM
systeml370.
Features:
Variable length instructions : bytes. 4 bytes, 6 bytes instructions
Variable opcode length 1 byte and 2 byte
Eight different instruction formats are used.
Mostly two operand instructions, however, one ana three operands are also used in
some instructions.
F i t two bits of instruction specifies:
length of the instruction and
format of the instruction
First two bits of opcode Instruction length (bytes) instruction opcode format
RR
RX
RREIRSISISI
SSISSE
The instruction,formats are:
Register-Register (R R) : A compact representation
Instruction length : 2bytes
0
- : 1 byte
Register addresses : 2 nos of 4 bit each.
Register : Used f a privileged instructions used by the
Register Extended operating system.
 InslrwtlonSets
Instruction length : 4 bytes
%ode : 2 byes
Register addresses : 2 o f l biteach
1 byte is unused.
-
Register-Indexed Instruction Length : 4bytes
(R Jo Opcode : 1 byte
First operand
Register operand : Oneof 4 bit
Second operand
Virtual memory operand : One 4 bit Index Register
4 bit base register
12 bit displacement
Register-Storage (R S) : Instruction lenglh : 4 byte
Number of operands : 3 (the only three
operand instruction
format)
opcode : 1 byte
First operand and Third
operand : Register operands
require 4 bit each for
register reference
Second operand : Virtual memory
operand using a base
register (4 bit) and
displacement (12 bits)
Storage lmmediate Instruction lenglh : 4bytes
(S 1) %ode : 1 byte
First operand : Virtual memory
operand using a base
register(4 bits) and
displacement (12 bits)
Second operand : Immediate operand
of one byte
Storage (S) Used for representing privileged instructions for I10
or system control.
Instruction lenglh : 4bytes
mode : 2bytes
Number of operands : one
Operand address is virtual address using a base
register (4 bits) and displacement (12 bits)
Storagc-Storage (S S) : Instruction lenglh : 6bytes
o~code : 1 byte
Number of operand = 2
both operands are virtual memory operands specified
by base register (4 bits) and displacement (12 bits)
Use of remaining 1 byte :
One length format : The remaining byte specifies
the number of bytes to be operated upon. Used for
moving a block of characters from one location to
another.
Two length format : two length fields of 4 bit each
specifying the size of each of the two operands.
Used for operations on BCD.
Register specifications : The byte designates two
general purpose registers which contains the conuol
*
information or lenglh specifications. Used for
privileged insuuctions.
Storage-Storage Extended : Used for privileged instructions
(S S E) Insmction length : 6 bytes
-Ode : 2 bytes
Two operands both in the form of base register
cPU o r p ~ h t l o n (4 bits) and displacem,ent (12 bits).
Thus,IBM SystemJ370formats tries to m a k efficient use of insuuction lengths. Figure 14
gives the summd of instruction formats of ihis system.

1-
R R Format R -+ Regiater addnaa
I -+ Index Regiater Addreas
B -+ Baae Register Address
A -+ Displacement
7 8 111
Subscript indicate aperand number
R R E Format
Opcode Not used R~ R2
0 15 16 23 24 27 28 31

R X Format

Opcode R1 I2 B2 A2
0 7 8 1112 1516 1920 31

R S Format

Opcode R1 Rj B2 A2
0 7 8 11 12 15 16 19 20 31

S I Format

S Format
Opcode B1 A1
0 15 16 19 20 31

S S Format
Special
Opcode use B1 A1 B2 A2
0 7 8 15 16 19 20 31 32 35 36 47

Special Use : One field of 8 bit specifying length of Block (One length format)
OR
T ~ Ofields of 4 bit each specifying length (Two length format)
OR
Two fields of 4 bit each of register address (Register specification)
S S E Format
Opcode B1 A1 B2 A2
0 15 16 19 20 31 32 35 36 47

Ftgwc I4 :Summary of lBM Syrtann70 Inrbudon tonnab

1.6 SUMMARY
In this unit, we have introduced you to various concepts relating to an instruction. We have
discussed about the basic characteristics, the number of addresses, type of operands and
operations in instructions and various addressing modes. We have also highlighted the basic
issues while designing instruction formals and presented details on the instruction set of IBM
 Instruction ScCl
[Link] note we have not provided you h e detailed insuuctions which his machine
provide. But only h e conceptu&model behind his instruction set. You can refer to furlher
reading for more details on instruction set for various machines.

1.7 MODEL ANSWERS

Check ~our"Progress1
1. False
2. False
3. False
4. False
5. True
6. False

Check Your Progress 2

- -
1. a (ii), b (iii), c (i) -
2. See section 1.2.2

3. (a) - (i), (iii); (b) - (u). (iv); ( CV : (dl-Nn.

4. The reasons are:
4 return address is needed

I
+ parameter passing
+ branching and coming back from a small program
1 5. Refer to sub-section on subroutinecalls.
I
Check Your Progress 3
1. No model answer
I 2. (a)False. (b) False. (c) True
3. Refer sub-section 1.3.6
4. Refer sub-section 1.3.6

Check Your Progress 4