11/16/2014

Copyright @IITBHU_CSE
Jagjit Singh(12100EN003)
Vivek Garg(12100EN009)
Shivam Anand(12100EN012)
Kshitij Singh(12100EN061)
Introduction As the price/performance of general
purpose graphic processors (GPGPUs) has
Supercomputer architectures were first improved, many petaflop supercomputers
introduced in the 1960s. A lot of changes such as Tianhe-I and Nebulae have started
have since been made since that time. to depend on them. However, other
Early supercomputer architectures systems such as the K computer continue
pioneered by Seymour Cray relied on to use conventional processors such
compact innovative designs and local as SPARC-based designs and the overall
parallelism to achieve superior applicability of GPGPUs in general purpose
computational performance. However, in high performance computing applications
time the demand for increased has been the subject under consideration,
computational power ushered in the age in that while a GPGPU may be tuned to
of massively parallel systems. perform well on specific benchmarks its
While the supercomputers of the 1970s overall applicability to everyday
used only a few processors, in the 1990s, algorithms may be limited unless
machines with many thousands of significant effort is spent to tune the
processors began to appear and as the application towards it. But GPUs are
20th century came to an end, massively gaining ground and in 2012 the Jaguar
parallel supercomputers with tens of supercomputer was transformed
thousands of "off-the-shelf" processors into Titan by replacing CPUs with GPUs.
were the norm. In the 21st century, As the number of independent processors
supercomputers can use as many as in a supercomputer increases, the method
100,000 processors connected by very fast by which they access data in the file
connections. system and how they share and
Systems with a massive number of access secondary storage resources
processors generally take one of two becomes prominent. Across the years a
paths: in one of the approaches, e.g., number of systems for distributed file
in grid computing the processing power of management were made, e.g., the IBM
a large number of computers in General Parallel File System, FhGFS,
distributed. Diverse domains are theParallel Virtual File System, Hadoop,
opportunistically used whenever a etc. A number of supercomputers on
computer is available. Another approach the TOP100 list such as the Tianhe-I
is to utilize many processors in close use Linux's Lustre file system.
proximity to each other, e.g., in
a computer cluster. In such
centralized massively parallel system the
speed the flexibility of the inter-connect
becomes very important, and modern
supercomputers have used approaches
ranging from enhanced Infiniband systems
to three-dimensional torus interconnects.
Background Pipelining was an innovation of the 1960s,
and by the 1970s the use of vector
processors had been well established.
The CDC 6600 series of computers were
Parallel vector processing had gained
very early attempts at supercomputing
ground by 1990. By the 1980s, many
and gained their advantage over the
supercomputers used parallel vector
existing systems by relegating work
processors.
to peripheral devices, freeing the CPU
(Central Processing Unit) to process In early systems the relatively small
valuable data. With the number of processors allowed them to
Minnesota FORTRAN compiler the 6600 easily use a shared memory architecture,
could sustain 500 kiloflops on standard hence processors are allowed to access a
mathematical operations. common pool of memory. Earlier a
common approach was the use of uniform
Other early supercomputers like the Cray
memory access (UMA), in which access
1 and Cray 2 that appeared afterwards
time to a memory location was similar
used a small number of fast processors
between processors. The use of non-
that worked in harmony and were
uniform memory access (NUMA) allowed
uniformly connected to the largest
a processor to access its own local
amount of shared memory that could be
memory faster than other memory
managed at the time.
locations, whereas cache-only memory
Parallel processing at the processor level architectures(COMA) allowed for the local
were introduced by these early memory of each processor to be used like
architectures, with innovations such a cache, thus requiring coordination as
as vector processing, in which the memory values changed.
processor can perform several operations
As the number of processors increases,
during one clock cycle, rather than having
efficient inter-processor
to wait for successive cycles.
communication and synchronization on a
In time, as the number of processors supercomputer becomes a challenge.
increased, different issues regarding Many different approaches may be used
architecture emerged. Two issues that to achieve this goal. For example, in the
need to be addressed as the number of early 1980s, in the Cray X-MP system used
processors increases are the distribution shared registers. In this approach, shared
of processing and memory. In the registers could be accessed by all
distributed memory approach, each processors that did not move data back
processor is packaged physically close and forth but were only used for inter-
with some local memory. The memory processor synchronization and
that is associated with other processors is communication. However, inherent
then "further away" based on challenges in managing a large amount of
bandwidth and latency parameters in non- shared memory among many processors
uniform memory access.
resulted in a move to more distributed architectures.

PROCESSOR YEAR CLOCK(MHZ) REGISTER FUCTIONAL UNITS

ELEMENT (PER
REGISTER)
CRAY-1 1976 80 8 64 6
CRAY-XMP 1983 120 8 64 8
CRAY-YMP 1988 166 8 64 8
NEC SX/2 1984 160 8+8192 256 16
variable
CRAY C-90 1991 240 8 128 8
NEC SX/4 1995 400 8+8192 256 16
variable
CRAY J-90 1995 100 8 64 8
CRAY T-90 1996 500 8 128 8
NEC SX/5 1999

Approaches to supercomputing GPUs, and the rest from various CPU

systems.

Distributed supercomputing The BOINC platform hosts a number of

distributed computing projects. By May
Opportunistic Supercomputing is a form 2011, BOINC recorded a processing power
of networked grid computing whereby a of as much as 5.5 petaflops through over
“super virtual computer” of many loosely 480,000 active computers on the
coupled volunteer computing machines network. The most active project
performs very large computational tasks. (measured by computational power)
Grid computing has been applied to a reports processing power of over
number of large-scale embarrassingly 700 teraflops through as much as 33,000
parallel problems that require active computers.
supercomputing scale of performance.
As of May
However, basic grid and cloud
2011, GIMPS's distributed Mersenne
computing approaches that rely
Prime search currently achieves about 60
on volunteer computing cannot handle
teraflops through over 25,000 registered
traditional supercomputing tasks such as
computers. The server of the Internet
fluid dynamic simulations.
PrimeNet supports GIMPS's grid
The fastest grid computing system is computing approach, among the earliest
the distributed computing project, 43.1 and most successful grid computing
petaflops of x86 processing power as of projects since 1997.
June 2014. Of this, 42.5 petaflops are
contributed by clients running on various
Quasi-opportunistic approaches The computer clustering approach
connects a number of readily available
Quasi-opportunistic supercomputing is a
computing nodes (e.g. personal
form of distributed computing whereby
computers used as servers) via a fast,
the “super virtual computer” of a large
private local area network. The activities
number of networked geographically
of the computing nodes are orchestrated
disperse computers performs computing
by "clustering middleware" which is a
tasks that demand huge processing
software layer that sits atop the nodes
power. Quasi-opportunistic
and allows the users to treat the cluster as
supercomputing aims to provide a higher
by and large one cohesive computing unit,
quality of service than opportunistic grid
for example via a single system
computing by achieving more control over
image concept.
the assignment of tasks to distributed
resources and the use of intelligence Computer clustering relies on a
about the availability and reliability of centralized management approach which
individual systems within the makes the nodes available as
supercomputing network. Whereas quasi- orchestrated shared servers. It is different
opportunistic distributed execution of from other approaches such as peer to
demanding parallel computing software in peer or grid computing which also use a
grids should be achieved through large number of nodes, but with a far
implementation of grid-wise agreements more distributed nature. By the 21st
of allocation, co-allocation subsystems, century, the TOP500 organization's semi
communication topology-aware allocation annual list of the 500 fastest
mechanisms, message passing libraries supercomputers often includes many
that are fault tolerant and data pre- clusters like the world's fastest in 2011,
conditioning. the K computer which had a distributed
memory and a cluster architecture.
When a large number of local semi-
Massive, centralized parallelism
independent computing nodes are used
During the 1980s, as the computing power (e.g. in a cluster architecture) the speed
demand increased, the trend to a much and flexibility of the interconnect
larger number of processors began, becomes very important. Modern
bringing in the age of massively supercomputers have taken various
parallel systems, with distributed approaches to resolve this issue,
memory and file systems, provided e.g. Tianhe-1 uses a proprietary high-
that shared memory architectures could speed network based on
not scale to a large number of the Infiniband QDR, enhanced
processors. Hybrid approaches such with FeiTeng-1000 CPUs. On the other
as distributed shared memory also hand, the Blue Gene/L system uses a
appeared after the early systems. three-dimensional torus interconnect with
auxiliary networks for global
communications. In this approach each well as the reliable availability of
node is connected to its six nearest resources at a given time.
neighbours. Likewise a torus was used by In quasi-opportunistic supercomputing a
the Cray T3E. large number of geographically disperse
Massive centralized systems at times use computers are orchestrated with built-in
special-purpose processors designed for a safeguards. The quasi-opportunistic
specialised application, and may use field- approach goes beyond volunteer
programmable gate arrays (FPGA) chips to computing on a highly distributed systems
gain performance by sacrificing generality. for example BOINC, or general grid
Such special-purpose supercomputers computing on a system such as Globus by
have examples like Belle, Deep allowing the middleware to provide
Blue, and Hydra, for almost seamless access to many
playing chess, MDGRAPE-3 for protein computing clusters so that existing
structure computation molecular programs in languages such
dynamics and Deep Crack for breaking as Fortran or C can be distributed among
the DES cipher. multiple computing resources.
Massive distributed parallelism Quasi-opportunistic supercomputing aims
to provide a higher quality of service
Grid computing uses a large number of
than opportunistic resource sharing. The
computers in diverse, distributed
quasi-opportunistic approach enables the
administrative domains which makes it an
execution of demanding applications
opportunistic approach which uses
within computer grids by establishing grid-
resources whenever they are available. An
wise resource allocation agreements;
example is BOINC a volunteer-based,
and fault tolerant message passing to
opportunistic grid
abstractly shield against the failures of the
system. Some BOINC applications have
underlying resources and maintaining
reached multi-petaflop levels by using
some opportunism as well as allowing a
close to half a million computers
higher level of control.
connected on the web, whenever
volunteer resources become
available. However, these types of results Vector processing principles
often do not appear in the TOP500 ratings Ordered set of scalar data items is known
because they do not run the general as vector. all the data items are of same
purpose Linpack benchmark. type stored in memory. generally the
Although grid computing has had success vector elements are ordered to have fixed
addressing increment between successive
in parallel task execution but demanding
elements , called stride.
supercomputer applications such
as weather simulations or computational Vector processor includes processing
fluid dynamics have not been successful, elements, vector registers, register
partly due to the barriers in reliable sub- counters and functional pipelines, to
assignment of a large number of tasks as perform vector operations. Vector
processing involves arithmetic or logical amortized. Thus, the cost of the
operations applied to vectors whereas latency to main memory is seen
scalar processing operates on one datum. only once for the entire vector,
The conversion from scalar code to vector rather than once for each word of
code is called vectorization the vector.
 Control hazards are no longer
Vector processors are special purpose present since an entire loop is
computers that match a range of replaced by a vector instruction
computing (scientific) tasks. These tasks whose behaviour is determined
usually consist of large active data sets, beforehand .
poor locality, and long run times and in
addition, vector processors provide vector Typical vector operations include (integer
instructions. and floating point:
Vector processors are special purpose  Add two vectors to produce a
computers that match a range of third.
(scientific) computing tasks. These tasks  Subtract two vectors to produce a
usually consist of large active data sets, third
often poor locality, and long run times. In  Multiply two vectors to produce a
addition, vector processors provide vector third
instructions.  Divide two vectors to produce a
These instructions operate in a pipeline third
(sequentially on all elements of vector  Load a vector from memory
registers), and in current machines. Some  Store a vector to memory.
properties of vector instructions are
 Since the calculation of every These instructions could be augmented to
result is independent of the do typical array operations:
calculation of previous results it  Inner product of two vectors
allows a very deep pipeline (multiply and accumulate sums)
without any data issues.
 Outer product of two vectors
 A vector instruction requires a (produce an array from vectors)
huge amount of work since it is the
 Product of (small) arrays (this
same as executing an entire loop. would match the programming
Hence, the instruction bandwidth
language APL which uses vectors
requirement is decreased. and arrays as primitive data
 Vector instructions that require elements.)
memory have a predefined access
pattern that can easily be
predicted. If the vector elements Hence vector processing is faster and
are all near each other, then much more efficient than scalar
obtaining the vector from a set of processing. Both SIMD computers and
heavily interleaved memory banks pipelined processors can perform vector
works extremely well. Because a operations. Vector processing generates
single access is initiated for the one result per clock cycle by continuously
entire vector rather than to a
matching with the pipelining and
single word, the high latency of
segmentation concepts. It also reduces
starting a main memory access
against accessing a cache is
the memory access conflicts and software vector and scalar operations, a vector
overhead. processor can achieve a manifold speed
up which could go up to 10 to 20 times, as
Depending on the vectorization ratio in
compared to conventional machines.
user programs and speed ratio between

Vector instruction types ‘Gather’ fetches the non-zero

Six types of vector instructions are elements from memory of a sparse
vector using indices that
 Vector-vector instructions themselves are indexed.
One or two vector operands Scatter, on the other hand, does
may be fetched from their vector the opposite: storing into memory
registers which then enter through a vector in a sparse vector whose
a functional pipeline unit, and non zero entries are indexed
produce results in another vector  Masking instructions
register. These instructions use a mask
 Vector scalar instructions vector to expand or to compress a
 Vector memory instructions vector to an index vector that is
 Vector reduced instructions either longer or shorter.
 Gather and scatter instructions
These use two vector registers to
gather or to scatter vector
elements randomly throughout
the memory.
Vector access memory schemes that usually acquire data with
Usually, multiple access paths pipeline the certain stride which is the
flow of vector operands between the distinction between addresses
main memory and vector registers. associated with consecutive vector
elements.
 Vector operand specifications  Register files and highly
Vector operands can be arbitrarily interleaved memories are usually
long. Vector elements may not be used to achieve a high memory
stored in memory locations that bandwidth required for vector
are contiguous. processing.
To access a vector, its base
It is not clear whether cache memories
address, stride, and length must be
can boost the performance of such
described. Since every vector
systems.
register has a predefined number Although cache memories have the
of component registers, in a fixed capability for boosting the performance of
number of cycles, only a small part future vector processors, numerous
of the vector can be loaded to the reasons counter the use of vector caches.
vector register. A single miss in the vector cache results in
 C-Access memory organisation. a number of processors. Stall cycles equal
 S-Access memory organisation. to the entire memory access time,
 C/S-Access memory organisation. however the memory accesses of a vector
processor without cache are fully
The Effect of cache design into pipelined. In order to benefit from a
vector computers vector cache, the miss ratio must be kept
extremely small. In general, cache misses
Cache memories have proven to be very
can be classified into these categories:
successful in the case of general purpose
 Compulsory miss
computers to boost system performance.
 Capacity miss
However, their use in vector processing
has not yet been fully established.  Conflict miss
Generally, the existing supercomputer
vector processors do not have cache The compulsory misses occur in the initial
loading of data, which are easily pipelined
memories because of the results drawn
from the following points: in a vector computer. Next, the capacity
misses are because of the size restrictions
 Generally the data sets of
numerical programs are too large of a cache to retain data between
references. If algorithms are blocked as
for the cache sizes provided by the
mentioned, the capacity misses can be
present technology. Sweep
linked to the compulsory misses during
accesses of a large vector may end
up completely reloading the cache the initial loading of every block of data
given that the block size is lesser than that
before the processor can even
of cache. Finally, conflict misses, plays a
reuses them.
deciding role in the vector processing
 Sequential addresses which are a
environment. Conflicts occur when
crucial assumption in the
elements of the same vector are mapped
conventional caches may not
directly to the same cache elements or
prove to be as effective in
line from two different vectors compete
vectorised numerical algorithms
for the same cache line. Since conflict supplant dedicated workstations for a
misses that reduce vector cache host of compute intensive applications. At
performance to do with vector access a deeper level GPU evolution depends on
stride, size of an application problem can the assumption of a processing model
be adjusted to make a good access stride that can achieve the highest possible
for a machine. This approach burdens a performance for a wide variety of graphics
programmer for knowing architecture algorithms. This then drives all relevant
details of a machine as well as it is aspects of hardware architecture and
infeasible for many applications. design. The most efficient GPU processing
Ideas like prime-mapped cache schemes model is Single Instruction Multiple Data
have been studied. The new cache (SIMD). The SIMD model has been of great
organization reduces cache misses due to use in traditional vector
cache line interferences that are critical in processor/supercomputer designs, (e.g.
numerical applications. Also, the cache Cray X-MP, Convex C1, CDC Star-100), by
lookup time of the new mapping scheme capability to boost datapath calculation
stays the same as conventional caches. based upon concurrent execution of
Creation of cache addresses for accessing processing threads. The SIMD concept has
the prime-mapped cache can be done been employed in recent CPU
parallel along with normal address architectural advancements, like the IBM
calculations. This address creation takes Cell processor, x86 with MMX extensions,
lesser time than the normal address SPARC VIS, Sun MAJC, ARM NEON etc.
calculation because of the special SIMD processing model adopted for GPU
properties of the Messene prime. Thus, can be used for general classes of
the new mapping scheme doesn’t cause scientific computation not specifically
any performance penalty in terms of the associated with graphics applications. This
cache access. With this new mapping was the start of the General Purpose
scheme, the cache memory can show a computing on GPU (GPGPU) movement
large amount of performance boost, and basis for many examples of GPU
which will increase as the speed gap accelerated scientific processing.
between processor and memory is GPGPU closely depends upon Application
increased. Programming Interface (API) access to
resources of GPU processing; GPU API
GPU based supercomputing abstracts much of the complexity
associated with manipulation of hardware
resources and provides convenient access
The demand for an increased Personal
Computer (PC) graphics subsystem to I/O, memory management, and thread
management functionality in form generic
performance never ceases. The GPU is an
ancillary coprocessor subsystem, programming function calls, (e.g. C, C++,
Python, Java). Thus, GPU hardware is
connected to an internal high-speed bus
and memory-mapped into global memory virtualized as a standard programming
resource, facilitating uninhibited
resources. Computer vision, gaming, and
application development incorporating
advanced graphics design applications
GPU acceleration. APIs that are currently
have led to sharp MIPS performance
in use include NVIDIA’s Compute Unified
boosts and increased variety and
Device Architecture (CUDA) and ATI’s
algorithmic efficiency on part of relevant
Data Parallel Virtual Machine (DPVM).
graphics standards. All this is a part of a
larger evolutionary trend whereby PCs
 calculation for ‘P’; pipelining effectively
GPU Architecture parallelizes CPU and GPU code segments
reducing the non-parallelized code
SIMD GPU is organized as a collection of fraction '(1- P)'. Thus, under circumstances
where decrease is sufficient to claim (P).
‘N’ distinct multiprocessors, each
consisting of ‘M’ distinct thread Hence, well-motivated software
architecture design can take advantage of
processors. Multiprocessor operation is
modulo an ensemble of threads managed this effect, greatly increasing acceleration
potential for the complete application.
and scheduled as a single entity, (i.e.
‘warp’). Like this, SIMD instruction fetch 21st-century architectural trends
and execution, shared-memory access,
The air cooled IBM Blue
and cache operations are completely
synchronized. Memory usually is Gene supercomputer architecture trades
organized hierarchically where processor speed for low power
Global/Device memory transactions are consumption so that a larger number of
understood as mediated by high-speed processors can be used at room
bus transactions, ([Link], temperature, by using normal air-
HyperTransport). conditioning. The second generation Blue
A feature associated with the CPU/GPU
Gene/P system is distinguished by the fact
processing architecture is GPU processing
is essentially non-blocking. Hence, CPU that each chip can act as a 4-
may continue processing as soon as a way symmetric multiprocessor and also
work-unit has been written to the GPU includes the logic for node-to-node
transaction buffer. GPU work unit communication. And at
assembly/disassembly and I/O at the GPU 371 MFLOPS/W the system is very energy
transaction buffer may to large extent be
efficient.
hidden. In these case, GPU performance
will effectively dominate the performance The K computer has water cooling system,
of the entire system. Optimal GPU homogeneous processor and distributed
processing gain is achieved at an I/O memory system with a cluster
constraint boundary whereby thread
architecture. It uses more than 80,000
processors never stall due to lack of data.
processors which are SPARC based, each
The maximum achievable speedup is
governed by Amdahl’s Law: any with eight cores, for a total of over
acceleration (‘A’) due to thread 700,000 cores – almost twice as many as
parallelization will critically depend upon: any other system and more than 800
 The fraction of code than can be cabinets, each with 96 computing nodes
parallelized (‘P’) ,each with 16 GB of memory , and 6 I/O
 The degree of parallelization (‘N’),
nodes although it is more powerful than
and
the next five systems on the TOP500 list
 Any overhead associated with
parallelization combined, at 824.56 MFLOPS/W but it
has the lowest power to performance
This indicates a theoretical maximum ratio of any current major supercomputer
acceleration for the application. CPU code system. The follow up system, called the
pipelining (i.e. overlap with GPU PRIMEHPC FX10 uses the same six-
processing) must also be factored into any
dimensional torus interconnect, but only memory address problems in an efficient
one SPARC processor per node. manner, for the same type of
programs. Blue Waters had been expected
Unlike the K computer, the Tianhe-
to run at sustained speeds of at least one
1A system uses a hybrid architecture and
petaflop which relied on the specific
integrates CPUs and GPUs. It uses more
water-cooling approach to manage heat.
than 14,000Xeon general-purpose
The National Science Foundation spent
processors and greater than 7,000 Nvidia
about $200 million on the project in the
Tesla graphic-based processors on about
first four years of operation. IBM released
3,500 blades. It has 112 computer
the Power 775 computing node derived
cabinets and 262 terabytes of distributed
from that project's technology soon , but
memory; 2 petabytes of disk storage is
effectively abandoned the Blue Waters
implemented via Lustre clustered
approach.
files. Tianhe-1 uses a proprietary high-
speed communication network to connect Architectural experiments are continuing
the processors. The proprietary in a number of directions, for example
interconnect network was based on the Cyclops64 system uses a
the Infiniband QDR, along with Chinese supercomputer on a chip approach,
made FeiTeng-1000 CPUs. In the case of contrasting the use of massive distributed
the interconnect the system is twice as processors. Each 64-bit Cyclops64 chip
fast as the Infiniband, but is slower than contains 80 processors with the entire
some interconnects on other system using a globally
supercomputers. addressable memory architecture. The
processors are connected with non-
The limits of specific approaches continue
internally blocking crossbar switch and
to be tested through large scale
communicate with each other via global
experiments, such as in 2011 IBM ended
interleaved memory with no data cache in
its participation in the Blue
the architecture, while half of
Waters petaflops project at the University
of Illinois. The Blue Waters architecture each SRAM bank can be used as a
scratchpad memory. Although this type of
was based on the IBM POWER7 processor
architecture allows unstructured
and intended to have 200,000 cores with
parallelism in a dynamically non-
a petabyte of "globally addressable
contiguous memory system but it also
memory" and 10 petabytes of disk
produces challenges in the efficient
space. The goal of a sustained petaflop led
to design choices that optimized single- mapping of parallel algorithms to a many-
core system.
core performance, and a lower number of
cores which is then expected to help Issues and challenges
performance on programs that did not
we could significantly increase the
scale well to a large number of
performance of a processor by issuing
processors. The large globally addressable
multiple instructions per clock cycle and
memory architecture aimed to solve
by deeply pipelining the execution units
to allow greater exploitation of instruction alternative approach to controlling
level parallelism. But there are serious multiple functional units with deep
difficulties in exploiting ever larger pipelines. Vector processors provide high-
degrees of instruction level parallelism. level operations that work on vectors. A
typical vector operation might add two
As we increase both the width of
floating-point vectors of 64 elements to
instruction issue and the depth of the
obtain a single 64-element vector result.
machine pipelines, we as well increase the
This instruction is equivalent to an entire
number of independent instructions
loop, in which each iteration is computing
required to keep the processor busy with
one of the 64 elements of the result and
useful work. This means an increase in the
updating the indices, and branching back
number of partially executed instructions
to the beginning. Vector instructions have
that can be in flight at one time. For a
several important properties that solve
dynamically-scheduled machine
most of the problems mentioned above:
hardware structures, such as reorder
buffers, instruction windows ,and rename
register files, must grow to have sufficient A single vector instruction describes a
capacity to hold all in-flight instructions,
great deal of work—it is equivalent to
and worse, the number of ports on each executing an entire loop where each
element of these structures must grow instruction represents tens or hundreds of
with the issue width. The logic to track
operations, and so the instruction fetch
dependencies between all in-flight and decode bandwidth needed to keep
instructions grows quadratically in the multiple deeply pipelined functional units
number of instructions. Even a VLIW busy is dramatically reduced.
machine, which is statically scheduled and
shifts more of the scheduling burden to
the compiler, needs more registers, more By using a vector instruction, the compiler
ports per register, and more hazard or programmer indicates that the
interlock logic (assuming a design where computation of each result in the vector is
hardware manages interlocks after issue independent of the computation of other
time) to support more in-flight results in the same vector and so
instructions, which similarly cause hardware does not have to check for data
quadratic increases in circuit size and hazards within a vector instruction. The
complexity. This rapid increase in circuit elements in the vector can be computed
complexity makes it difficult to build using an array of parallel functional units,
machines that can control large numbers or a single very deeply pipelined
of in-flight instructions which limits functional unit, or any mixed
practical issue widths and pipeline depths. configuration of parallel and pipelined
Vector processors were successfully functional units.
commercialized long before instruction
level parallel machines and take an
Hardware need only check for data operations include not only the arithmetic
hazards between two vector instructions operations, but also memory accesses and
once per vector operand and not once for effective address calculations. Also, most
every element within the vectors. That high-end vector processors allow multiple
means the dependency checking logic vector instructions to be in progress at the
required between two vector instructions same time, creating further parallelism
is approximately the same as that among the operations on different
required between two scalar instructions, vectors.
but now many more elemental operations
can be in flight for the same complexity of
control logic. Vector processors are particularly useful
for large scientific and engineering
applications, such as car crash simulations
Vector instructions that access memory and weather forecasting, for which a
have a known access pattern then typical job might take dozens of hours of
fetching the vector from a set of heavily supercomputer time running over multi
interleaved memory banks works very gigabyte data sets. Multimedia
well if the vector’s elements are all applications can also benefit from vector
adjacent. The high latency of initiating a processing, as they contain abundant data
main memory access versus accessing a parallelism and process large data
cache is amortized as a single access is streams. A high-speed pipelined processor
initiated for the entire vector not just to a will usually use a cache to avoid forcing
single word. Hence the cost of the latency memory reference instructions to have
to main memory is seen only once for the very long latency. Unfortunately, big
entire vector and not for each word of the scientific programs often have very large
vector. active data sets that are sometimes
accessed with low locality hence yielding
poor performance from the memory
Because an entire loop is replaced by a hierarchy. This problem could be
vector instruction whose behaviour is overcome by not caching these structures
predetermined the control hazards that if it were possible to determine the
would normally arise from the loop memory access patterns and pipeline the
branch are non-existent. For these memory accesses efficiently. Compiler
reasons, vector operations can be made assistance and novel cache architectures
faster than a sequence of scalar through blocking and prefetching are
operations on the same number of data decreasing these memory hierarchy
items, and if the application domain can problems, but still they continue to be
use them frequently, designers are serious in some applications.
motivated to include vector units. As
mentioned above, vector processors
pipeline and parallelize the operations on
the individual elements of a vector. The
Application
All the expensive machines are
The machine can be used in scientific and simulated before their actual
business applications, but more suited to construction to prevent economic
scientific applications. Large multinational losses and saving of time. Life
banks and corporations are using small threating stunts are simulated before
supercomputers. Some of the applications
performed which can predict any
include; special effects in film, weather
technical or other fault and prevent
forecasting, processing of geological data
damage.
and data regarding genetic decoding,
Movies
aerodynamics and structural designing,
These are used to produce special effects.
mass destruction weapons and
Movies like The Star trek, Star fighter,
simulation. The users include; Film
Babylon 5, Terminator’s sequel, Dante’s
makers, Geological data processing Peak, Asteroid, Jurassic Park, The Lost
agencies, National weather forecasting World, Matrix’s sequel, Lord of the Rings,
agencies, Space agencies, Genetics Godzilla and all the latest movies have
research organizations, Government special effects generated on
agencies, Scientific laboratories,, Military supercomputers.
and defence systems, research groups and
Large corporations.
Weather forecasting
Simulation Data is collected from worldwide network
Duplicating an environment is called of space satellites, ground stations and
simulation. It is done for reasons like; airplanes, is fed in to supercomputer for
analysis to forecast weather. Thousands
Training of the users of variables are involved in weather
forecasting and can only be processed on
Predict/forecast the result a supercomputer. Accurate predictions
If physical experimentation is not possible cannot be made beyond one month
If physical experimentation is very because we need more powerful
expensive computers to do so.

Oil Exploration
To determine the most productive oil
exploration sites millions of pieces of data
is processed. Processing of geological data
involves billions of pieces of data and
thousands of variables, a very complex
calculation requiring very large computing
power.

Genetics engineering
Used for the processing and decoding of
genetic data this is used by genetics
scientists and engineers for research and simulation and modelling for these
development to immune human beings designs and tests include processing of
from heredity diseases. Since genetics billions of pieces of data and solving
data processing involves thousands of numerous complex mathematical
factors to be processed supercomputers calculations for supercomputers.
are the best choice. The latest
developments, like gene mapping and Nuclear weapons
cloning also require the capabilities of
supercomputers. Simulation is also used for the production
of mass destruction weapons to simulate
Space exploration the results of an atomic or nuclear bomb
Great achievements are simply impossible formula. For this reason, USA government
without supercomputers. The remarkable is very cautious about the production and
accuracy and perfection in the landing of export of this computer to several
pathfinder on the Mars is another proof of nations. Some of the famous export deals
the capabilities of this wonderful machine. include.
Famous IBM processor technology
RISC/6000 used as in flight computer, that • America provided Cray supercomputer
was modified for the project, made of type XMP to India for weather data
hardened and called RAD/6000. processing.

Aerodynamic designing of airplanes • USA supplied a supercomputer to China

In manufacturing of airplanes, for peaceful nuclear research.
supercomputer to use to simulate the
passage of air around separate pieces of • International Business Machines
the plane and then combine the results, Corporation exported supercomputer
Today’s super computers are still unable RISCJ6000 SP to Russia, and they used it
to simulate the passage of air around an for their nuclear and atomic research
entire aircraft. purposes. This deal put International
Business Machines Corporation under
strong criticism by the US government.
Aerospace and structural designing
Conclusion and future work
Simulation in aerospace and structural
designing was used for the space station
Given the current progress rate, industry
and space plane. These projects required experts estimate that supercomputers will
extensive experiments, some of which are reach 1 exaflops (1018, one quintillion
physically impossible. Such as, the FLOPS) by 2018. China describes plans to
proposed space station would collapse
have a 1 exaflop supercomputer online by
under its own weight if built in the gravity 2018. Using the Intel multi-core processor,
of Earth. The plane must be able to take which is Intel's response to graphics
off from a runway on Earth and accelerate
processor unit (GPU) systems, SGI plans to
directly into orbit at speeds greater than achieve a 500 times increase in
8,800 miles per hour. Most of these performance by 2018, in order to achieve
conditions cannot be duplicated; the one extra flop. Samples of MIC chips with
32 cores, which combine VPU with recent Top 500 list. But the amount of
standard CPU, have become available. data being put to servers is outpacing the
The government of India has also stated growth of supercomputing speeds.
ambitions for an exaflop-range Networks are not going faster, the chip
supercomputer, which they hope to clock speeds are not increasing and there
complete by 2017.].In November 2014 it is not a huge increase in data-access time.
Applications no longer live in the classic
was reported that India is working on the
compute microprocessors; instead
Fastest supercomputer ever which is set
application and workflow computation are
to work at 132 Exaflops per second.
distributed throughout the system
hierarchy.
Supercomputers with this new
A simple example of reducing the size of
architecture could be out within the next data sets by decomposing information in
year. The aim is to improve data storage, which can then be moved to
processing at the memory, storage and memory of the computer. That type of
I/O levels. model can be applied to oil and gas
workflow -- which typically takes months -
That will help break down parallel - and it would significantly shorten the
computational tasks into small parts, time required to make decisions about
reducing the compute cycles required to drilling.
solve problems. That is one way to A hierarchy of storage and memory
overcome economic and scaling including non-volatile RAM, which means
limitations of parallel computing that much lower latency, higher bandwidths,
affect conventional computing models. without the requirement to move the
data all the way back to central storage.
Memory, storage and I/O work in tandem Following conventional computing
to boost system performance, but there architectures such as the Von Neumann's
are bottlenecks with present approach, in which data is put into a
processor, calculated and put back in the
supercomputing models. A lot of energy
memory. Most of the computer systems
and time is wasted in continuously moving
today work on the type of architecture
large chunks of data between processors,
only, which was derived in the 1940's by
memory and storage. Decreasing the
mathematician named John von
amount of data that has to be moved, Neumann.
which could help process data increase At the individual compute element level,
three times faster than current we continue the Von Neumann's
supercomputing models. approach. At the level of the system,
however, an additional way to compute,
When working with petabytes and which is to move the evaluate to the data
exabytes of data, moving this amount of is provided. There are multiple ways to
data is extremely inefficient and time reduce latency in a system and reduce the
consuming, so processing to the data can amount of data which has to be moved.
be moved by providing compute capability This saves energy as well as time.
throughout the system hierarchy. Moving computing closer to data in
IBM has built the world's fastest storage or memory is not a new concept.
computers for decagon, including the appliances and servers with CPUs targeted
third- and fifth-fastest, according to a at specific workloads, and with
disaggregating storage, memory and the world's first and only quantum based
processing subsystems into separate computer, which is being used by NASA,
boxes are built which can be improved by Lockheed Martin and Google for specific
optimizing entire supercomputing tasks. The others are in phase of
workloads that involve simulation, experiments. IBM has built an
modeling, visualization and complex experimental computer with a chip
analytics on massive data sets. designed to mimic a human brain.
The model will work in research areas like
oil and gas life sciences, exploration,
materials research and weather
modelling. Applications will need to be
written and well-defined for processing at
different levels and IBM is working with
institution, companies and researchers to
define software models for key sectors.
The fastest supercomputers today are
calculated with the LINPACK benchmark, a
simple measurement based on fractional
(float) point operations. IBM is not
ignoring Top 500, but providing a different
approach to enhance supercomputing.
LINPACK is good to measure speed, but
has under-represented the utility of
supercomputers and the benchmark does
not fully account for specialized
processing elements like int processing
and FPGAs.
The Top 500 list measures some elements
of the behaviour of compute nodes, but it
is not complete in terms of its
characterization of workflows that require
merging modelling, simulation and
analytics but many classic applications
are only moderately related to the
measure of LINPACK
Different organizations building
supercomputers have studied to build
software to take advantage of LINPACK,
which is worse measurement of
supercomputing performance.
The actual performance of some
specialized applications goes far beyond
LINPACK, and IBM's seems convincing.
There are companies developing
computers that give a new spin on how
data is accessed and interpreted. System
(D-Wave) is offering what is believed to be
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