Digital Fundamentals

ELEVENTH EDITION
GLOBAL EDITION

CHAPTER 7
Latches, Flip-Flops,
and Timers

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
7.1 Latches

The latch is a type of temporary storage device that has two stable states
(bistable) and is normally placed in a category separate from that of flip-flops.
Latches are similar to flip-flops because they are bistable devices that can reside
in either of two states using a feedback arrangement, in which outputs are
connected back to the opposite inputs.

 The S-R (SET-RESET) Latch

A latch is a type of bistable logic device or multivibrator. Notice that the output
of each gate is connected to an input of the opposite gate. This produces the
regenerative feedback that is characteristic of all latches and flip-flops.

FIGURE 7-1 Two versions of SET-RESET (S-R) latches.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 _ _
FIGURE 7-2 Negative-OR equivalent of the NAND gate S-R latch in Figure 7-1(b).

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 The three modes of basic S-R latch operation (SET, RESET, no-change)
and the invalid condition.
__
FIGURE 7-3

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 TABLE 7–1 Truth table for an active-LOW input S-R
latch.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
S R Q Q’
1 1 IC IC
1 0 1 0
0 1 0 1
0 0 NC NC

_ _
FIGURE 7-4 Logic symbols for the S-R and S-R latch.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 _ _
Example: If the S and R
waveforms in Figure given
below are applied to the inputs
of the latch in Figure given
right side, determine the
waveform that will be observed
on the Q output. Assume that
Q is initially LOW.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
An Application:

When the pole of a switch strikes the contact upon switch

closure, it physically vibrates or bounces several times
before finally making a solid contact. Although these
bounces are very short in duration, they produce voltage
spikes that are often not acceptable in a digital system.

__
FIGURE 7-6 The S-R latch used to eliminate switch contact bounce.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
An Application:
_
The switch is normally in position 1, keeping R input LOW
and latch RESET. When the switch is thrown to position 2,
_ _
R goes HIGH because of the pull-up resistor to Vcc, and S
goes LOW_ on the first contact.
Although S remains LOW for only a very short time before
the switch bounces, this is sufficient
_ to set the latch. Any
further voltage spikes on the S input due to switch
bounce do not affect the latch and it remains SET.

__
FIGURE 7-6 The S-R latch used to eliminate switch contact bounce.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 _
Notice that two of the latches each have two S inputs.

_ _
FIGURE 7-7 The 74HC279A quad S-R latch.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 The Gated S-R Latch

A gated latch requires an enable input, EN (G is also used to designate an enable

input). The S and R inputs control the state to which the latch will go when a
HIGH level is applied to the EN input. The latch will not change until EN is HIGH;
but as long as it remains HIGH, the output is controlled by the state of the S and
R inputs. The gated latch is a level-sensitive device. In this circuit, the invalid
state occurs when both S and R are simultaneously HIGH and EN is also HIGH.

FIGURE 7-8 A gated S-R latch.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Determine the Q output waveform if the inputs shown in Figure are applied to a
gated S-R latch that is initially RESET.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 The Gated D Latch

Another type of gated latch is called the D latch. It differs from the S-R latch
because it has only one input in addition to EN. This input is called the D (data)
input.
When the D input is HIGH and the EN input is HIGH, the latch will set.
When the D input is LOW and the EN input is HIGH, the latch will reset.
Stated another way, the output Q follows the input D when EN is HIGH.

FIGURE 7-10 A gated D latch.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Determine the Q output waveform if the inputs shown in Figure are applied to
a gated D latch, which is initially RESET.

When D is HIGH and EN is HIGH, Q goes HIGH.

When D is LOW and EN is HIGH, Q goes LOW.
When EN is LOW, the state of latch is not affected by the D input.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Gated D Latch

FIGURE 7-12 The 74HC75 quad D latch.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
7.2 Flip-Flops

Flip-flops are synchronous

bistable devices, also known
as bistable multivibrators. In
this case, the term
synchronous means that the
output changes state only at
a specified point (leading or
trailing edge) on the
triggering input called the
clock (CLK) which is
designated as a control
input C; that is, changes in
the output occur in
synchronization with the
clock.
Flip-flops are edge-triggered
or edge-sensitive whereas
gated latches are level-
sensitive.
FIGURE 7-13 Edge-triggered flip-flop logic
symbols (top: positive edge-triggered; bottom:
negative edge-triggered).

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 The D Flip-Flop

The D input of the D flip-flop is a synchronous input because data on the input
are transferred to the flip-flop’s output only on the triggering edge of the clock
pulse.
When D is HIGH, the Q output goes HIGH on the triggering edge of the clock
pulse, and the flip-flop is SET. Then D is LOW, the Q output goes LOW on the
triggering edge of the clock pulse, and the flip-flop is RESET.

FIGURE 7-14 Operation of a positive edge-triggered D flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 TABLE 7–2 Truth table for a positive edge-triggered
D flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
_
Determine the Q and Q output waveforms of
the flip-flop in Figure shown in right side, for
the D and CLK inputs in Figure-b. Assume
that the positive edge-triggered flip-flop is
initially RESET.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
S R Q Q’
1 1 IC IC
1 0 1 0
0 1 0 1
0 0 NC NC

_ _
FIGURE 7-4 Logic symbols for the S-R and S-R latch.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 The J-K Flip-Flop

The J and K inputs of the J-K flip-flop are synchronous inputs because data on
these inputs are transferred to the flip-flop’s output only on the triggering edge of
the clock pulse. When J is HIGH and K is LOW, the Q output goes HIGH on
triggering edge of the clock pulse, and the flip-flop is SET. When J is LOW and K
is HIGH, the Q output goes LOW on triggering edge of the clock pulse, and the
flip-flop is RESET.

When both J and

K are LOW, the
output does not
change from its
prior state. When
J and K are both
HIGH, the flip-
flop changes
state. This called
the toggle mode.

FIGURE 7-17 Operation of a positive edge-triggered J-K flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 TABLE 7–3 Truth table for a positive edge-triggered
J-K flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

The waveforms in Figure are applied to the J, K, and clock inputs as indicated.
Determine the Q output, assuming that the flip-flop is initially RESET.

Since the negative edge-triggered flip-flop, as indicated by the «bubble» at the

clock input, the Q output will change only on the negative-going edge of the
clock pulse.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Given the waveforms in Figure for the input and the clock, determine the Q
output waveform if the flip-flop starts out RESET.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Edge-Triggered Operation

J-K Flip-Flop _
The Q output is connected back to the input gate G2, and the Q output is
connected back to the input of gate G1. The two control inputs are labeled J and K
in honor of Jack Kilby, who invented the integrated circuit. A J-K flip-flop can also
be of the negative edge-triggered type, in which case the clock input is inverted.

FIGURE 7-23 A simplified logic diagram for a positive edge-triggered J-K flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Let assume that the flip-flop in Figure is RESET and that J input is HIGH and K
input is LOW rather than as shown.
_
1.J is HIGH and Q is HIGH. Flip-Flop is now SET.
2. If you make J LOW and K HIGH, Flip-Flop is now RESET state.
3. Both the J and K are LOW, J and K results in a no-change condition. J and K
inputs are HIGH, then the flip-flop is now SET (toggle).

FIGURE 7-24 Transitions illustrating flip-flop operation.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Asynchronous Preset and Clear Inputs

Most integrated circuit flip-flops also have

asynchronous inputs. These are inputs that
affect the state of the flip-flop independent
of the clock. They are normally labeled
preset (PRE) and clear (CLR), or direct set
(SD) and direct reset (RD) by some
manufacturers.

FIGURE 7-25 Logic symbol for a D flip-flop with active-LOW preset and
clear inputs.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 7-26 Logic diagram for a basic D flip-flop with active-LOW preset
and clear inputs.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

For the positive edge-triggered D flip-flop with preset and clear

inputs in Figure, determine the Q output for the inputs shown in
the timing diagram in part (a) if Q is initially LOW.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 7-28 The 74HC74 dual positive edge-triggered D flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 7-29 The 74HC112 dual negative edge-triggered J-K flip-flop.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
___ ___
The 1J, 1K, 1CLK, 1PRE, and 1CLR waveforms in Figure are applied to one of the
negative edge-triggered flip-flops in a 74HC112 package. Determine the 1Q output
waveform.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
7.3 Flip-Flop Operating Characteristics
Propagation Delay Time:

The propagation delay time is the interval of time required after an input signal
has been applied for the resulting output change to occur.
Four categories of propagation delay times are important in the operation of a
flip-flop:
1. Propagation delay tPLH as measured from triggering edge of the clock pulse to
the LOW-to-HIGH transition of the output. This delay is illustrated in Figure-a.

2. Propagation delay tPHL as measured from the triggering edge of the clock pulse
to the HIGH-to-LOW transition of the output. This delay is illustrated in Figure-b.

FIGURE 7-31 Propagation delays, clock to output.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Propagation Delay Time:

3. Propagation delay tPLH as measured from the leading edge of the preset input
to the LOW-to-HIGH transition of the output. This delay is illustrated in Figure-a.

4. Propagation delay tPHL as measured from the leading edge of the clear input to
the HIGH-to-LOW transition of the output. This delay is illustrated in Figure-b.

FIGURE 7-32 Propagation delays, preset input to output and clear input to
output.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Set-up Time:

The set-up time (ts) is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K or D) prior to the triggering edge of
the clock pulse in order to the levels to be reliably clocked in to the flip-flop.

FIGURE 7-33 Set-up time (ts). The logic level must be present on the D
input for a time equal to or greater than ts before the triggering edge of the
clock pulse for reliable data entry.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Hold Time:

The hold time (th) is the minimum interval required for the logic levels to remain
on the inputs after triggering edge of the clock pulse in order for the levels to be
reliably clocked into the flip-flop.

FIGURE 7-34 Hold time (th). The logic level must remain on the D input for
a time equal to or greater than th after the triggering edge of the clock pulse
for reliable data entry.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Power Dissipation:

The power dissipation of any digital circuit is the total power consumption of the
device. For example, if the flip-flop operates on a +5 V DC source and draws 5
mA of current, the power dissipation is,

P = VCC x ICC = 5 V x 5 mA = 25 mW

The power dissipation is very important in most applications in which the capacity
of the DC supply is a concern. As an example, let’s assume that you have a
digital system that requires a total of ten flip-flops, and each flip-flop dissipates
25 mW of power. The total power requirement is

PT = 10 x 25mW = 250 mW = 0.25 mW

This tells you the output capacity required of the DC supply. If the flip-flops
operate on +5 V DC, then the amount of current that the supply must provide is

I=250 mW / 5 V = 50 mA

You must use a +5 V DC supply that is capable of providing at least 50 mA of

current.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 TABLE 7–4 Comparison of operating parameters for
four IC families of flip-flops of the same type at 25°C.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
7.4 Flip-Flop Applications

Parallel Data Storage

Each of the four parallel data lines

is connected to the D input of a
flip-flop. The clock inputs of the
flip-flops are connected together,
so that each flip-flop is triggered
by the same clock pulse. In this
example, positive edge-triggered
flip-flops are used, so the data on
D inputs are stored simultaneously
by the flip-flops on the positive
edge of the clock, as indicated in
the timing diagram in Figure-b.
Also, the asynchronous rest (R)
inputs
___ are connected to a common
CLR line, which initially resets all
the flip-flops.

FIGURE 7-35 Example of flip-flops used in a basic register for parallel data
storage.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Frequency Division

When a pulse waveform is_ applied to the clock input a D or J-K flip-flop that is
connected to toggle (D=Q or J = K = 1), the Q output is a square wave with
one-half the frequency of the clock input. Thus, a single flip-flop can be applied
as a divide-by-2 device as shown in Figure-a and –b.
As you can see in part (c), the flip-flop changes state on each triggering clock
edge (positive-edge triggered in this case) This results in an output that changes
at half the frequency of the clock waveform.

FIGURE 7-36 The D flip-flop and J-K flip-flop as a divide-by-2 device. Q is

one-half the frequency of CLK.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Further division of a clock
frequency can be achieved
by using the output of one
flip-flop as the clock input to
a second flip-flop, as shown
in Figure. The frequency of
the QA output is divided by
2 by flip-flop B. The QB
output is, therefore, one-
fourth the frequency of the
original clock input.
Propagation delay times are
not shown on the timing
diagrams.

FIGURE 7-37 Example of two D flip-flops used to divide the clock frequency
by 4. QA is one-half and QB is one-fourth the frequency of CLK.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Develop the fout waveform

for the circuit in Figure
when 8 kHz square wave
input is applied to the
clock input of flip-flop A.

Solution:
The three flip-flops are connected to divide the input frequency by eight (23=8)
and the QC (fout) waveform is shown in Figure. Since these are positive edge-
triggered flip-flops, the outputs change on the positive-going clock edge. There
is one output pulse for every eight input pulses, so the output frequency is 1
kHz. Waveforms of QA and QB are also shown.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Counting
Negative edge-triggered J-K flip-
flops are used for illustration. Both
flip-flops are initially RESET. Flip-
flop A toggles on the negative-
going transition of each clock
pulse. The Q output of flip-flop A
clocks flip-flop B, so each time QA
and QB waveforms are shown in
Figure.
Prior to clock pulse 1, QA = 0 and
QB = 0; after clock pulse 1, QA =1
and QB = 0; after clock pulse 2, QA
= 0 and QB =1; and after clock
pulse 3, QA =1 and QB =1. If we
take QA as the least significant bit,
a 2-bit sequence is produced as
the flip-flops are clocked. This
binary sequence repeats every
four clock pulses, as shown in the
timing diagram of Figure. Thus,
the flip-flop A are counting in
sequence from 0 to 3 (00, 01, 10, FIGURE 7-40 J-K flip-flops used to generate a
11) and recycling back to 0 to binary count sequence (00, 01, 10, 11). Two
begin the sequence again. repetitions are shown.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Determine the output

waveforms in relation to
the clock for QA, QB, and
QC in the circuit of Figure
and show the binary
sequence represented by
these waveforms.
Solution:

Notice that the outputs change on the negative-going on edge of the clock pulses.
The outputs go through the binary sequence 000, 001, 010, 011, 100, 101, 110,
and 111 as indicated.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
If the waveforms in Figure are applied to an active-LOW S-R latch, draw the
resulting Q output waveform in relation to the inputs. Assume that Q starts
LOW.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
Solve the pervious problem for the input waveform shown in Figure.

Solution: S R Q Q’
1 1 IC IC
1 0 1 0
0 1 0 1
0 0 NC NC

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Example:
Solve the previous problem for the input waveform shown in Figure (active-
LOW).

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example: _
For a gated S-R latch, determine the Q and Q outputs for the inputs in Figure.
Shown them in proper relation to the enable input. Assume that Q starts
LOW.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
Determine the output of a gated D latch for the inputs in Figure.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Determine the output of a gated D latch for the inputs in Figure.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

For a gated D latch, the waveforms shown in figure are observed on its
inputs. Draw the timing diagram showing the output waveform you would
expect to see at Q if the latch is initially RESET.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Two edge-triggered J-K flip-flops are shown in Figure. If the inputs are as
shown, draw the Q output of each flip-flop relative to the clock, and explain
the difference between the two. The flip-flops are initially RESET.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

The Q output of an edge-triggered D flip-flop is shown in relation to the clock

signal in Figure. Determine the input waveform on the D input that is required
to produce this output if the flip-flop is a positive edge-triggered type.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Draw the Q output relative to the clock for a D flip-flop with the inputs as
shown in Figure. Assume positive edge-triggering and Q initially LOW.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Solve the previous problem for the inputs in Figure.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

For a positive edge-triggered D flip-flop with the input as shown in Figure,

determine the Q output relative to the clock. Assume that Q starts LOW.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:

Solve the previous problem for the input shown in Figure.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
Determine the Q waveform relative to the clock if the signals shown in figure
are applied to the inputs of the J-K flip-flop. Assume that Q is initially LOW.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
For a negative edge-triggered J-K flip-flop with the inputs in Figure, develop
the Q output waveform relative to the clock. Assume that Q is initially LOW.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
For a negative edge-triggered J-K flip-flop
with the inputs in Figure, develop the Q
output waveform relative to the clock.
Assume that Q is initially LOW.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
__
Solve the previous problem with the same J and K inputs with the PRE and
__
CLR inputs as shown in Figure in relation to the clock.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
The flip-flop in Figure is initially RESET. Show the relation between Q output
and the clock pulse if the propagation delay tPLH (clock to Q) is 5 ns.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
For the circuit in Figure, determine the maximum frequency of the clock
signal for reliable operation if the set-up time for each flip-flop is 3 ns and the
propagation delays (tPLH and tPHL) from clock to output are 6 ns for each flip-
flop.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
A D flip-flop is connected as shown in Figure. Determine the Q output in
relation to the clock. What specific function does this device perform?

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Self-Test Answers 1-a 2-c 3-d 4-b 5-d 6-d 7-a 8-b 9-d 10-d 11-c 12-f

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved