Digital Fundamentals

ELEVENTH EDITION
GLOBAL EDITION

CHAPTER 3
Logic Gates

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The Inverter
The inverter (NOT circuit) performs the operation called inversion or
complementation.

FIGURE 3-1 Standard logic symbols for the inverter (ANSI/IEEE Std. 91-
1984/Std. 91a-1991).

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Truth Table
When a HIGH level is applied to an inverter input, a LOW level will appear on
its output. When a LOW level is applied to its input, a HIGH will appear on its
output. This operation is summarized in Table 3-1, which shows the output for
each possible input in terms of levels and corresponding bits. A table such as
this is called Truth Table.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Inverter Operation
When the input is LOW, the output is HIGH; when the input is HIGH, the
output is LOW, thereby producing an inverted output pulse.

FIGURE 3-2 Inverter operation with a pulse input.

FIGURE 3-3 Timing diagram for the case in Figure 3–2.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

FIGURE 3-5

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Logic Expression for an Inverter
Letter near the beginning of the alphabet usually designate inputs, while
letters near the end of the alphabet usually designate outputs. The
complement of a variable is designated by a bar over the letter.

The operation of an inverter (NOT circuit) can be expressed as follows: If the

input variable is called A and the output is called X, then

FIGURE 3-6 The inverter complements an input variable.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
An Application

How can we realized 1’s complement operation by using Gates?

FIGURE 3-7 Example of a 1’s complement circuit using inverters.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The AND Gate

The AND gate is composed of two or more inputs and a signal output, as
indicated by the standard logic symbols shown in Figure 3-8.

FIGURE 3-8 Standard logic symbols for the AND gate showing two inputs
(ANSI/IEEE Std. 91-1984/Std. 91a-1991).

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Operation of an AND Gate
An AND Gate produces a HIGH output only when all of the inputs are HIGH.
When any of inputs is LOW, the output is LOW. Therefore, the basic purpose
of an AND gate is to determine when certain conditions are simultaneously
true, as indicated by HIGH levels on all of its inputs, and to produce a HIGH
on its output to indicate that all these conditions are true.

For a 2-input AND gate, output X is HIGH only when inputs A and B are HIGH;
X is LOW when either A or B is LOW, or when both A and B are LOW.

FIGURE 3-9 All possible logic levels for a 2-input AND gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 AND Gate Truth Table
The total number of possible combinations of binary inputs to a gate is
determined by the following formula:

N=2n
where N is the number of possible input combinations and n is the number of
input variables.

TABLE 3–2 Truth table for a 2-input TABLE 3–2 Truth table for a 3-input
AND gate. AND gate.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
AND Gate Operation with Waveform Inputs

FIGURE 3-10 Example of AND gate operation with a timing diagram

showing input and output relationships.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-11 And Gate Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-12 And Gate Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-13 And Gate Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Logic Expressions for an AND Gate
The logical AND function of two variables is represented mathematically either by
placing a dot between two variables, as A · B, or by simply writing the adjacent
letters without the dot, as AB.

FIGURE 3-15 Boolean expressions for AND gates with two, three, and four inputs.

TABLE 3–4 Truth Table

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Applications
The AND Gate as an Enable/Inhibit Device
A common application of the AND gate is to enable (that is, to allow) the
passage of a signal (pulse waveform) from one point to another at certain times
and to inhibit (prevent) the passages at the other times.
During the 1 millisecond (1 ms) interval of the enable pulse, pulses in waveform
A pass through the AND gate to the counter. The number of pulses passing
through during the 1 ms interval is equal to the frequency of waveform A. For
example, Figure 3-16 shows six pulses in one millisecond, which is a frequency
of 6 KHz. If 1000 pulses pass through the gate in the 1 ms interval of the enable
pulse, there are 100 pulse/ms, or a frequency of 1 MHz.

FIGURE 3-16 An AND gate performing an enable/inhibit function for a

frequency counter.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Applications
A Seat Belt Alarm System

If the ignition switch is on, a HIGH is produced on input A of the AND gate. If the
seat belt is not properly buckled, a HIGH is produced on input B of the AND gate.
Also, when the ignition switch is turned on, a timer is started that produces a
HIGH on input C for 30 s. If all three conditions exist –that is, if the ignition is
on and the seat belt is unbuckled and the timer is running- the output of the
AND gate is HIGH, and an audible alarm is energized to remind the driver.

FIGURE 3-17 A simple seat belt alarm circuit using an AND gate.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The OR Gate

The OR gate produces a HIGH on the output when any of the inputs is HIGH.

For a 2-input OR gate, output X is HIGH when either input A or input B is

HIGH, or when both A and B are HIGH; X is LOW only when both A and B are
LOW.

FIGURE 3-18 Standard logic symbols for the OR gate showing two inputs
(ANSI/IEEE Std. 91-1984/Std. 91a-1991).

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Operation of an OR Gate

FIGURE 3-19 All possible logic levels for a 2-input OR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
OR Gate Operation with Waveform Inputs

FIGURE 3-20 Example of OR gate operation with a timing diagram showing

input and output time relationships.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Logic Expressions for an OR Gate
The logical OR function of two variables is represented mathematically by a +
between the two variables, for example, A+B. The plus sign is read as «OR»

FIGURE 3-24 Boolean expressions

for OR gates with two, three, and four
inputs.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
OR Gate Applications
That system could be used for one room in a home – a room with two Windows
and a door. The sensors are magnetic switches that produce a HIGH output when
open and a LOW output when closed. As long as the windows and door are
secured, the switches are closed and all three of the OR gate inputs are LOW.
When one of the windows or the door is opened, a HIGH is produced on that
input to the OR gate and the gate output goes HIGH.

FIGURE 3-25 A simplified intrusion detection system using an OR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The NAND Gate
The NAND gate is a popular logic element because it can be used as a
universal gate; that is, NAND Gates can be used in combination to perform
the And, OR and INVERTER operations.
The term NAND is a contraction of NOT-AND and implies an AND function
with a complemented (inverted) output.
The symbol Ξ means equivalent to.

FIGURE 3-26 Standard NAND gate logic symbols (ANSI/IEEE Std. 91-
1984/Std. 91a-1991).

FIGURE 3-30 ANSI/IEEE standard symbols representing the two equivalent

operations of a NAND gate.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Operation of a NAND Gate

For a 2-input NAND gate, OUTPUT X is LOW only

when inputs A and B are HIGH; X is HIGH when
either A or B is LOW, or when both A and B are LOW.

FIGURE 3-27 Operation of a 2-input NAND gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
NAND Gate Applications
Two tanks store certain liquid chemicals that are required in a manufacturing
process. Each tank has a sensor that detects when the chemical level drops to
25% of full. The sensors produce a HIGH level of 5 V when the tanks are more
than one-quarter full. When the volume of chemical in a tank drops to one-
quarter full, the sensor puts out a LOW level of 0 V.

Show how a NAND gate can be used to implement this function.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Logic Expressions for an NAND Gate
The Boolean expression for the output of a 2-input NAND gate is

X = AB

This expression says that the two input variables, A and B, are first ANDed and
then complemented, as indicated by the bar over the AND expression.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The NOR Gate
The NOR gate, like the NAND gate, is a useful logic element because it can
also be used as a universal gate; that is NOR Gates can be used in
combination to perform the AND, OR, and inverter operations.

FIGURE 3-34 Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984/
Std. 91a-1991).

FIGURE 3-38 Standard symbols representing the two equivalent operations

of a NOR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Operation of a NOR Gate

A NOR gate produces a LOW output when any of its

HIGH. Only when all of its inputs are LOW is the
output HIGH.
For a 2-input NOR gate, output X is LOW when
either input A or input B is HIGH, or when both A
and B are HIGH; X is HIGH only when both A and B
are LOW.

FIGURE 3-35 Operation of a 2-input NOR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
NOR Gate Application
As part of an aircraft’s functional monitoring system, a circuit is required to
indicate the status of the landing gears prior to landing. A green LED display
turns on if all three gears are properly extended when the «gear down»
switch has been activated in preparation for landing. A red LED display turns
on if any of the gears fail to extend properly prior to landing. When a
landing gear is extended, its sensor produces a LOW voltage. When a landing
gear is retracted, its sensor produces a HIGH voltage. Implement a circuit to
meet this requirement.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Logic Expressions for an NOR Gate
The Boolean expression for the output of a 2-input NOR gate is

X = A+B

This equation says that the two input variables are first ORed and then
complemented, as indicated by the bar over the OR expression.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The Exclusive-OR Gate
The XOR gate has only two inputs. The exclusive-OR gate performs modulo-2
addition. The output of an exclusive-OR gate is HIGH only when the two
inputs are at opposite logic level.

FIGURE 3-42 Standard logic symbols for the exclusive-OR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-43 All possible logic levels for an exclusive-OR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Exclusive-OR Gate Application

 A certain system contains two identical circuit operating in parallel. As

long as both are operating properly, the outputs of both circuits are
always the same. If one of the circuits fails, the outputs will be at opposite
levels at some time. Devise a way to monitor and detect that a failure has
occurred in one of the circuits.

 A failure in either one of circuits produces differing outputs which cause of

the XOR gate, indicating a failure in one of the circuits.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Exclusive-OR Gate Application-2

 The XOR gate can be used a two-bit modulo-2 adder. The basic rules for binary
addition are as follows: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10. An
examination of the truth table for an XOR gate shows that its output is the
binary sum of the two input bits. In the case where the inputs are both 1s, the
output is to sum 0, but you lose the carry of 1.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
The Exclusive-NOR Gate
When the two inputs logic levels are opposite, the output of the exclusive-NOR
Gate is LOW. The operation can be stated as follows:

For an exclusive-NOR gate, output X is LOW when input A is LOW and input B
is HIGH, or when A is HIGH and B is LOW; X is HIGH when A and B are both
HIGH or both LOW.

FIGURE 3-45 Standard logic symbols for the exclusive-NOR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-46 All possible logic levels
for an exclusive-NOR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Programmable Logic Device (PLD)
 Most types of PLDs use some form of AND Array. Basically, this array consists
of AND Gates and a matrix of interconnections with a programmable link at each
cross point, as shown in Figure 3-49(a). Programmable links allow a connection
between a row line and a column line in the interconnection matrix to be opened
or left intact. For each input to an AND gate, only one programmable link is left
intact in order to connect the desired variable to the gate input. Figure 3.49(b)
illustrates an array after it has been programmed.

FIGURE 3-49 Concept of a programmable AND array.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example:
Show the AND array in Figure 3-49(a) programmed for the following outputs:

X1=AB, X2=AB, X3=AB

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Fuse Technology

The Fuse is a metal link that connects a row and a column in the
interconnection matrix. Before programming, there is a fused connection at each
intersection. To program a device, the selected fuses are opened by passing a
current through them sufficient to «blow» the fuse and break the connection. To
intact fuses remain and provide a connection between the rows and columns.
Programmable logic devices that use fuse technology are one-time
programmable (OTP)

FIGURE 3-51 The programmable fuse link.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Fuse Technology

 An antifuse programmable link is the opposite of a fuse link. Instead of

breaking the connection, a connection is made during programming. An antifuse
starts out as an open circuit whereas the fuse starts out as a short circuit. Before
programming, there are no connections between the rows and columns in the
interconnection matrix.
 An antifuse is basically two conductors separated by an insulator. To program
a device with antifuse technology, a programmer tool applies a sufficient voltage
across selected antifuses to break down the insulation between two conductive
materials, causing the insulator to become a low-resistance link. The antifuse
devise is also a one-time programmable (OTP) device.

FIGURE 3-52 The programmable antifuse link.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
EPROM (Electrically Programmable ROM) Technology

This type of PLD is programmed using a special tool known as a device

programmer. The device is inserted in to the programmer, which is connected to
a computer running programming software. EEPROM (E2PROM) can be erased
and reprogrammed electrically.

FIGURE 3-53 A simple AND array with EPROM technology. Only one gate in
the array is shown for simplicity.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
SRAM (Static RAM) Technology

A SRAM-type memory cell is used to turn a transistor on or off to connect or

disconnect rows and columns. A SRAM cell doesn’t retain data when power is
turned off but fuse, antifuse, EPROM, EEPROM and flash process
technologies are nonvolatile.

FIGURE 3-54 Concept of an AND array with SRAM technology.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Device Programming

Although device programmer can be used for this type of device, it is generally
programmed initially on a PLD development board.

FIGURE 3-55 Programming setup for reprogrammable logic devices.

(Photo courtesy of Digilent, Inc.)
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Fixed-Function Logic Gates

74 Series Logic Gate Functions

The 74 series is the standard fixed-function logic devices.

74xxyy
Type of IC technology Type of Logic
family (HC or LS) Function

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
AND GATE

FIGURE 3-59 74 series AND gate devices with pin numbers.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
NAND GATE

FIGURE 3-60 74 series NAND gate devices with package pin numbers.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
OR GATE

FIGURE 3-61 74 series OR gate device.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
NOR GATE

FIGURE 3-62 74 series NOR gate devices.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
XOR GATE

FIGURE 3-63 74 series XOR gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 IC PACKAGES

FIGURE 3-64 Typical dual in-line (DIP) and small-outline (SOIC) packages
showing pin numbers and basic dimensions.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 TABLE 3–14 74 series logic families based on circuit
technology.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-65 CMOS logic. Partial data sheet for a 54/74HC00A quad 2-
input NAND gate. The 54 prefix indicates military grade and the 74 prefix
indicates commercial grade.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-65 (continued) CMOS logic. Partial data sheet for a 54/74HC00A
quad 2-input NAND gate. The 54 prefix indicates military grade and the 74
prefix indicates commercial grade.
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
FIGURE 3-66 Bipolar logic. Partial data sheet for a 54/74LS00 quad 2-input
NAND gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Performance Characteristics and Parameters

1. Propagation Delay Time

PDT, tp, of a logic gate is the time interval between the transition of an input
pulse and occurrence of the resulting transition of the output pulse. There are
two different measurements of propagation delay time associated with a logic
gate that apply to all the types of basic Gates:
• tPHL: The time between a specified reference point on the input pulse and a
corresponding reference point on the resulting output pulse, with the
output changing from HIGH level to the LOW level (HL).
• tPLH: The time between a specified reference point on the input pulse and a
corresponding reference point on the resulting output pulse, with the
output changing from the LOW level to the HIGH level (LH).

Example:

The delays are measured between the

50% points of the corresponding
edges of the input and output pulses.
The values of tPHL and tPLH are not
necessarily equal but in many cases
they are the same.

tPLH
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Performance Characteristics and Parameters

2. DC Supply Voltage

The typical DC supply voltage for CMOS logic is either 5 V, 3.3 V, 2.5 V or 1.8
V depending on the category. The 5 V CMOS can tolerate supply variations
from 2 V to 6 V and still operate properly although propagation delay time
and power dissipation are significantly affected.

3. Power Dissipation

The PD of a logic gate is the product of the DC supply voltage and the average
supply current. Normally, the supply current when the gate output is LOW
greater than when the gate output is HIGH. The manufacturer’s datasheet
usually designates the supply current for the LOW output state as ICCL and
for the HIGH state ICCH.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
4. Input and Output Logic Levels

VIL is the LOW level input voltage for a logic gate, and VIH is the HIGH level
input voltage. The 5 V CMOS accepts a maximum voltage of 1.5 V as VIL and
a minimum voltage of 2 V as VIH.

5. Speed Power Product

This parameter can be used as a measure of the performance of a logic circuit

taking into account the propagation delay time and power dissipation.

SPP = tPPD
Example

A certain gate has a propagation delay of 5 ns and ICCH= 1 mA and ICCL =2.5
mA with a DC supply voltage of 5 V. Determine the speed-power product.

Solution:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
6. Fan-Out and Loading

The fan-out of a logic gate is the maximum number of inputs of the same
series in an IC family that can be connected to a gate’s output and still
maintain the output voltage levels within specified limits.
• Fan-out is specified in terms of unit loads. A unit load for a logic gate
equals one input to a like circuit. For example, a unit load for a 74LS00
NAND gate equals one input to another logic gate in the 74LS family.
• Because the current from a LOW input (IIL) of a 74LS00 gate is 0.4 mA
and the current that a LOW output (IOL) can accept is 8.0 mA, the number
of unit loads that a 74LS00 gate can drive in the LOW state is

FIGURE 3-68 The LS family NAND gate

output fans out to a maximum of 20 LS
family gate inputs.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Troubleshooting

FIGURE 3-69 The effect of an open input on a NAND gate.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example-cont.

There is a problem!!! What

should we do to fix it?

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Summary

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -1: Draw output waveform across each inverter in proper relation
to the input.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -2: If a LOW is applied to point A, determine the net output at points
E and F.

Answer:
B=1, C=0, D=1, E=0, F=1
Output at E=0 and F=1

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -3: Determine the output, X, for a 2-input AND gate with the input
waveforms shown in Figure.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -4: The signal are applied to points A and B of 2-input AND gate
followed by inverter. Draw the output waveform.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -5: The input waveforms applied to a 3-input AND gate are as
indicated in Figure. Show the output waveform in proper relation to the inputs
with a timing diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -5: The input waveforms applied to a 4-input AND gate are as
indicated in Figure. The output of the AND gate is fed to inverter. Draw the
net output waveform of this system.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -6: For the waveforms given in Figure, A and B are ANDed with
output F; D and E are ANDed with output G; and C, F, G are ORed. Draw the
net output waveform.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -7: Determine the output for the gate shown and draw the timing
diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -8: Determine the gate output for the input waveforms in Figure
and draw the timing diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -9: Determine the output waveform in Figure.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -10: Two logic symbols represent equivalent operations. Draw the
timing diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -11: Determine the output waveform and draw the timing diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -12: Determine the output waveform and draw the timing diagram.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -13: Determine the boolean output expressions.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -14:

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -15: Determine tPLH and tPHL from the oscilloscope display.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -16: Identify the faulty gates.

(a) NAND gate OK

(b) AND gate faulty
(c) NAND gate faulty
(d) NOR gate OK
(e) XOR gate faulty
(f) XOR gate OK

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Example -17: Determine the faulty gates in Figure by analyzing the timing
diagram.

(a) NAND gate faulty. Input A open

(b) NOR gate faulty. Input B shorted to ground.
(c) NADN gate OK
(d) XOR gate faulty. Input A open.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Self-Test Answers
1-d
2-d
3-a
4-e
5-c
6-a
7-d
8-b
9-d
10-b
11-d
12-c
13-b
14-a
15-d
16-c
17-c

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved