Scribd
Upload
4 views2 pages

Tutorial 6b

The document outlines a tutorial for a computer systems and organization course, featuring various design tasks related to digital circuits. It includes exercises on decoders, multiplexers, encoders, and truth tables, with specific input conditions and expected outputs. The tutorial emphasizes the construction and simplification of circuits using logic gates and multiplexers.

Uploaded by

fachrirazali03
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
4 views2 pages

Tutorial 6b

The document outlines a tutorial for a computer systems and organization course, featuring various design tasks related to digital circuits. It includes exercises on decoders, multiplexers, encoders, and truth tables, with specific input conditions and expected outputs. The tutorial emphasizes the construction and simplification of circuits using logic gates and multiplexers.

Uploaded by

fachrirazali03
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

WIX1003/WXES1109 – COMPUTER SYSTEMS & ORGANIZATION

SEMESTER 1, SESSION 2016/2017

TUTORIAL 6b

1. Design a 3:8 decoder using two 2:4 decoders (with 1 enable)

2. Design a 4:16 decoder using 3:8 decoders (with 1 enable).

3. Build 4:1 multiplexer using only 2:1 multiplexer (with enable pin).

4. Build 8:1 multiplexer using only 2:1 multiplexer (with enable pin).

5. Build 16:1 multiplexer using only 8:1 74LS151 multiplexer.

6. Draw the output waveform of a 4 x 1 multiplexer if the selector input and


data input is as below.

DO 0 1 1 0 1 0 1 1
D1 1 0 1 1 1 1 0 1
D2 1 1 1 1 0 1 0 1
D3 1 0 1 1 1 1 0 1
S0 1 1 0 1 1 1 0 1
S1 1 0 1 1 0 1 0 1

7. Build a simplified circuit with three inputs A, B, C, and two outputs Y, Z.


The output is obtained by adding all the inputs. For example, if A, B, C is
(011)2 the output Y, Z will become (10)2. However for input with all ‘1’, the
output will be in don’t care condition. The answer should show
a. Truth table
b. K-map with simplified equation
c. Simplified circuit (Please use original input (i.e. no repetition is
allowed))
d. Change the circuit into nand gate only and draw the circuit.
8. A 4-to-2 priority encoder has inputs D3 (highest) to D0. The VALID output
V = 1 when any input is HIGH.

The signals feeding the encoder are defined as:

D3 = A'B + C
D2 = AC' + B'
D1 = A + BC'
D0 = A'BC + C'

(a) Evaluate D3, D2, D1, D0 when A=1, B=0, C=1.


(b) Determine the encoder output Y1Y0.
(c) Determine VALID bit V.

9. A 3-to-8 decoder has active-HIGH outputs Y0 to Y7.


The inputs are connected as follows:

A2 = X
A1 = Y + Z'
A0 = XY' + Z

Given X=1, Y=0, Z=1,


(a) Determine A2, A1, A0.
(b) Identify which decoder output Yi becomes active.

10. Implement F(A,B,C) = A'C + AB + B'C using a 4-to-1 MUX. Select lines:
S1 = B, S0 = C.

(a) Construct a truth table for (B,C) and find F for each pair.
(b) Determine D0–D3 values.
(c) Draw the MUX circuit

11. 1-to-8 DEMUX with D = X + YZ', selects S2=A, S1=B', S0=C.


Given A=0, B=1, C=0, X=1, Y=0, Z=1,
(a) Determine D.
(b) Determine S2S1S0 binary.
(c) Identify which output line Y0..Y7 becomes HIGH.

You might also like