Computer System Architecture

Tutorial 2:
1. A benchmark program is run on an 80 MHz processor. The executed program consists of 100,000
instruction execution, with the following instruction mix and clock cycle count:
Instruction Type Instruction Count Cycle per Instruction

Integer Arithmetic 45000 1

Data Transfer 32000 2

Floating Point 15000 2

Control Transfer 8000 2

CP に r 0s

Determine the effective CPI, MIPS rate, and execution time for this program · MIPS = =51.63
.
% 0.
0010

m--
, 00
T

2. The performance of a 100MHz microprocessor P is measured by executing 10,000,000 instruction of

√
C βに
'crouk benchmark code, which is found to take 0.25s. What are the values of CPI and MIPS for this
performance experiment? Is P likely to be superscalar?
Miperfo surersalaraf
afl
'f 2
5-
-

rint;:
.
"

-
:

.i v e *
3. Suppose that a single-chip microprocessor P operating at clock frequency of 50MHz is replaced by a
new model P’, which has the same architecture as P but has a clock frequency of 75MHz.
superscalar *

a. If P has a performance rating of p MIPS for a particular benchmark program Q, what is the
corresponding MIPS rating p’ for P fal §
b. P takes 250s to execute Q in a particular personal computer system C. On replacing P by P’
in C, the execution time of Q drops only to 220s. Suggest a possible reason for this
disappointing performance improvement. b expected speed 1 5 : .
• Memory bottleneck

→
. • I/O delays
• Cache misses
9 ctral

• Memory bott
:
250 + 220 • Program not CPU-bound

possible reason :

4. Suppose we have two implementations of the same instruction set architecture. Computer A has a
clock cycle time of 250 ps and a CPI of 2.0 for a given benchmark program, and computer B has a • I/O delays
clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for
this program and by how much?
=
is 1 2 faster
A .
• Cache misse
• Program not
5. A compiler designer is deciding between two codes for a particular machine. Based on the hardware
implementation, there are three different classes of instructions: Class A, Class B, and Class C,

.
and they require one, two, and three cycles respectively.
Code 1 :
difference :

First code has 5 instructions: 2 of A, 1 of B, and 2 of C.

灣
"
.

Second code has 6 instructions: 4 of A, 1 of B, and 1 of C. iimie

Which code is faster?

n
code
By how much?

What is the CPI for each code?

 %ไ
、
∞

·
r ー

↓บร
ร

Mrt
·

• Memory bottleneck
• I/O delays
ーた

• Cache misses

• Memory bottleneck
• Program not CPU-bound

• I/O delays
ー
勤

• Cache misses
• Program not CPU-bound