1.

Different types of addressing techniques in computer architecture with examples

Implied addressing mode which has no operand specified in the instruction that is the operand
is specified implicit in defining the instruction. An example of this is the complement
accumulator because the operand in the accumulator register is implied in defining the
instruction and written as:
CMA: Take complement of content of AC
Similarly, the instruction,
RLC: Rotate the content of Accumulator is an implied mode instruction.

Immediate addressing mode whereby the operand is specified in the instruction itself which
means it has an operand field and not and address field. An example is:
MVI 06 Move 06 to the accumulator
ADD 05 ADD 05 to the content of accumulator
Direct addressing mode, also known as absolute addressing mode, has the address of the data or
operand in the instruction. The operand resides in the memory and its address is given directly by
the address field of the instruction. An example of an instruction is:
ADD A ,[0325] Means add contents of cell A to accumulator .
Indirect addressing mode has the address field of instruction gives the memory address where
on, the operand is stored in memory. Indirect mode is of two kind:
 Register Indirect: Effective address is in the register, and corresponding register name
will be maintained in the address field of an instruction.
Here one register reference,one memory reference is required to access the data.
 Memory Indirect: Effective address is in the memory, and corresponding memory address
will be maintained in the address field of an instruction.
For example,
ADD (A) Means adds the content of cell pointed to contents of A to Accumulator.
Register addressing mode, the operands are in registers that reside within the CPU. That is, in
this mode, instruction specifies a register in CPU, which contains the operand. The address refers
to the register. Example:
MOV AL, [BX]
Auto Indexed (increment mode): Effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory location. (R1)+.
Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
R2 = R2 + d
Auto indexed (decrement mode): Effective address of the operand is the contents of a register
specified in the instruction. Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory location. –(R1)
Example:
Add R1,- (R2) //OR
R2 = R2-d
R1 = R1 + M[R2]
Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI
or DI and an 8 bit or 16-bit displacement. Example:
MOV AX, [SI +05]
Based Indexed addressing mode: The operand’s offset is sum of the content of a base register
BX or BP and an index register SI or DI. Example:
ADD AX, [BX+SI]
PC relative addressing mode: PC relative addressing mode is used to implement intra segment
transfer of control. Effective address is obtained by adding displacement to PC.
EA= PC + Address field value
PC= PC + Relative value.
Base register addressing mode: Base register addressing mode is used to implement inter
segment transfer of control. Effective address is obtained by adding base register value to
address field value.
EA= Base register + Address field value.
PC= Base register + Relative value.
1. Role of instruction pipelining in the design of a microprocessor
Pipelining increases the overall instruction throughput where each segment consists of an input
register followed by a combinational circuit. The register is used to hold data and combinational
circuit performs operations on it and the next segment is tackled with this circuit.
The cycle time of the processor is reduced therefore has a high speed of processing data.
It makes the system reliable with the performance improved by fast processing of data.
Through this an ALU can be designed which will be faster.
It increases the overall performance of the CPU due to reliability and fast speed.

2. Evolution of 8086 processor

8086- It was a 16-bit machine and was far more powerful than the previous one, 8085. It had a
wider data path of 16-bits and larger registers along with an instruction cache or queue that
prefetches a few instructions before they are executed. It uses High-speed Metal Oxide
Semiconductor and consists of a powerful instruction set. It is the first appearance of 8086
architecture. It has a real mode and an addressable memory of 1 MB.
80286 – It has an addressable memory of 16 MB instead of just 1 MB and contains two modes-
real mode and first generation 16-bit protected mode. It has a data transfer width of 16-bits and
programming model of 16-bits (16-bits general purpose registers and 16-bit addressing).
80386 – It was Intel’s first 32-bit machine. Due to its 32-bit architecture it was able to compete
against the complexity and power of microcomputers and mainframes introduced just a few
years earlier. It was the first processor to support multitasking and contained the 32-bit protected
mode. It also implemented the concept of paging (permitted 32-bit virtual memory address to be
translated into 32-bit physical memory address). It has an addressable physical memory of 4 GB
and data transfer width of 32-bits.
80486 – It introduced the concept of cache technology and instruction pipelining. It contained
write protect feature and offered a built-in math co-processor that offloaded complex math
operations from the main CPU.
Pentium – The use of superscalar techniques was introduced as multiple instructions started
executing in parallel. The page size extension (PSE) feature was added as a minor enhancement
in paging.
Pentium Pro – It used register renaming, branch prediction, data flow analysis, speculative
execution and more pipeline stages. Advanced optimization techniques in microcode were also
added along with level 2 cache. It implemented the second generation address translation in
which 32-bit virtual address is translated into 36-bit physical memory address.
Pentium II – It was able to process video, audio and graphics data efficiently by incorporating
Intel MMX technology (multimedia data set).
Pentium III – It contains SMD (streaming extensions) instructions (SSE) and supports 3D
graphics software. It has a maximum CPU clock rate of 1.4 GHz and contained 70 new
instructions.
Pentium 4 – It implements third generation address translation that translates 48-bit virtual
memory address to 48-bit physical memory address. It contains other floating point
enhancements for multimedia.
Core – It is the first Intel microprocessor with dual core that is the implementation of 2
processors on a single chip. There is an addition of Visualizing Technology.
Core 2 – It extends the architecture to 64-bits and core 2 Quad provides four processors on a
single chip. The register set as well as addressing modes are of 64-bits.

3. 8086 processor architecture and the instruction set classifications

It is a 16-bit Integer processor in a 40-pin, Dual Inline Packaged IC.
The size of the internal registers present within the chip, indicates how much information the
processor can operate on at a time and how it moves data around internally within the chip,
sometimes also referred to as the internal data bus.
8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide.
The main advantage of the 8086 microprocessor is that it supports Pipelining.
In order to increase execution speed and fetching speed, 8086 segments the memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit
(BIU), and The Execution Unit (EU).
The Bus Interface Unit (BIU): provides the interface of 8086 to external memory and I/O
devices via the System Bus. It performs various machine cycles such as memory read, I/O
read, etc. to transfer data between memory and I/O devices.
BIU performs the following functions as follows:
It generates the 20-bit physical address for memory access, it fetches instructions from the
memory, it transfers data to and from the memory and I/O and maintains the 6-byte pre-fetch
instruction queue (supports pipelining).
BIU contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an
Address Generation Circuit.
The Execution Unit (EU) The main components of the EU are General purpose registers, the
ALU, Special purpose registers, the Instruction Register and Instruction Decoder, and the
Flag/Status Register.
Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
operations using the ALU.
Sends control signals for internal data transfer operations within the microprocessor.(Control
Unit)
Sends request signals to the BIU to access the external module.
It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store
intermediate values during execution. Each of these has two 8-bit parts (higher and lower).
 AX register: (Combination of AL and AH Registers)
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.

 BX register: (Combination of BL and BH Registers)

It holds the memory address (offset address) in indirect addressing modes.

 CX register: (Combination of CL and CH Registers)

It holds the count for instructions like a loop, rotates, shifts and string operations.

 DX register: (Combination of DL and DH Registers)

It is used with AX to hold 32-bit values during multiplication and division.

Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations.
Special purpose registers (16-bit): Special purpose registers are called Offset registers also.
Which points to specific memory locations under each segment.
 Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during
instructions like PUSH, POP, CALL, RET etc.
 Base Pointer: BP can hold the offset addresses of any location in the stack segment.
It is used to access random locations of the stack.
 Source Index: It holds offset address in Data Segment during string operations.
 Destination Index: It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The instruction
decoder decodes it and sends the information to the control circuit for execution.
Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the
microprocessor.
There are 6 Status flags which are: Carry flag(CF), Parity flag(PF), Auxiliary carry
flag(AF),Zero flag(Z), Sign flag(S) and Overflow flag (O)
Status flags are updated after every arithmetic and logic operation and have 3 Control flags:
Trap flag(TF)
Interrupt flag(IF)
Direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI,
etc. The Control flags are used to control certain operations.
Instruction Set - 8086 has instruction (mostly same as in 8085) which are:
1. Data Copy/Transfer instructions e.g.
MOV, Moves data from register to register, register to memory, memory to register, memory to
accumulator, accumulator to memory, etc.
LDS, Loads a word from the specified memory locations into specified register. It also loads a
word from the next two memory locations into DS register.
LES, Loads a word from the specified memory locations into the specified register. It also loads
a word from next two memory locations into ES register.
2. Arithmetic instructions such as
ADD, Adds data to the accumulator i.e. AL or AX register or memory locations.
ADC, Adds specified operands and the carry status (i.e. carry of the previous stage).
SUB, Subtract immediate data from accumulator, memory or register.
3. Logical instructions e.g.
AND, performs bit by bit logical AND operation of two operands and places the result in the
specified destination.
OR, performs bit by bit logical OR operation of two operands and places the result in the
specified destination.
XOR, performs bit by bit logical XOR operation of two operands and places the result in the
specified destination.

4. Shift and rotate instructions e.g.

RCL, Rotate all bits of the operand left by specified number of bits through carry flag.
RCR, Rotate all bits of the operand right by specified number of bits through carry flag.
ROR, Rotate all bits of the operand right by specified number of bits.
SAL or SHL, Shifts each bit of operand left by specified number of bits and put zero in LSB
position.
SAR, Shift each bit of any operand right by specified number of bits. Copy old MSB into new
MSB.
SHR, Shift each bit of operand right by specified number of bits and put zero in MSB position.
5. Branch instructions such as
JA or JNBE, Jump if above, not below, or equal i.e. when CF and ZF = 0
JAE/JNB/JNC, Jump if above, not below, equal or no carry i.e. when CF = 0
JB/JNAE/JC, Jump if below, not above, equal or carry i.e. when CF = 0
JBE/JNA, Jump if below, not above, or equal i.e. when CF and ZF = 1

6. Loop instructions
LOOP, Jump to defined label until CX = 0.
LOOPZ/LOOPE, Decrement CX register and jump if CX ≠ 0 and ZF = 1.
LOOPNZ/LOOPNE, Decrement CX register and jump if CX ≠ 0 and ZF = 0.

7. Flag (Bit) Manipulation instructions

CLC, Clear Carry Flag: This instruction resets the carry flag CF to 0.
CLD, Clear Direction Flag: This instruction resets the direction flag DF to 0.
CLI, Clear Interrupt Flag: This instruction resets the interrupt flag IF to 0.
CMC, This instruction take complement of carry flag CF.
8. String instructions
MOVS/MOVSB/MOVSW, Moves 8-bit or 16-bit data from the memory location(s) addressed
by SI register to the memory location addressed by DI register.
CMPS/CMPSB/CMPSW, Compares the content of memory location addressed by DI register
with the content of memory location addressed by SI register.
SCAS/SCASB/SCASW, Compares the content of accumulator with the content of memory
location addressed by DI register in the extra segment ES.

4. Various applications of microprocessor 8086 in computing

 Useful in the field of instrumentation. Frequency counters, function generators, frequency
synthesizers, spectrum analyses
  Microprocessor based controllers are available in home appliances, such as microwave
oven, washing machines etc., microprocessors are being used in controlling various
parameters like speed, pressure, temperature etc.
 In the telephone industry, these are used in digital telephone sets. Telephone exchanges
and modem etc. The use of microprocessor is also in television, and satellite
communication
 Microprocessors based systems are being used for word processing, spread sheet
operations, and storage.
 It is used in calculators and game machine.
 It is used in accounting systems and data acquisition systems.
 It is used in military applications.
 It is also used in traffic light control
References
Addressing modes. (n.d.). Retrieved October 12, 2022, from
[Link]
Evolution of microprocessors - GeeksforGeeks. (2022). Retrieved 12 October 2022, from
[Link]
Architecture of 8086 - GeeksforGeeks. (2022). Retrieved 12 October 2022, from
[Link]
Instruction Set of 8086 - javatpoint. (2022). Retrieved 12 October 2022, from
[Link]
Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- GeeksforGeeks. (2022). Retrieved 12 October 2022, from
[Link]
execution-stages-and-throughput/
Durani, R. (2020). 8086 [Blog]. Retrieved from [Link]
[Link]