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Hypervisors Structures

The document outlines the structure and components of a Virtual Machine Control Structure (VMCS), detailing the guest and host state areas, control fields, and VM-exit control fields. It includes various registers and their configurations, such as CR0, CR3, and CR4, as well as execution controls and VM-exit information. The document serves as a technical reference for understanding the management of virtual machines within a computing environment.

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0% found this document useful (0 votes)
21 views2 pages

Hypervisors Structures

The document outlines the structure and components of a Virtual Machine Control Structure (VMCS), detailing the guest and host state areas, control fields, and VM-exit control fields. It includes various registers and their configurations, such as CR0, CR3, and CR4, as well as execution controls and VM-exit information. The document serves as a technical reference for understanding the management of virtual machines within a computing environment.

Uploaded by

fabrifioo334
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Virtual Machine Control Structure

GUEST STATE AREA


CR0 CR3 CR4
DR7
RSP RIP RFLAGS
CS Selector Base Address Segment Limit Access Right
SS Selector Base Address Segment Limit Access Right
DS Selector Base Address Segment Limit Access Right
ES Selector Base Address Segment Limit Access Right
FS Selector Base Address Segment Limit Access Right
GS Selector Base Address Segment Limit Access Right
LDTR Selector Base Address Segment Limit Access Right
TR Selector Base Address Segment Limit Access Right
GDTR Selector Base Address Segment Limit Access Right
IDTR Selector Base Address Segment Limit Access Right
IA32_DEBUGCTL IA32_SYSENTER_CS IA32_SYSENTER_ESP IA32_SYSENTER_EIP
IA32_PERF_GLOBAL_CTRL IA32_PAT IA32_EFER IA32_BNDCFGS
SMBASE
Activity state Interruptibility state
Pending debug exceptions
VMCS link pointer
VMX-preemption timer value
Page-directory-pointer-table entries PDPTE0 PDPTE1 PDPTE2 PDPTE3
Guest interrupt status
PML index

HOST STATE AREA


CR0 CR3 CR4
RSP RIP
CS Selector
SS Selector
DS Selector
ES Selector
FS Selector Base Address
GS Selector Base Address
TR Selector Base Address
GDTR Base Address
IDTR Base Address
IA32_SYSENTER_CS IA32_SYSENTER_ESP IA32_SYSENTER_EIP
IA32_PERF_GLOBAL_CTRL IA32_PAT IA32_EFER
CONTROL FIELDS
Pin-Based VM- External-interrupt exiting NMI exiting Virtual NMIs
Execution Controls Activate VMX-preemption timer Process posted interrupts
Interrupt-window exiting Use TSC offsetting
Primary processor- HLT exiting INVLPG exiting MWAIT exiting RDPMC exiting
based RDTSC exiting CR3-load exiting CR3-store exiting CR8-load exiting
VM-execution CR8-store exiting Use TPR shadow NMI-window exiting MOV-DR exiting
controls Unconditional I/O exiting Use I/O bitmaps Monitor trap flag Use MSR bitmaps
MONITOR exiting PAUSE exiting Activate secondary controls
Virtualize APIC accesses Enable EPT Descriptor-table exiting Enable RDTSCP
Virtualize x2APIC mode Enable VPID WBINVD exiting Unrestricted guest
Secondary
APIC-register virtualization Virtual-interrupt delivery PAUSE-loop exiting
processor-based
RDRAND exiting Enable INVPCID Enable VM functions VMCS shadowing
VM-execution
Enable ENCLS exiting RDSEED exiting Enable PML EPT-violation #VE
controls
Conceal VMX non-root operation from Intel PT Enable XSAVES/XRSTORS
Mode-based execute control for EPT Use TSC scaling
Exception Bitmap I/O-Bitmap Addresses TSC-offset
Guest/Host Masks for CR0 Guest/Host Masks for CR4 Read Shadows for CR0 Read Shadows for CR4
CR3-target value 0 CR3-target value 1 CR3-target value 2 CR3-target value 3 CR3-target count
APIC-access address Virtual-APIC address TPR threshold
APIC Virtualization EOI-exit bitmap 0 EOI-exit bitmap 1 EOI-exit bitmap 2 EOI-exit bitmap 3
Posted-interrupt notification vector Posted-interrupt descriptor address
Read bitmap for low MSRs Read bitmap for high MSRs Write bitmap for low MSRs Write bitmap for low MSRs
Executive-VMCS Pointer Extended-Page-Table Pointer Virtual-Processor Identifier
PLE_Gap PLE_Window VM-function controls VMREAD bitmap VMWRITE bitmap
ENCLS-exiting bitmap PML address
Virtualization-exception information address EPTP index XSS-exiting bitmap

VM-EXIT CONTROL FIELDS


Save debug controls Host address space size Load IA32_PERF_GLOBAL_CTRL
VM-Exit Controls Acknowledge interrupt on exit Save IA32_PAT Load IA32_PAT Save IA32_EFER Load IA32_EFER
Save VMX preemption timer value Clear IA32_BNDCFGS Conceal VM exits from Intel PT
VM-Exit Controls VM-exit MSR-store count VM-exit MSR-store address
for MSRs VM-exit MSR-load count VM-exit MSR-load address
VM-EXIT INFORMATION FIELDS
Basic VM-Exit Exit reason Exit qualification
Information Guest-linear address Guest-physical address
VM Exits Due to Vectored Events VM-exit interruption information VM-exit interruption error code
VM Exits That Occur During Event Delivery IDT-vectoring information IDT-vectoring error code
VM-exit instruction length VM-exit instruction information
VM Exits Due to Instruction Execution
I/O RCX I/O RSI I/O RDI I/O RIP
VM-instruction error field

 Natural-Width fields.
 16-bits fields.
 32-bits fields.
 64-bits fields.

CopyLeft 2017, @Noteworthy (Intel Manuel of July 2017)

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