MODULE V – ASSIGNMENT QUESTIONS
Interconnect, I/O Pads, and Layout
VLSIDesign | DigitalIntegratedCircuits
Q. Question Assigned Students (Roll No. | Name)
No.
Topic 1: Layouts of Universal Gates and Design Rules
1. Draw the stick diagram and complete layout of a 2-input NAND gate using CMOS Assigned To:
technology. Label all layers (diffusion, polysilicon, metal) and verify compliance with lambda- BTECH/10152/24 ABHINAV
based design rules as per Mead-Conway guidelines. Also explain why design rules are BTECH/10164/24 NABANJAN DUTTA
stated in terms of lambda (λ) rather than absolute dimensions. BTECH/10253/24 AYUSH JAISWAL
BTECH/10317/24 RUDRAKSH
2. Design a minimum-area CMOS layout for the logic function F = (A + B)(C + D) using Euler Assigned To:
BTECH/10434/24 SIDHANT ANWESHI
path ordering. Draw the stick diagram, derive the optimal transistor ordering for pull-up and BTECH/10438/24 ANIMESH KUMAR
pull-down networks, and compare the area with a naïve layout implementation. BTECH/10454/24 PREKSHA BAID
BTECH/10501/24 PRINCE RAJ
Assigned To:
3. Implement the logic function F = (AB + CD + EF)' using diffusion sharing and transistor
BTECH/10625/24 PARI GAUTAM
reordering. Derive all possible Euler paths and determine which one minimizes diffusion
BTECH/10649/24 RAM GUPTA
breaks. Compare the layout with a standard AOI gate in terms of area efficiency and well BTECH/10668/24 GUNGUN KUMARI
contact placement. BTECH/10671/24 PRITIKA KUMARI
Assigned To:
4. For a 0.18 μm CMOS technology, design the layout of a 3-input NAND gate optimized for BTECH/10672/24 PRATIK TIRKEY
minimum delay instead of minimum area. Determine the optimal transistor widths using BTECH/10677/24 OM KUMAR SINGH
logical effort and estimate the layout area penalty. Explain how design rule violations (e.g., BTECH/10678/24 DIPANSHU AGRAWAL
minimum polysilicon spacing) are detected by DRC tools. BTECH/10679/24 RAHUL SAHU
Topic 2: Interconnect Parameters and Electrical Wire Models
5. A global interconnect of length 4 mm is implemented in a 90 nm CMOS process. Given: Assigned To:
Sheet resistance = 0.05 Ω/□, Wire capacitance = 0.18 fF/μm. Derive the distributed RC delay BTECH/10680/24 PRINCE JANARDAN
expression and compute the delay using the Elmore delay approximation. Show that BTECH/10682/24 HIMANSHU DUBEY
BTECH/10685/24 DEVENDRA HEMBRAM
propagation delay is proportional to L².
BTECH/10686/24 KSHITIZ SINHA
Assigned To:
6. A global clock wire of 5 mm length must meet a skew budget of 50 ps. Given R_sheet = 0.08 BTECH/10691/24 HITESH BAJAJ
Ω/□ and C = 0.2 fF/μm², determine the minimum required wire width and suggest an optimal BTECH/10698/24 SUMIT RATHORE
repeater buffering strategy to meet the constraint. Derive the optimal number and size of BTECH/10701/24 ARPAN MANEK
repeaters. BTECH/10708/24 HIMANSHU GUPTA
Assigned To:
7. A clock distribution network must drive 32 loads arranged in an H-tree structure. Derive the
Elmore delay expression for each branch and estimate the maximum clock skew. Compare BTECH/10712/24 ARYAN RAJ
lumped vs. distributed wire models and identify the frequency at which inductance effects BTECH/10715/24 MOHIT
BTECH/10716/24 MOHAMMAD SHARIB
must be included. SIDDIQUI
BTECH/10717/24 PRIYANSHU SRIVASTAVA
Assigned To:
8. Starting from Maxwell's equations, derive the distributed RLC transmission line model for on-
BTECH/10719/24 AMAN CHANDRA
chip wires. For a high-speed bus operating at 3 GHz, analyze the effects of skin effect, BTECH/10720/24 SADIQUE AHMAD KHAN
inductive ringing, and crosstalk-induced delay variations. BTECH/10721/24 NITIN SINGH
BTECH/10725/24 ADITYA RAJ
Topic 3: Capacitive, Resistive, and Inductive Parasitics
9. Derive a complete capacitance model for two parallel interconnect wires including: (a) Assigned To:
BTECH/10735/24 PAWAN KUMAR RANA
parallel plate capacitance, (b) fringing capacitance, and (c) coupling capacitance. Compare
BTECH/10745/24 AYUSH MARK HEMBROM
the values when using SiO₂ (k = 3.9) and low-k dielectric (k = 2.5) and discuss how low-k BTECH/10746/24 ARNAV SRIVASTAVA
materials reduce parasitic interconnect delay. BTECH/10756/24 SIDDHARTH KUMAR
NAYAK
Assigned To:
10. In a 65 nm process, two parallel wires run for 1 mm with a coupling capacitance of 0.15
BTECH/10767/24 SOURISH CHOUDHARY
fF/μm. A signal wire also runs parallel to an aggressor wire for 500 μm. Calculate the Miller BTECH/10774/24 AYUSH
coupling capacitance and analyze its effect on signal integrity (delay, noise) for both in-phase BTECH/10776/24 PRAKHAR TAMBI
and out-of-phase switching scenarios. BTECH/10794/24 AOZZ BRAHMSHIV JHA
Assigned To:
11. Derive the inductance per unit length of a microstrip wire over a ground plane. At what clock BTECH/10799/24 GARIMA AGARWAL
frequency does inductive impedance become comparable to resistive impedance for a 1 mm BTECH/10805/24 SAMEER KUMAR
Cu wire of 1 μm width? Compute the inductive reactance at 5 GHz using appropriate process BTECH/10814/24 SRIJAN SINHA
parameters. BTECH/10816/24 ARYAMAN PRASAD
Assigned To:
12. Perform parasitic extraction of a 2 mm clock wire using both π-model and T-model and BTECH/10826/24 SAHIL
compare accuracy with the distributed RC model. In a mixed-signal SoC, model the substrate BTECH/10831/24 SUMIT KUMAR DUTTA
as a distributed RC network and estimate the noise voltage reaching an analog block due to BTECH/10834/24 VIVEK KUMAR SAHU
BTECH/10847/24 SAGARNIL BARARI
digital switching. Explain how guard rings and deep n-well structures mitigate this coupling.
Topic 4: I/O Pads and ESD Protection Circuits
13. Design a CMOS output driver capable of driving a 50 Ω transmission line at 1 Gbps. Include Assigned To:
pre-driver stages and slew-rate control. Determine the required transistor sizing, estimate BTECH/10849/24 SMARAN YANAPU
power dissipation, and explain how controlled edge rates reduce EMI and ground bounce. BTECH/10850/24 ANKIT RAJ
BTECH/10859/24 ARYAN PATRO
BTECH/10863/24 AADARSH NINGWAL
Assigned To:
14. During a 2 kV Human Body Model (HBM) ESD event, derive the current waveform and BTECH/10871/24 ABDULLAH SAIF
calculate the peak current and energy dissipated in the protection device. Explain the
operation of a double-diode clamp structure and verify the device can handle the event BTECH/10879/24 SHARWANI MUNDA
without triggering latch-up. BTECH/10887/24 NAMAN GUPTA
BTECH/10888/24 STUTI GARG
15. Compare SCR-based ESD protection circuits with diode-based clamps in terms of: (a) trigger Assigned To:
voltage, (b) holding voltage, (c) area efficiency, and (d) leakage current. Analyze gate- BTECH/10891/24 ANISH KUMAR GUPTA
grounded NMOS (ggNMOS) vs. SCR I-V characteristics and their suitability for nanometer BTECH/10895/24 MICHRAI PURTY
BTECH/10897/24 BHAGYA RAJ
CMOS technologies. BTECH/10899/24 AKRITI AGARWAL
16. Assigned To:
A chip uses 1.2 V core logic and 3.3 V I/O logic. Design a level-shifting circuit that prevents
BTECH/10920/24 SUJEET TANA BHAGAT
oxide breakdown and ensures reliable operation. Explain how transistor stacking prevents BTECH/10938/24 MAYUR SETH
oxide overstress and ensures correct logic translation between voltage domains. BTECH/10939/24 PREETY MURMU
BTECH/10942/24 RAKSHIT POONIA
Topic 5: Bidirectional and Schmitt Trigger in the Input Pad
17. Analyze the latch-up condition in CMOS I/O pads using the parasitic npnp thyristor model. Assigned To:
Describe layout-level and circuit-level techniques — guard rings, well taps, and retrograde BTECH/10949/24 ADITI SHANKAR
wells — used to prevent latch-up triggering during ESD events. BTECH/10955/24 MANISH JALARAM BISNOI
BTECH/10956/24 PALAK CHANDAN
AGARWALA
BTECH/10961/24 ANMOL KACHHAP
Assigned To:
18. Design a bidirectional I/O pad that functions as both input and output depending on an enable
signal. Include bus-hold circuitry with weak feedback to prevent floating nodes. Draw the BTECH/10969/24 PREM RANJAN
BTECH/10977/24 SOURABH KUMAR
complete transistor-level schematic, explain tri-state output control, and discuss how bus
BTECH/10978/24 ADITYA MAHESH
contention is avoided.
BTECH/10982/24 DIVYANSHU KUMAR
Derive the switching thresholds (V_IL, V_IH) of a CMOS Schmitt trigger in terms of transistor Assigned To:
19. BTECH/10989/24 MALOTH SHASANK
sizing ratios. Design a Schmitt trigger for a 3.3 V supply with switching thresholds V_TH+ =
BTECH/10998/24 KHUSHI NARENDRA
2.1 V and V_TH− = 0.9 V. Calculate all transistor dimensions and verify the hysteresis SHUKLA
window using DC transfer curve analysis. BTECH/11001/24 DIVYESH MOHAN
BTECH/11009/24 LAXMI KUMARI