LOW POWER IC DESIGN

ASSIGNMENT TASK-2

WINTER SEMESTER 2025-26

COURSE CODE: MAVLD602
SLOT: D1+TD1

Submitted by
Kalaiselvan.R
25MVD0070
 Study of Transistor Stacking Effect on Leakage Currents in a 3-Input CMOS NAND Gate

Aim:
To analyse the effect of transistor stacking on leakage and conduction currents in a static CMOS logic gate by
studying a 3-input static CMOS NAND gate. The experiment aims to evaluate how different input combinations
(000 to 111) influence:

• Subthreshold leakage current in stacked NMOS transistors

• Drain current of the bottom (last) NMOS transistor in the pull-down stack
• Gate leakage currents of individual NMOS devices
• Source current drawn from VDD (static power consumption)

This analysis helps in understanding the stacking effect and its role in reducing leakage current and static power
dissipation in deep submicron CMOS technologies.

Tools Required:
Cadence Virtuoso.

Circuit Description
The circuit under study is a 3-input static CMOS NAND gate implemented using complementary pull-up and pull-
down networks.
Objective of the Configuration
• The series stacking of NMOS transistors creates different conduction and leakage paths depending on the
input vector.
• For input combinations where one or more NMOS transistors are OFF, the stacking effect reduces the
subthreshold leakage current due to:
o Reduced 𝑉𝐷𝑆
o Increased effective threshold voltage
o Body effect and intermediate node voltage rise

Figure1. schematic of 3 input Static CMOS NAND gate

Procedure:
1. Library Setup
Create a new library in Cadence Virtuoso and attach it to the GPDK 90 nm technology.

2. Schematic Design
Draw a 3-input static CMOS NAND gate using gpdk90 NMOS and PMOS devices.
Connect three PMOS transistors in parallel (pull-up network) and three NMOS transistors in series (pull-down
stack).

3. Transistor Sizing
All transistors were sized uniformly with:
NMOS width = 360 nm , PMOS width = 415 nm & Channel length = 180 nm
This sizing ensures balanced operation while enabling clear observation of stacking effects in the NMOS
pull-down network.

4. Power Supply and Inputs

Apply VDD (1 V) and ground.
Provide DC input voltages for A, B, and C to generate all input combinations from 000 to 111.

5. Simulation Setup
Open ADE, select DC operating point analysis, and enable saving of device operating point parameters and
currents.

6. Current Measurement
Measure gate leakage currents of NMOS transistors, drain current of the bottom NMOS in the stack, and
source current drawn from VDD for each input vector.

7. Result Recording
Apply input combinations sequentially:
000, 001, 010, 011, 100, 101, 110, 111
Record all currents for each vector & tabulate the results for comparison

Simulation Parameters:

Parameter Value
Gate 3-input Static CMOS NAND Gate

Supply Voltage (VDD) 1.0 V

Load Capacitance (CL) 1pf
Analysis Type Transient Analysis & dc Analysis

Table1: simulation setup

Observations:

Figure 3: Device current observations for input combination 000 in a 3-input CMOS NAND gate.

Figure 4: Device current observations for input combination 001 in a 3-input CMOS NAND gate.
Figure 5: Device current observations for input combination 010 in a 3-input CMOS NAND gate.

Figure 6: Device current observations for input combination 011 in a 3-input CMOS NAND gate.
Figure 7: Device current observations for input combination 100 in a 3-input CMOS NAND gate.

Figure 8: Device current observations for input combination 101 in a 3-input CMOS NAND gate.
Figure 9: Device current observations for input combination 110 in a 3-input CMOS NAND gate.

Figure 10: Device current observations for input combination 111 in a 3-input CMOS NAND gate.
Consolidated Observation Table

Input NMOS Gate NMOS Gate NMOS Gate Drain Current of Source Current
Vector Current (Top) Current (Mid) Current (Bottom) Bottom NMOS from VDD
000 −203 aA −4.79 fA −609 fA 0.79 pA −1.88 nA
001 809 pA −1.32 fA −606 fA 1.57 nA −2.30 nA
010 −1.89 fA 462 pA −607 fA 1.63 nA −1.90 nA

011 809 pA 809 pA −605 fA 35.81 nA −35.37 nA

100 −1.54 fA −519 fA 24.36 fA 1.52 nA −2.24 nA
101 809 pA −431 fA 277 fA 20.72 nA −21.08 nA

110 −401 fA 759 fA 259 fA 18.84 nA −19.20 nA

111 809 pA 809 pA 809 pA 2.69 nA −1.07 nA

Table2 : 3-Input CMOS NAND Gate (GPDK 90 nm)

(NMOS W = 360 nm, PMOS W = 415 nm, L = 180 nm)

Note:
• Sign indicates current direction as reported by Virtuoso
• Magnitudes are used for leakage and power analysis
• Drain current corresponds to bottom NMOS in the stack

INFERENCE
1. Strong NMOS Stacking Effect at 000
o All NMOS transistors are OFF, resulting in minimum drain current (~pA).
o Subthreshold leakage is significantly reduced due to stack-induced VDS reduction and increased
effective threshold voltage.
2. Leakage Increases with Partial Stack Activation
o Input combinations such as 011, 101, and 110 show large drain currents (≈20–35 nA).
o This occurs when two NMOS devices are ON, reducing the stacking effect.
3. Maximum Static Power Not at 111
o Although all NMOS are ON at 111, the drain current is lower than some partially ON cases.
o This highlights that stack position and intermediate node biasing dominate leakage behavior.
4. Gate Leakage Trends
o Gate currents are in fA–pA range, increasing when the corresponding NMOS gate is driven HIGH.
o Gate leakage remains much smaller than drain leakage but becomes relevant in deep-submicron
nodes.
5. Source Current from VDD Correlates with Leakage
o VDD current magnitude closely follows bottom NMOS drain current.
o Highest static power is observed for 011, confirming worst-case leakage occurs with partial stack
conduction.
According to Weste and Harris, CMOS VLSI Design, the stacking of OFF NMOS transistors significantly reduces
subthreshold leakage current due to multiple physical effects. The observations from this experiment are consistent
with these principles.
1. When multiple NMOS transistors in a stack are turned OFF (input 000), the leakage current reduces
exponentially. This occurs because the voltage at the intermediate nodes rises, thereby reducing the drain-to-
source voltage (𝑉𝐷𝑆 ) across each OFF transistor.
2. The rise in intermediate node voltage introduces body effect, which increases the effective threshold voltage
(𝑉𝑇𝐻 ) of the upper NMOS devices, further suppressing subthreshold conduction.
3. Input combinations that turn ON one or two NMOS transistors (such as 011, 101, and 110) reduce the
stacking effect. As described by Weste and Harris, partial conduction lowers the intermediate node voltages,
resulting in higher leakage currents, which is observed as increased drain and VDD source currents.
4. The experimental results show that maximum static leakage does not necessarily occur when all NMOS
devices are ON (111). Instead, the worst-case leakage appears when the stack is only partially ON, which
agrees with the discussion in Weste and Harris regarding leakage paths and stack biasing.
5. The measured VDD source current closely tracks the bottom NMOS drain current, confirming that static
power dissipation in CMOS gates is primarily dominated by subthreshold leakage in the pull-down
network, as explained in the textbook.