8086 ARCHITECTURE

8086 Features
 It is a 16 bit µp.
 8086 has a 20 bit address bus can access upto 220 memory locations ( 1 MB) .
 It can support upto 64K I/O ports.
 It provides 14, 16-bit registers.
 It has multiplexed address and data bus AD 0- AD15 and A16 – A19

 16-bit Arithmetic Logic Unit


16-bit data bus
It requires single phase clock with 33% duty cycle to provide internal timing. 

8086 is designed to operate in two modes, Minimum and Maximum. 

It can prefetches upto 6 instruction bytes from memory and queues them in order to speed

up instruction execution.  
 It requires +5V power supply.

 16 bit flag

 Clock frequency range is 5-10 MHZ

 Designed by Intel

 Rich set of instructions

40 Pin DIP, Operates in two modes
 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit
(EU).The
 The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands.
 The instruction bytes are transferred to the instruction queue.
The BIU contains the following registers:

 
 IP - the Instruction Pointer


CS - the Code Segment Register


DS - the Data Segment Register


SS - the Stack Segment Register

ES - the Extra Segment Register

 instruction queue
The BIU fetches instructions using the CS and IP, written CS: IP, to construct the 20-
bit address. Data is fetched using a segment register (usually the DS) and an effective
address (EA) computed by the EU depending on the addressing mode.
 EU executes instructions from the instruction system byte queue
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register
The EU contains the following 16-bit registers:

 
 AX - the Accumulator
 
 BX - the Base Register
 
 CX - the Count Register
 
 DX - the Data Register
 
 SP - the Stack Pointer
 
BP - the Base Pointer

SI - the Source Index Register

DI - the Destination Register
 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

These are referred to as general-purpose registers, although, as seen by their names,

they often have a special-purpose use for some instructions. The AX, BX, CX, and DX
registers can be considered as two 8-bit registers, a High byte and a Low byte. This
allows byte operations and compatibility with the previous generation of 8-bit processors,
the 8080 and 8085. The 8-bit registers are:

 
 AX --> AH,AL
 
 BX --> BH,BL
 
 CX --> CH,CL
 
DX --> DH,DL

The ALU performs all basic computational operations: arithmetic, logical, and
comparisons. The control unit orchestrates the operation of the other units. It fetches
instructions from the on-chip cache, decodes them, and then executes them. Each
instruction has the control unit direct the other function units through a sequence of steps
that carry out the instruction's intent. The execution path taken by the control unit can
depend upon status bits produced by the arithmetic logic unit or the floating-point unit
(FPU) after the instruction sequence completes. This capability implements conditional
execution control flow, which is a critical element for general-purpose computation.

ES Extra Segment
BIU registers
(20 bit adder)
CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
EU registers
16 bit arithmetic DI Destination Index Register
FLAGS
8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

Most of the registers contain data/instruction offsets within 64 KB memory segment.

There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low order byte of
the word, and AH contains the high-order byte. Accumulator can be used for I/O
operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte. BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the low
order byte of the word, and CH contains the high-order byte. Count register can be used
in Loop, shift/rotate instructions and as a counter in string manipulation.
Data register consists of two 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low order
 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

byte of the word, and DH contains the high-order byte. Data register can be used as a port
number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.

The EU also contains the Flag Register which is a collection of condition bits and
control bits. The condition bits are set or cleared by the execution of an instruction. The
control bits are set by instructions to control some operation of the CPU.
 
 Bit 0 - CF Carry Flag - Set by carry out of MSB
 
 Bit 2 - PF Parity Flag - Set if result has even parity
 
 Bit 4 - AF Auxiliary Flag - for BCD arithmetic
 
 Bit 6 - ZF Zero Flag - Set if result is zero
 
 Bit 7 - SF Sign Flag = MSB of result
 
 Bit 8 - TF Single Step Trap Flag
 
 Bit 9 - IF Interrupt Enable Flag
 
 Bit 10 - DF String Instruction Direction Flag
 
 Bit 11 - OF Overflow Flag
 
Bits 1, 3, 5, 12-15 are undefined
 Question: how to generate memory address?
Ans: Physical address = segment address*10+offset address

Example: we have segment no 6020h and offset is 4267h then 60200+4267=64467h
physical address.

8086 PIN CONFIGURATION

The pins and signals of 8086 can be classified into six groups, they are as follows.


Address/status bus


Address/data bus


Control and status signals


Interrupts and external initiated signals

Power supply and clock frequency signals
The 8086 works in two modes, minimum and maximum. Accordingly pin configuration
changes. They are 32 signals common to both modes. Remaining 8 pins are different for
each mode. Let us describe each signal/pin.
Vcc (pin 40): Power

Gnd (pin 1 and 20): Ground

AD0...AD7, A8...A15, A19/S6, A18/S5, A17/S4, and A16/S3: 20 -bit Address Bus

MN/MX’ (input): Indicates Operating mode

READY (input, Active High): take µP to wait state

CLK (input): Provides basic timing for the processor

RESET (input, Active High): At least 4 clock cycles Causes the µP immediately
terminate its present activity.
TEST’ (input, Active Low): Connect this to HIGH

HOLD (input, Active High): Connect this to LOW (BR)

HLDA (output, Active High): Hold Ack (BG)

INTR (input, Active High): Interrupt request

INTA’ (output, Active Low): Interrupt Acknowledge

NMI (input, Active High): Non-mask able interrupt

DEN’ (output): Data Enable. It is LOW when processor wants to receive data or
processor is giving out data (to74245)

DT/R’ (output): Data Transmit/Receive. When high, data from µP to memory When
Low, data is from memory to µP (to74245 dir)
IO/M’ (output): If High µP access I/O Device. If Low µP access memory

RD’ (output): When Low, µP is performing a read operation

WR’ (output): When Low, µP is performing a write operationALE (output): Address Latch
Enable, Active High Provided by µP to latch address When HIGH, µP is using AD0...AD7,
A19/S6, A18/S5, A17/S4, A16/S3 as address lines
 S4 S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

S2, /S1, /S0 status bits (output): pin 26, 27 and 28

These signals indicate the status of current bus cycle i.e. type of machine cycle. The
following table gives the type of machine cycles.

S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State

QS0, QS1 queue status (output) pin 24 and 25:

These signals indicate the status of instruction queue during the previous clock cycle.
These are accessed by the co-processor 8087. Following table gives the queue status.

LOCK: This output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the /LOCK signal is low. The /LOCK signal is activated by
the lock prefix instruction and remains active until the completion of the next instruction.
 MINIMUM MODE CONFIGURATION OF 8086 SYSTEM

In a minimum mode 8086 system, the microprocessor 8086 is operated in

minimum mode by strapping its MN//MX pin to logic 1.


In this mode, all the control signals are given out by the microprocessor chip
itself. There is a single microprocessor in the minimum mode system.


The remaining components in the system are latches, Tran receivers, clock
generator, memory and I/O devices. Some type of chip selection logic may be
required for selecting memory or I/O devices, depending upon the address map of

the system.

Latches are generally buffered output D-type flip-flops like 74LS373 or 8282.
They are used for separating the valid address from the multiplexed address/data

signals and are controlled by the ALE signal generated by 8086.

Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
 
 They are controlled by two signals namely, DEN and DT/R.



The DEN signal indicates the direction of data, i.e. from or to the processor. The
 system contains memory for the monitor and users program storage.

Usually, EPROM is used for monitor storage,while RAM for user’s program
storage. A system may contain I/O devices.

The working of the minimum mode configuration system can be better described  in
 terms of the timing diagrams rather than qualitatively describing the operations.

 
 
 

The opcode fetch and read cycles are similar. Hence the timing diagram can be
 is the timing diagram for read cycle and the second is the
categorized in two parts, the first
timing diagram for write cycle.

The read cycle begins in T1 with the assertion of address latch enable (ALE)
signal and also M / IO signal. During the negative going edge of this signal, the
 valid address is latched on the local bus.

The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO
signal indicates a memory or I/O operation.

 The bus
At T2, the address is removed from the local bus and is sent to the output.
 is then tristated. The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers.
After RD goes low, the valid data is available on the data bus.

The addressed device will drive the READY line high. When the processor

returns the read signal to high level, the addressed device will again tri state its bus drivers.

A write cycle also begins with the assertion of ALE and the emission of the
address. The M/IO signal is again asserted to indicate a memory or I/O operation.
In T2, after sending the address in T1, the processor sends the data to be written to

the addressed location.

The data remains on the bus until middle of T4 state. The WR becomes active at
the beginning
 of T2 (unlike RD is somewhat delayed in T2 to provide time for
floating).

The BHE and A0 signals are  used to select the proper byte or bytes of memory or
I/O word to be read or write.

The M/IO, RD  and WR signals indicate the type of data transfer as specified in
table below.

Write Cycle Timing Diagram for Minimum Mode

 Hold Response sequence: The HOLD pin is checked at leading edge of each clock
pulse. If it is received active by the processor before T4 of the previous cycle or during T1
state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting master.

The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.

69

Bus Request and Bus Grant Timings in Minimum Mode System

Read Cycle timing Diagram for Minimum Mode

Maximum Mode Configuration of 8086

A processor is in the Maximum Mode Configuration of 8086 when its MN/MX pin is grounded.
The maximum mode defines pins 24 to 31 as follows:
Pin Definitions (24 to 31) in Maximum Mode:
1.QS1, QS0 (output) : These two output signals reflect the status of the instruction queue. This
status indicates the activity in the queue during the previous clock cycle.

2.S2,S1,S0 (output) : These three status signals indicate the type of transfer to be take
place during the current bus cycle.
[Link] : This signal indicates that an instruction with a LOCK prefix is being executed
and the bus is not to be used by another processor:
[Link]/GT1 and RQ/GT0 : In the Maximum Mode Configuration of 8086, HOLD and
HLDA pins are replaced by RQ (Bus request)/GT0 (Bus Grant), and RQ/GT1 signals. By
using bus request signal another master, can request for the system bus and processor
[Link] the request is granted to the requesting master by using bus grant. Both
signals are similar except the RQ/GT0has higher priority than RQ/GT1.

Maximum Mode Configuration:

Fig. 10.8 shows the typical Maximum Mode Configuration of 8086. In the maximum mode
additional circuitry is required to translate the control signals. The additional circuitry converts
the status signals (S2-S0) into the I/O and memory transfer signals. It also generates the control
signals required to direct the data flow and for controlling 8282 latches and 8286 transceivers.
The Intel 8288 bus controller is used to implement this control circuitry.
Fig. shows that the 8288 is able to originate the address latch enable signal to the 8282’s, the
enable and direction signals to the 8286 transceivers, and the interrupt acknowledge signal to the
interrupt controller. It also decodes the S2-S0 signals to generate MRDC, MWTC, IORC, IOWC,
MCE/PDEN, AEN, IOB, CEN, AIOWC, and AMWC signals.
MRDC (Memory Read Command) : It instructs the memory to put the contents of the
addressed location on the data bus.
MWTC (Memory Write Command) : It instructs the memory to accept the data on the data
bus and load the data into the addressed memory location.
IORC (I/O Read Command) : It instructs an I/O device to put the data contained in the
addressed port on the data bus.
IOWC (I/0 Write Command) : It instructs an I/O device to accept the data on the data bus and
load the data into the addressed port.
MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls the mode of
operation of 8259. It selects cascade operation for 8259 (interrupt controller) if IOB signal is
grounded and enables the I/O bus transceivers if IOB is tied high.
AEN, IOB and CEN : These pins are used in multiprocessor system. With a single processor in
the system, AEN and IOB are grounded and CEN is tied high. AEN causes the 8288 to enable
the memory control signals. IOB (I/O bus mode) signal selects either the I/O bus mode or
system busmode operation. CEN (control enable) input enables the command output pins on the
8288.
AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write Command)
: These signals are similar to IOWC and MWTC except that they are activated one clock pulse
earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.
Bus Timings for Maximum Mode Configuration of 8086:
The timing diagrams of input and output transfers are shown in the Fig. 10.10 (a) and (b)
respectively.
These are explained in steps.

1. S0,S1,S2 are set at the beginning of bus cycle. On detecting the change on
passive state S0 = S1 = S2 = 1, the 8288 bus controller will output a pulse on its ALE and apply
a required signal to its DT/R pin during T1.
2. In T2, 8288 will set DEN = 1 thus enabling transceiver. For an input, 8288 it will activates
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC
is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
3. The status bits S0 to S2 remain active until T3, and become passive during T3 and T4.
4. If ready input is not activated before T3, wait state will be inserted between T3 and T4
[Link] a neat block diagram, explain the architecture of 8086 microprocessor or Draw and
explain the functions of each block in the internal architecture of 8086 .8 marks

1.1 8086 Architecture

It is implemented in HMOS technology. The 16 bit CPU is available in 3 clock rates: 5,8,10
MHz. The internal functions are divided into two processing units which are Bus Interface
Unit(BIU) and Execution Unit(EU).
The BIU performs the following functions:
1. Instruction fetching and queuing,
2. operand fetching and storing, and
3. Memory relocation.
4. This unit also provides the basic bus control .
5. It overlaps instruction pre fetching with instructions execution and improves processor
performance.
6. When the current instruction is being decoded and executed, it can fetch and store 6 bytes
of next instructions. Fetching the next instruction while the current instruction executes is
called pipelining.
7. Whenever there is a space for atleast 2 bytes in the instruction queue, the BIU attempts a
word fetch memory cycle. The queue acts as first in first out buffer.

The Execution Unit performs the following functions:

1. The EU receive the pre-fetched instructions from the BIU queue, decode and execute the
instructions by generating the required timing and control signals.
 2. If the instruction contains operand addresses then they are passed to the BIU.
3. BIU provide the memory operands to the EU which then complete the operation of the
instruction.
4. Effective address is calculated for the required addressing modes by ALU and sent to the
BIU.
5. The result of the instruction operation are stored in registers or stored in memory by
sending it to BIU.
6. Depending on the result of the instructions, the flag register bits are set. The EU has a 16
bit ALU which can add, sub, AND ,OR,XOR,INC, DEC, complement or shift binary
numbers.

Explain the memory organization of 8086. Or What are the different segment
registers in 8086? Why need memory segmentation?

Memory Segmentation:
8086 programs are stored in memory in a structured way. Program instructions or machine code
is stored in a separate section of the memory and the area is called Code segment. The base area
is fixed by loading CS register with Upper 16 bits of the starting address of the code segment.
Data is stored in a separate area called as data segment . The upper 16 bits of the base address of
the data segment is loaded into DS register. For more data one more section of the memory
known as extra segment can be used and it’s starting address is loaded into ES register.
Data related to procedure and return addresses of call instruction are stored in separate section of
the memory called as stack segment. It’s starting address is loaded into SS register.
At a time a 8086 program may use only code segment or code and data segment or all 3 or 4
segments as per requirement. If the program uses interrupts or procedures than stack segment is
used.
A segment size can vary from 16 bytes to 64 kbs. Segment can be overlapped and segments can
be combined into a single segment by using the same base address in segment registers.
Relocatable segments:
All data or code access from memory are made relative to base addresses contained in segment
registers. Hence program contain only offset addresses.
The segment register to be used is automatically chosen by the instruction types. By changing the
contents of segment registers, the location of segments in the memory are changed. Hence the
programs are shorter, faster and more structured.
Word operands can be located on even or odd address boundaries. The least significant byte of
the word operand is stored in the lower address location and the most significant byte in the next
higher address location. The word operand is fetched by BIU in one memory access if the word
is aligned with even byte boundary and take two memory access if the word is aligned with odd
byte boundary.
Advantages of memory segmentation:
1. Allows 1 MB memory addresses to be handled by 16 bit registers.
2. Allows placing of code, data and stack portions of the same program in different sections
of memory which provide data and code protection.
3. Makes the program re locatable to different areas and get executed.
4. The data segment can be used by many programs.
5. Multiprogramming capability is introduced.
6. Programs become shorter and executes faster because 16 bits offset addresses are used
instead of 20 bit memory operand addresses.

Explain the physical address calculation mechanism

Generating a physical address:

The part of a segment starting address stored in a segment register is often called
the segment base. The 20 bit physical address is represented in the form:
Segment base: offset
The content of segment register (segment address) is shifted left bit-wise four times.
The content of an offset register (offset address) is added to the result of the
previous shift operation.
These two operations together produce a 20-bit physical address.
For example, consider the physical address is 2010: 3535.

Then the physical address is calculated as:

Segment Base Address 2010H 0010 0000 0001 0000
Shifted left by
4 bit positions 0010 0000 0001 0000 0000
+
16 bit offset address 0011 0101 0011 0101
---------------------------------------------------------------
physical address 0010 0011 0110 0011 0101

2 3 6 3 5
The segment address by the segment value 2010H can have offset value from 0000H
to FFFFH within it, ie. Maximum 64K locations may be accommodated in the
segment.
The physical address range for this segment is from 20100H to 300FFH.
The segment register indicates the base address of a particular segment and CS, DS,
SS and ES are used to keep the segment address.
The offset indicates the distance of the required memory location in the segment
from the base address, and the offset may be the content of register IP, BP, SI, DI and
SP.

The following table gives the type of operation and the default segment used
for the physical address calculation.

Types of memory Default Segment Alternate Segment Offset (Logical

Reference Address)
Instruction fetch CS None IP
Stack operation SS None SP
General data DS CS, ES, SS Effective address
String source DS CS, ES, SS SI
String destination ES None DI
BX used as pointer DS CS, ES, SS Effective address
BP used as pointer SS CS, ES, SS Effective address
Branching
Instruction CS None Effective address
Types of Addressing Modes in 8086
The different ways in which a source operand is denoted in an instruction is known
as addressing modes.
There are 8 different addressing modes for data in 8086 programming −
I. Addressing modes for data
1) Immediate addressing mode
2) Register addressing mode
3) Direct memory addressing mode
4) Register indirect addressing mode
5) Register relative addressing mode
6) Base indexed addressing mode
7) Relative based indexed addressing mode
8) Implied addressing mode
II. Addressing Modes for Program Memory
1)Intra segment direct mode
2) Intra segment indirect mode
3) Inter segment direct mode
4) Inter segment indirect mode
III. Addressing Modes for I/O ports
1) Direct or fixed port addressing mode
2) Indirect or Variable port addressing mode

1. Immediate addressing mode:

In this type of addressing, immediate data is a part of instruction, and

appears in the form of successive byte or bytes.

Example: MOV AX, 0005H.

In the above example, 0005H is the immediate data. The immediate data may be 8- bit or
16-bit in size.
2. Direct addressing mode:

In the direct addressing mode, a 16-bit memory address (offset) directly specified
in the instruction as a part of it.
Example: MOV AX, [5000H].

3. Register addressing mode:

In the register addressing mode, the data is stored in a register and it is referred
using the particular register. All the registers, except IP, may be used in this mode.

Example: MOV BX, AX

4. Register indirect addressing mode:
Sometimes, the address of the memory l o c a t i o n which contains data or
operands is determined in an indirect way, using the offset registers. The mode of
addressing is known as register indirect mode.
In this addressing mode, the offset address of data is in either BX or SI or DI
Register. The default segment is either DS or ES.

Example: MOV AX, [BX].

5. Indexed addressing mode:
In this addressing mode, offset of the operand is stored one of the index registers.
DS & ES are the default segments for index registers SI & DI respectively.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS.
6. Register relative addressing mode:
In this addressing mode, the data is available at an effective address formed by
adding an 8-bit or 16-bit displacement with the content of any one of the register BX, BP,
SI & DI in the default (either in DS & ES) segment.

Example: MOV AX, 50H [BX]

7. Based indexed addressing mode:
The effective address of data is formed in this addressing mode, by adding content
of a base register (any one of BX or BP) to the content of an index register (any one of SI
or DI). The default segment register may be ES or DS.

Example: MOV AX, [BX][SI]

8. Relative based indexed addressing mode:
The effective address is formed by adding an 8 or 16-bit displacement with the
sum of contents of any of the base registers (BX or BP) and any one of the index
registers, in a default segment.

Example: MOV AX, 50H [BX] [SI]