MATCHING IN LAYOUT
Introduction
Matching is a very important technique in Analog IC layout. It helps
compensating a lot of undesirable layout-dependent effects. In IC design
there are multiple sources of nonidealities that affect IC performance.
We can split them into two categories:
1. Manufacturing-related
2. Environmental
1. Manufacturing-related sources include dopant gradients, oxide
thickness gradients, and mechanical stress, which are very hard to
predict and simulate.
2. Environmental factors include temperature gradients which are
also hard to predict.
Gradient Types
There are 3 types of gradients
1. Dopants gradients
2. Temperature gradients
3. Mechanical stress
1. Dopants gradients
Manufacturing imperfections due to ion beam gradients,beam
angles, etc.
2. Temperature Gradients
Environmental factors,includes temperature variations and self-
heating.
3. Mechanical stress
Manufacturing and packaging imperfection due to material density
variations and thermal impact during welding.
There are two main types of mismatches:
1. Systematic mismatch
2. Random mismatch
MISMATCH
Systematic Mismatch Random Mismatch
Mask-related Gradient Mismatch
mismatch
➢ Mechanisms ➢ Caused by ➢ Caused by
have equal process statistical
effects on each gradients; fluctuations in
device of equal ➢ Affects devices processing
size; that are placed conditions or
far from each material
➢ Has to be other properties.
considered at the
schematic ➢ Matched devices ➢ Highly
design stage; has to be placed dependant on
close to each the level of
➢ Example: other to avoid device
Variation in this effect; dispersion
width/length of
the device. ➢ Example:
Variation in Vth
of the transistor.
Mismatch Compensation
Mismatch Compensation
Mask-related Gradient Random
mismatch mismatch mismatch
➢ Use multiples ➢ Maximize unit ➢ Use devices
of unit sized device size; with the same
devices; ➢ Maximize size,
➢ Use dummies Area/Perimete orientation,
to create r ratio (use location;
similar square shape); ➢ Maximize the
surroundings. ➢ Place matched dispersion of
devices close the device
to each other. distribution
Matching methodology
Matching Techniques
Matching - is a very useful technique in IC layout targeting similar
performance from every device in analog design. Let's take a look on a
very simple example - a current mirror (1:2). Reference current Iref is
copied from device A (2 fingers, 2 multipliers) to the device B (2
fingers, 4 multipliers) producing an output current Iout = 2Iref. For a
current mirror to exhibit a good performance it is required that both
devices A&B have the same performance.
First, let's have a look on the placement without matching and apply a
linear gradient to it:
Gradient impact on unmatched devices
Now we can summarize the total impact on the each devices:
A=1+2=3
B=3+4+5+6=18
Keeping in mind that the device B is 2 times larger than device A:
[A=3] < [B=9]
We can clearly see, that the impact of the linear gradient on the device B
is 3 times larger than on the device A. It means that if we have any
gradient on this current mirror (i.e. dopants gradient), device B will
have, for example, a different VthVth , and this will negatively affect the
accuracy of the current mirror circuit.
Let's now apply an interdigitation pattern to our devices. To have a
symmetry in our placement, we should implement a BBAABB pattern:
In this case, the total impact on each device:
A=3+4=7
B=1+2+5+6=14
Keeping in mind that the device B is 2 times larger than device A:
[A=7] =[B=7]
We can clearly see, that the impact of the linear gradient on both devices
is equal and will not affect the accuracy of the circuit. Now, let's take a
2-dimensional example and see, how dummies together with matching
help us to achieve the best performance.
Placement
Correct placement of the devices is playing a vital role in layout. Placing
devices as evenly as possible will reduce a lot of unwanted effects. Let's
have a look on the placement examples and discuss their impact on the
design.
For the first example on the image above, we can see that two devices
has a different orientation. This will lead to a variation in device
parameters due to gradients that are going along the different axis of
symmetry. It worth mentioning that it is always recommended to keep
gate orientation same for all the devices in the design, and for more
advanced technologies (28nm and below) it is mandatory. The second
example shows two devices with different widths. In this case, the main
problem is the different size of the masks that will lead to different edge-
effects for each device. The third example shows two devices with a
different lengths. Those devices will also have a different size masks,
affecting the performance in the same way as in a previous example.
We should also be aware of not only the shape and orientation of the
matched devices themselves, but also about the surrondings. ASIC are
usually contain sensitive analog blocks, such as amplifiers, bandgaps
and comparators together with a noisy or high-current blocks, such as
LDOs, drivers and digital logic. Those blocks may create a lot of
substrate noise and temperature gradients, that may impact the
performance of the sensitive devices.
As shown in the example above, in the first case, the location of the
matched devices with respect to the agressor is incorrect, because the
gradient, caused by the agressor is affecting both devices unequally. In
the second case, both devices are located symmetrically to the agressor,
hereby reducing and equalising the stress on the sensitive devices.
Matching Summary