EXPT NO.

:2
DATE

DESIGN ANDIMPLEMENTATION OF ENCODERAND BCD T07SPGMENI

1o convert a givenoctal input to the binary output and to study the LED display using
7447 7-segment decoder/ driver.

APPARATUS REQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1 3 VP NAND GATE IC7410 2
2. OR GATE IC7432 3
3. NOT GATE IC 7404 1
2 IC TRAINER KIT 1
3. PATCH CORDS 27

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder
has 2" input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when DO = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
intocoded output where input and putput codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
ie there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2" possible outputs. 2n
output values are from 0 through out 2"-1.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(ii) Observe the output and verify the truth table.

PIN DIAGRAM FOR IC7445:

BCD TODECIMAL DECODER:

OIP
VCC 16
2 OIP 15
3 OIP WP 14

4 OIP 7 WP 13

5 OIP VP 12

6 OIP OIP 1

7 OIP 5 OIP 10

GND OIP

PIN DLAGRAM FOR IC 74147:

16 VCC
1
15 NC
2

13 3

E8 12 -E2
11 E1

7 10

GNO 8 QA
LOGIC DIAGRAM FOR ENCODER:
Y1 Y2 Y3 Y4 Y5 Y6 Y7

7432

7433
a+ Y6 + Y6+ Y7
7432

7432 B
B Y2+Y3 + Y6 + T
7432

7432

7432

7432
C Y1+ Y3+ Y5 + Y7
7493

TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

0 .
0 0

0 1 0 0 1

0 0 1

0 0

0 0 1 1 0

0 0 1 1 0
0 0 0. 1 1 1
 LOGICDIAGRAM FOR DECODER:

A B

7404 /404 7404

DO

7410

D1
|

7410

D2

7410

D3

7410

TRUTH TABLE:

INPUT OUTPUT

A DO D1 D2 D3
1 1

0 0 1 1
0 1 1 0 1 1

0) 0 1
1 1 1
PIN DETAILS:
74140

TH
INO AD
IN1
IN2 A1
IN3
IN4 AZ
INS
ING GS 14
IN7
15
,

TRUTHTABLE:
Ea A B C D EF G H Qa(V) Qi(V) QolV) Es(V) EoV)
1 X X XX 1 1

1 1 1 1 1

X 1 1 1 1

1 1 1 1 1 1 1 1

X 1 1 1 |1 0

|1 1

1 1 0 1

0 0 1

0 1 1 1 1 1 1

RESULT:
Thus encoder and decoder were designed and implemented using logic gates and IC
7445 and IC
74147 were studied.