ARM Based Embedded System Design

Unit-2
ARM Philosophy
RISC - Reduced Instruction Set CISC – Complex Instruction Set
Computing Computing

Emphasis on Software Emphasis on Hardware

Single-clock, Includes multi-clock
reduced instruction only complex instructions
Register to register: Memory-to-memory:
"LOAD" and "STORE" "LOAD" and "STORE"
Low cycles per second, Small code sizes,
large code sizes high cycles per second
32 Bit Instructions 16 – 64 Bit Instructions
[Link] to Register Load and Store:
1. In this type of operation, data is transferred directly between CPU registers
2. Data doesn’t pass through memory; instead, it moves directly from one register to another within the CPU
3. This operation is typically very fast because it involves accessing data from high-speed internal registers
4. It is commonly used for arithmetic and logical operations within the CPU, where data needs to be quickly
manipulated.
[Link] to Memory Load and Store:
1. In this type of operation, data is transferred between two locations in the memory
2. The data is fetched from one memory location and stored into another memory location
3. This operation involves accessing data from the system memory, which is slower compared to accessing
registers
4. It is typically used for transferring data between different parts of memory, such as copying arrays or
moving data between RAM and peripheral devices
 Developed by Processor vs. MCU
ARM

Cortex-M4 Debug
32-bit
Core System Microprocessor.
Internal Bus
32-bit Data path.
STM32 411
Peripherals Memory 32-bit
Register bank.
Clock &
I/O
Developed Reset 32-bit Memory
by Chip interfaces.
Manufacturer
(ST Microelectronics)
The RISC Design Philosophy
• Delivering simple but powerful instructions that execute in a single cycle at high clock speed
• RISC philosophy
• focuses on reducing the complexity of instructions performed by the hardware
• Provides greater flexibility and intelligence in software (greater complexity at Compiler)
• The RISC philosophy is implemented with four major design rules:

1. Instructions
1. Reduced number of instructions
2. Simple operations that can be executed in single cycle
3. Compiler and Programmer handles complicated operations (Multiplication using multiple addition)
4. Fixed length instructions to allow pipelining (fetching of next instruction before decoding the
current instruction)
The RISC Design Philosophy
2. Pipelines

1. The processing of instructions is broken down into smaller units that can be executed in parallel by

pipelines

2. In pipeline the execution advances by one step for each cycle and maximizes throughput

3. Registers

1. RISC machines have a large set of GPRs (General Purpose Registers) to handle data or address

2. Registers acts as fast storage elements required during processing operations

3. It stores the state of the processor. It is used in arithmetic operations, intermediate variable storage,

temporary address storage etc.

The RISC Design Philosophy
4. Load-Store Architecture
1. The processor operates on data held in registers
2. Separate load and store instructions transfer data between the register bank and memory
3. Memory accesses are costly, so separating memory from data processing is advantageous in terms of
multiple accesses to data using registers
RISC processor is simple -> thus core can operate at higher clock frequencies
Non-Pipelined vs Pipelined Architecture
3-Stage Pipelining
There are three stages in this pipeline method:
[Link] – The instruction is fetched from the memory and stored in the instruction register.
[Link] – The instruction is moved to the decoder which decodes the instruction. It activates the
appropriate control signals and takes the necessary steps for the the next execution stage.
[Link] – The instruction is executed. Data transfer, logical and arithmetic operations all take
place during this stage
Special Case (Pipeline behavior for Multiple Cycle Instructions)
For simple instructions, the execute stage last only one clock cycle. But there are some instructions which has
a multi-cycle execution stage. For example. STR
Basic Features of ARM
[Link] Architecture: ARM processors are based on RISC architecture. They have a relatively small set of
simple and highly optimized instructions, which allows for efficient execution of code.
[Link] Efficiency: ARM processors typically consume less power compared to other architectures, making
them ideal for battery-powered devices like smartphones and tablets.
[Link]: ARM processors come in a wide range of configurations, from simple microcontrollers to
powerful multi-core processors.
[Link]: ARM processors are designed to be highly compatible with different software and operating
systems led to its widespread adoption and popularity in a variety of devices and platforms.
[Link]: Allows for a high degree of customization by manufacturers. This means that companies
can design their own ARM-based processors with specific features and optimizations tailored to their needs.
6.ARMv8-A Architecture: The latest version of ARM architecture, ARMv8-A, introduces support for 64-bit
processing along with other enhancements for improved performance and security.
Myths and Misconceptions about ARM
1.A Manufacturer: ARM Holdings, now part of NVIDIA, designs and licenses ARM processor architectures
but does not manufacture or sell actual chips. Instead, ARM licenses its technology to semiconductor
companies and device manufacturers, who then incorporate ARM designs into their products.
[Link] to Mobile Devices: While ARM processors gained popularity initially in mobile devices like
smartphones and tablets, they are not limited to these devices. ARM processors are used in a wide range of
applications beyond mobile, including embedded systems, IoT devices, networking equipment, servers, and
some desktop and laptop computers.
[Link] Inferior in Performance: There's a misconception that ARM processors are inherently inferior
in performance compared to x86 processors commonly used in desktop and laptop computers. However, ARM
processors have made significant advancements in performance over the years.
[Link] Low-End: While ARM processors are commonly used in low-power and cost-effective
devices, they are also employed in high-end and performance-critical applications. ARM-based processors can
be found in entry-level smartphones as well as high-performance supercomputers.
ARMs Approach Towards RISC
• Power Consumption
• High Code Density
• Slow and Low Cost Memories
• Physical Size
• Hardware Debugging facility
Instruction Set used in ARM
• Variable cycle execution for certain instructions
• Inline barrel shifter leading to more complex instructions
• performs bitwise shifting operations on binary data
• shift the bits of a binary number left or right by a specified number of positions
• Unlike a simple shift operation that shifts bits one position at a time, a barrel shifter can perform
multiple shifts in parallel, which improves the speed of shifting operations
• Thumb 16-bit instruction set
• ARM uses 16-bit instructions instead of the regular 32-bit instructions
• Thumb instructions offer reduced code size compared to the ARM instruction set
• subset of the ARM instruction set, providing a balance between code size and performance
• Conditional execution
• Conditional execution is a feature in ARM architecture that allows instructions to be executed
conditionally based on the status of the processor's condition flags.
Instruction Set used in ARM
• BUS Structure of ARM
• Pipelining
BUS Structure of ARM (AMBA – Harvard Bus Architecture)
• The Advanced Microcontroller Bus Architecture (AMBA) is a widely-used bus standard developed by
ARM for on-chip communication in System-on-Chip (SoC) designs
• It defines a set of protocols for high-performance, low-latency communication between components such
as CPUs, memory controllers, DMA controllers, and peripherals
• In the context of AMBA, the Harvard Bus Architecture is implemented to provide efficient data
transfer between the CPU (which fetches instructions from the instruction memory) and other
components like memory or peripherals (which interact with data memory)
• AMBA consists of several interconnect protocols, with Advanced High-Performance Bus (AHB) and
Advanced Peripheral Bus (APB) being the most commonly used.
• AHB is a high-performance bus protocol to connect high-bandwidth peripherals & memory components
• APB is a lower-performance, lower-power protocol used to connect low-bandwidth peripherals
Introduction - ARM Cortex M4
In today’s technology-driven world, embedded systems play a crucial role in powering various devices and
applications. One of the key components in the design and development of these systems is the ARM Cortex
M4 microcontroller.
Cortex M4 is specifically designed for embedded systems, where its small size and low power consumption
make it an ideal choice.
The Cortex-M0...M3 processors are designed to deliver industry-leading deterministic behavior, lowest
sleep & dynamic power, & smallest area possible whilst maintaining high processing efficiency
The Cortex-Rx delivers a roadmap from Classic ARM processors including the ARM7...11 families, enabling
existing applications to be easily ported to a higher performance platform
The family CORTEX Mx is divided into four subgroups that are: M0, M1, M3 and M4.
The computing power of CORTEX Mx is in the range from 0.84 DMIPS/MHz to 1.25 DMIPS/MHz.
ARM consider obsolete the families: ARM7, ARM9 and ARM11.
ARM Cortex – M4
Architecture: Harvard
Bus Interface: AMBA – Harvard Bus Architecture
Buses: AHB and APB
Pipeline: 3 Stage – Fetch, Decode, Execute
Arithmetic: Floating-Point Unit Processor
MPU: Memory Protection Unit
Bit Manipulation: Bus Level Bit Banding
NVIC: Nested Vectored Interrupt Controller
Wakeup: Sleep Controller for power saving
Debug: JTAG and Serial Wire Debug
Core: Armv7
Key features of Arm Cortex-M4 core
The Arm Cortex M4 core incorporates several features that contribute to its performance and versatility. These
key features include:
1. Thumb-2 Instruction Set: The Thumb-2 instruction set provides a balance between code density and
performance by offering both 16-bit and 32-bit instructions
2. Single-Cycle Multiplication: The Cortex-M4 core supports single-cycle 32-bit multiplication and 64-bit
multiplication with accumulated results, enhancing performance in arithmetic-intensive applications
3. Memory Protection Unit (MPU): The MPU allows for the partitioning of memory regions and provides
protection against unauthorized access, enhancing system security and reliability
4. Integrated Floating-Point Unit (FPU): The FPU enables precise floating-point arithmetic operations,
improving performance in applications that involve complex mathematical calculations
5. Low Power and Sleep Modes: Cortex-M4 microcontrollers incorporate various power-saving modes,
such as sleep and deep sleep, allowing for efficient power management and extended battery life.
Applications of ARM Cortex-M4 processors in Embedded Systems
Some key applications of ARM Cortex-M4 processors in embedded systems include:

1. Real-time Applications: Well-suited for real-time applications that require precise timing and

responsiveness. Offers predictable and deterministic execution, making them ideal for such applications

2. Low-Power Design: Known for their energy-efficient designs, enabling the development of battery-powered

and environmentally friendly devices. Applications like wearables, IoT devices

3. Multimedia Processing: Equipped with Digital Signal Processing (DSP) capabilities, enabling efficient

multimedia processing. Applications such as audio & speech processing, image & video processing

4. Connectivity: Provide extensive support for various communication protocols, including Wi-Fi, Bluetooth,

Ethernet, and USB. This enables seamless connectivity and integration with other devices and networks,

making them suitable for applications that require network connectivity and communication.
Criteria for Choosing a Microcontroller