Following projects may be proposed using Python simulations.
And all are framed from the covered
syllabus only. Please check the feasibility and discuss.
List of prjects
1. Python Simulation of Basic Computer Organization
Build Python model of CPU, ALU, registers, memory, and bus. Simulate data flow for sample
operations and print stepwise transfer traces.
2. Von Neumann vs IAS Architecture Trace Simulator
Simulate instruction storage and execution flow for Von Neumann and IAS models. Generate
stepwise traces and compare memory access patterns.
3. CISC vs RISC Execution Count Simulator
Create two small instruction sets and simulate the same task. Compare instruction count, cycles, and
memory references using Python logs.
4. Instruction Execution Cycle State Machine
Implement fetch, decode, execute, memory, writeback as a Python state machine. Run sample
instructions and output cycle-by-cycle tables.
5. Addressing Modes Effective Address Calculator
Simulate multiple addressing modes in Python. Compute effective addresses for given registers and
memory values and validate results with test cases.
6. Instruction Format Encoder and Decoder
Design instruction formats and implement Python encoder/decoder for zero, one, two, three address
instructions. Output binary fields and decoded meanings.
7. Signed Number Representation Simulator
Convert integers into sign-magnitude, 1’s complement, and 2’s complement in Python. Demonstrate
addition/subtraction with overflow detection.
8. Booth Multiplier Step-by-Step Simulator
Implement Booth multiplication in Python. Display accumulator, multiplier, and partial product at
each cycle and verify final signed product.
9. Fast Multiplication Comparison Tool
Simulate shift-add multiplication and a faster method in Python. Compare number of additions,
shifts, and total steps for multiple operand pairs.
10. Binary Division Algorithm Simulator
Implement restoring or non-restoring division in Python. Print stepwise quotient and remainder
updates and validate final division results.
11. Floating Point Addition Simulator
Simulate floating point addition steps: alignment, mantissa addition, normalization, rounding. Output
intermediate exponent and mantissa values per stage.
12. Floating Point Multiplication Simulator
Implement floating point multiplication steps: exponent addition, mantissa multiplication,
normalization. Show intermediate states and final floating-point result.
13. Decimal Arithmetic Using BCD Simulator
Implement BCD addition and subtraction with correction logic in Python. Show intermediate
correction and carry handling for multiple test cases.
14. ALU Micro-Operations Simulator in Python
Build ALU simulation supporting arithmetic, logic, and shift micro-operations. Provide menu driven
tests and output result with flags per operation.
15. Hardwired Control Unit FSM Simulation
Design a finite state machine for hardwired control. Generate control signals per cycle for
instructions and print timing-like signal tables.
16. Microprogrammed Control Unit Simulation
Create microinstruction format and control memory table in Python. Simulate micro-sequencing for
each instruction and output executed micro-operations.
17. Hardwired vs Microprogrammed Control Comparison
Run identical instruction sequences on both control simulations. Compare cycle counts, control
steps, and produce a short Python-generated comparison report.
18. I/O Organization Handshake Simulation
Simulate CPU and device interface with status and control registers. Demonstrate programmed I/O
read/write with handshake and timing steps.
19. Interrupt Driven I/O Simulation
Implement interrupt requests, priority handling, ISR execution, and return flow. Output interrupt
latency, service order, and CPU state changes.
20. DMA Controller Transfer Simulation
Simulate DMA block transfer between I/O and memory. Compare CPU-busy time versus DMA mode
and print bus ownership timeline.
21. Pipeline Stage Occupancy Visualizer
Simulate instruction flow through pipeline stages. Generate stage-occupancy table per cycle and
compute throughput and total cycles.
22. Pipeline Hazard Detector and Stall Inserter
Detect structural, data, and control hazards in an instruction stream. Insert stalls or forwarding
decisions and output final pipeline schedule.
23. Pipeline Speedup and CPI Calculator
Compute speedup, CPI, and efficiency for different pipeline depths and hazard rates. Provide Python
report for multiple configurations.
24. Parallel Processor Concept Simulation
Simulate two-core execution of independent tasks and shared resource contention. Compare
completion time with single-core baseline using simple cycle counts.
25. Memory Hierarchy Access Time Simulator
Model memory hierarchy levels and access probabilities. Compute average access time and show
impact of changing hit rates using Python.
26. Main Memory Cell Read/Write Operation Demo
Create a conceptual memory cell model. Simulate read/write steps with state transitions and timing
sequence logs for multiple operations.
27. Direct Mapped Cache Simulator
Implement direct mapped cache in Python. Feed address trace, compute hits/misses, and output hit
rate with cache line status.
28. Set Associative Cache Simulator with LRU
Implement set associative cache with LRU replacement. Run address traces and output misses,
evictions, and final cache contents.
29. Write Policy Impact Simulator
Simulate write-through and write-back cache policies. Count memory writes, dirty blocks, and
compute performance impact from trace-driven simulation.
30. Cache Size vs Hit Rate Experiment Simulator
Run same trace for multiple cache sizes. Generate hit rate table and plot cache size versus hit rate
using Python.