BECE 102L

DIGITAL SYSTEM DESIGN

Module-II Verilog HDL
Module-II (Verilog HDL)
Lexical Conventions, Ports and Modules, Operators, Dataflow Modelling, Gate
Level Modelling, Behavioural Modeling, Test Bench

(5 hours)

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Introduction
Digital IC’s are classified as
• Small Scale Integration Circuit (SSI).
• Medium Scale Integration.(MSI)
• Large Scale Integration.(LSI)
• Very Large Scale Integration(VLSI)
• Ultra Large Scale Integration.(ULSI)
• Smaller circuits can be verified using simple Breadboard connections.
• Highly impossible with LSI and higher integrated circuits.
• As the design becomes more and more difficult Computer Aided Design (CAD)
are evolved for the design and testing of Digital circuits.
• So CAD tools are more popular.

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Introduction
• For a long time, programming languages such as FORTRAN, Pascal, and C were
being used to describe computer programs that were sequential in nature.

• Similarly, in the digital design field, designers felt the need for a standard language to
describe digital circuits. Thus, Hardware Description Languages (HDLs) came into
existence.

• Different HDLs are available different purpose such as Analog system design, digital
system design, and PCB design.

• Hardware description languages such as Verilog HDL and VHDL became popular.

• Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL

was developed under contract from DARPA.
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 Introduction (Continu…)
• Both Verilog and VHDL simulators to simulate large digital circuits quickly gained
acceptance from designers

• Purpose of VHDL and Verilog HDL are same but they differ in their syntax and the
levels of circuit descriptions.
• VERILOG HDL – VERIfiable LOGic HDL: Programming language used to
describe digital circuits and systems..

• Verilog Supports Digital only doesn’t support analog circuits.

• File Extension .v

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 Difference Between HDL and Programming
Language
HDL Software/programming language

•Allows both sequential and concurrent •Can only handle sequential instructions
executions.
• Successful VHDL programmer needs •Successfully written with pure logical or
thorough working knowledge of the algorithmic thinking
hardware circuits
•Memory and other logic elements are • Don't care about resource usage in C.
limited in a FPGA.

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 VERILOG HDL VHDL
• VERIfiable LOGarithmic HDL • Very high speed integrated circuit HDL
• Developed based on C-language • Developed based on ADA-language
• Case sensitive • No case sensitive
• It allows switch-level modelling • switch-level modelling is not possible
• Very simple data types • Complex data types
• User defined data types are not allowed • User defined data types are allowed
• Unary reduction operators are available • Unary reduction operators not available
• Multi-dimensional array not supported • Multi-dimensional array supported
• Code is simplified using procedure • Code is simplified using task
• Design composed of modules • Design composed of entities
• All signals are initialized to “unknown” state • All signals are initialized to “zero” state
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Simulators for Verilog HDL
• Verilog Simulators:
• Commercial Simulators:
• Xilinx ISE
• Active HDL • Open Source Simulators:
• Model Sim • Verilator
• Quartus-II • Icarus Verilog
• MP Sim • GPL cver
• VeriWell
• Online Simulators:
• [Link]
• [Link]
• [Link]

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 Simulation Vs Synthesis
In Verilog, simulation is the process of testing a system on a computer, while synthesis is the process of
converting the code into a hardware circuit
Simulation
•Tests a system on a computer before it's turned into hardware
•Helps identify potential issues and understand the system's behavior
•Can be faster than synthesis for small designs
•Can be used to debug a design by tracing every wire in the design
Synthesis
•Converts Verilog code into a hardware circuit
•Optimizes the design for performance by considering timing constraints
•Creates a circuit netlist, which is a set of logic gates and wiring
Why simulation and synthesis are important
•Simulation and synthesis work together to ensure that digital circuits are functional, perform well, and
are successfully realized
•Simulation can help identify issues before the hardware is created
•Synthesis can help optimize the design for performance
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Design Process

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 Design Methodologies
There are 2 types of design methodologies:
1. Top-down design methodology
2. Bottom-up design methodology

✓ Top-down design : First define the top-level block and identify the sub-blocks necessary
to build the top-level block.

✓ Bottom-up design : First identify the building blocks that are available to us then build
bigger cells, using these building blocks.

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Top Down Design

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Bottom Up Design

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 Verilog Program- Format

Sum = A ⊕ B
Carry =𝑨𝑩

1. Module
2. Port Declaration
3. Port directions
4. Output logic
A. Gate level modelling - Uses various gate primitives, logic diagram
must be known
B. Data flow modelling - Uses assignment statement and operators,
logical expression must be known
C. Behavioural modelling - Uses procedural & conditional statements,
circuit behaviour described as Truth table is known
D. Switch level modelling - Uses various transistor level primitives,
CMOS logic diagram must be known 15
 AND GATE -Design
Behavioral Model
Structural/Gate Level Data flow Model module andgate (y,a,b);
module andgate (y,a,b); module andgate (y,a,b); input a,b;
input a,b; input a,b; output y;
output y; output y; reg y;
and (y,a,b); assign y = a & b; always @ (a or b)
endmodule endmodule begin
if (a == 1 && b == 1)
ex: and A1(out,in1,in2); // if one y = in1 & in2 & in3; //and gate
‘AND’ gate is using A1 is not needed. If we use
y = 1;
y = in1 | in2; // or gate
multiple ‘AND’ gates identifiers are needed. else
Name of the gate id user defined (user only
assigns some specifi name).-- Don’t maintain
y = ~in1 // not gate y = 0;
the same name more than one time
y = ~ (in1 & in2) // Nand gate end
or A2(out,in1,in2);
not A3(out,in1); y = ~(in1 | in2); // Nor gate endmodule
xor A4(out,in1,in2);
y = in1 ^ in2 // xor gate
nand A4(out,in1,in2);
nor (out,in1,in2); y = ~(in1 ^ in2); //Xnor gate
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xnor A5(out,in1,in2);
 //TESTBENCH
module andgate_tb;
reg a,b;
Structural/Gate Level wire y;
andgate dut(y,a,b);
module andgate(y,a,b);
initial begin
input a,b;
a=0; b=0; //This is input a=0,b=0
output y;
#10;
and (y,a,b);
a=0; b=1; //This is input a=0,b=1
endmodule
#10;
a=1; b=0; //This is input a=1,b=0
#10;
a=1; b=1; //This is input a=1,b=1
#10;
end
initial begin
$monitor(“a=%b, b=%b, y=%b",a,b,y);
//if any changes in variables include inside monitor, it takes effect
// $monitor("name=%d",variable_name)
end
endmodule

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 Half adder-Design
Behavioral Model
Structural/Gate Level Data flow Model module half_adder (sum,carry, a,b);
module half_adder (sum,carry, a,b); output sum,carry;
module half_adder (sum,carry, a,b);
output sum,carry; input a,b;
output sum,carry;
input a,b; input a,b; reg sum,carry;
xor(sum,a,b); assign sum=a ^ b; always @ (a or b)
and(carry,a,b); assign carry =a&b; begin
endmodule endmodule if (a == 0 && b == 0)
sum = 0; carry =0;
elseif (a == 0 && b == 1)
sum = 1; carry =0;
elseif (a == 1 && b == 0)
sum = 1; carry =0;
elseif (a == 1 && b == 1)
Sum = A ⊕ B sum = 0; carry =1;
Carry =𝑨𝑩 end
endmodule

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Half adder-Design // Half_adder_tb
module half_adder _tb;
reg a;
reg b;
wire sum;
wire carry;
half_adder dut (sum,carry, a,b);
initial begin
a=1'b0; b=1'b0; // This is input a=0,b=0
#10 a=1'b0; b=1'b1; // This is input a=0,b=1
#10 a=1'b1; b=1'b0; // This is input a=1,b=0
#10 a=1'b1; b=1'b1; // This is input a=1,b=1
#10 $stop;
end
initial begin
$monitor($time, "a=%b, b=%b, sum=%b,carry=%b", a,b,sum,carry);
end
endmodule

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Verilog Program- Format : Module
• A module in Verilog consists of distinct parts.
• A module definition always begins with the keyword module and must
completed with the keyword endmodule.
• The module name, port list, port declarations, and optional parameters must come
first in a module definition.
• Port list and port declarations are present only if the module has any ports to
interact with the external environment.
• The five components within a module are - variable declarations, dataflow
statements, instantiation of lower modules, behavioral blocks, and tasks or
functions.
• These components can be in any order and at any place in the module definition.

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 Verilog Program-Format
• Example:

module <module-name> (<module-terminal-list>) ;

…
<module internals>
…
…
endmodule

• module : Signifies the beginning of the module definition

• endmodule : Signifies the end of the module definition

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A sample Verilog HDL Program
• Structure of Verilog Program:

// A simple example → comment line

module and2 (c,a, b ); → module name and port list
input a, b; → port declarations
output c; → port declarations
assign c = a & b; → body
endmodule → end of the module

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 PORTS
Verilog Type of Port
Keyword
input Input Port
output Output Port
inout Bidirectional Port

module arith1 (bi_out, out, in1,in2, in3);

inout bi_out;
output out;
input in1, in2,in3;
…
…
endmodule 23
➢ Input and output can be a group of wires, this is known as
bus.
module paralleladd (sum,carry,a,b)
➢ To declare the input or output as a bus, we need to provide output [3:0] sum;
Output carry;
with the index of the most significant bit (MSB) of the bus
input [3:0] a,b;
and the index of the least significant bit (LSB) of the bus. ---------------
---------------
endmodule
➢ For example, “input [7:0]D” statement defines an 8-bit wide
bus “D”, where the left-most bit (MSB) has the index 7 and
the right-most bit (LSB) has the index 0.

➢ Indexing a bus in Verilog is similar to indexing an array in the

C language. For example, to index the second bit of D bus,
use D[1].
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 Lexical Conventions- Keywords
Behavioral Model
Structural/Gate Level Data flow Model module andgate(y,a,b);
module andgate (y,a,b); module andgate(y,a,b); input a,b;
input a,b; input a,b; output y;
output y; output y; reg y;
and (y,a,b); assign y = a & b; always @ (a or b)
endmodule endmodule begin
if (a == 1 && b == 1)
y = 1;
else
y = 0;
end
endmodule

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Lexical Conventions- Keywords
• Keywords are predefined, special identifiers that define the language
constructs.
• All key words defined in lower case.
• Some of them are
• input, output, inout
• reg, wire, task, tri, time,
• pmos, nmos, and, or, not, wor, xnor,
• begin, parameter, buf, edge, join, medium, wait, use
• if, else, case, while, always, initial, posedge, negedge, assign
• end, endtask, endcase, endfunction, default, endtable, endmodule.

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 Lexical Conventions-Identifier
• Identifiers are name given to objects so that they can be referenced in the
design.
• Identifiers are case sensitive
• Mymodule ≠ mymodule Identifier
• Formed from {[A-Z], [a-z], [0-9], _, $}, but .. .. can’t begin with $ or [0-9].
• Identifiers cannot be Verilog keywords or system functions.
• Examples:
• andgatepr →valid
• ANDGATEPR →valid module andgate (y,a,b);
input a,b;
• and_gate →valid output y;
and (y,a,b);
• and →invalid ( ‘and is a key word) endmodule
• 3and_gate →invalid (in starting number is not allowed)
• $and_gate →invalid (in starting $ symbol is not allowed
• _and_gate →valid 28
 Lexical Conventions-Comments
• Two types of comments possible.
• Single Line Comment (\\).
• Example:
• A= x^y; // this is single line comment
• Multiple Line Comment (/*……*/).
• Example:
• /* this is example of multiline comment
A= x^y;
C=a+b; */
• Nesting of Comments not possible.

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Value Levels // Half_adder_tb
module
reg a;
reg b;
wire sum;
wire carry;
half_adder dut (sum,carry, a,b);
initial begin
a=1'b0; b=1'b0; // This is input a=0,b=0
#10 a=1'b0; b=1'b1; // This is input a=0,b=1
#10 a=1'b1; b=1'b0; // This is input a=1,b=0
#10 a=1'b1; b=1'b1; // This is input a=1,b=1
#10 $stop;
end
initial begin
$monitor($time, "a=%b, b=%b, sum=%b,carry=%b",
a,b,sum,carry);
end
endmodule

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Logical (0,1,x,z) Operation
Verilog Number

Format:
<number of bit><base><number>

Bit length in decimal. Default is host

<number of bit>
machine word size, usually 32 bit.

<base> ‘b, ‘B, ‘d, ‘D, ‘o, ‘O, ‘h, ‘H. Default is ‘d

<number> 0-9, a-f, A-F, X, Z, ?, _

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Representation of Number in Verilog

This field signifies the value of the number. For binary numbers, the characters 0, 1, x, z can be used to
form the value.
For octal numbers, the numerals 0 to 7, x, z can be used to form the value.
For decimal numbers, all the numerals, x, z can be used to form the value.
For hex numbers, all the numerals, a, b, c, d, e, f, x, z can be used to form the numbers.

This combination - the single quote character followed by b, o, d, or h - specifies the base of the
number. The character signifies binary, octal, decimal, or hexadecimal base. If this field is absent,
the number is taken as a decimal one.

If present, the decimal number in this field signifies the bit width of the number. If absent, the width
is assigned a default value by the compiler.

This field (optional) is for the sign bit. It is allowed only with the decimal numbers. If absent, the
number is taken as positive. For a number with a negative sign, the number is represented in 2's
complement form.

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Lexical Conventions-Numbers
• Number Specification allowed are
• Sized numbers
• Unsized numbers
• Unknown and high-impedance values
• Negative numbers
• Underscore character and question marks used to improve readability.
• Not allowed as the first character.
• Examples:
• 12’b1111_0000_1010
• – ‘?’is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz
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 Lexical Conventions-Sized Numbers
Examples:

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Lexical Conventions-Unsized Numbers
• Size of Number is not specified. Default size is at least 32 (depends on
Verilog compiler).
• Default base is decimal.
• Examples:

• Negative numbers can be used with negative sign (-) before size.
• Examples:
• -6’d35
• 6’d-35 // illegal
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 Lexical Conventions-Unsized Numbers
X or Z values:
• Unknown value: lowercase x or Uppercase X
• 4 bits in hex, 3 bits in octal, 1 bit in binary.
• High-impedance value: lowercase z or Uppercase Z
• 4 bits in hex, 3 bits in octal, 1 bit in binary.
• Examples:
• 12’h1a3x
• 4’hX
➢ Extending the most-significant part

➢ If MSB is 0, x or z then same value will be extended

➢ 4’bx1 = 4’bxx_x1 //Extend X for the remaining bits, if MSB is X

➢ If MSB is 1, then 0 will be extended to match with the size declared

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➢ 4’b1x = 4’b00_1x //Extend 0 for the remaining bits, if MSB is 1
Lexical Conventions- White spaces and Strings
Whitespace:
• Blank space (\b)
• Tab (\t)
• Newline (\n)
Strings:
• As like C, use double-quotes
• Examples:
• “Hello world!”
• “a / b”
• “text \t column1 \b column2 \n”

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 Data Types
Data types are mainly used to declare identifiers/variables
• The Data types used in Verilog are
• Value Set
• Nets
• Registers
• Vectors
• Integer, Real, and Time Registers
• Arrays
• Memories
• Parameters
• Strings

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 Data Types-Nets
• Nets represent connections between hardware elements.
• Just as in real circuits, nets have values continuously driven on them by the
outputs of devices that they are connected to.
• Nets are declared primarily with the keyword wire.
• Nets are one-bit values by default unless they are declared explicitly as vectors.
• The terms wire and net are often used interchangeably.
• The default value of a net is z (except the trireg net, which defaults to x ).
• Nets get the output value of their drivers.
• If a net has no driver, it gets the value z.

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wire

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Data Types-Registers
• Registers represent data storage elements.
• Registers retain value until another value is placed
onto them.
• In Verilog, the term register merely means a
variable that can hold a value.
• The default value for a reg data type is x.
• Unlike a net, a register does not need a driver.
• Verilog registers do not need a clock as hardware
registers do.
• Values of registers can be changed anytime in a
simulation by assigning a new value to the
register.
• Register data types are commonly declared by the
keyword reg. 43
Data Types-Vectors
• Examples: wire b; //scalar net variable
wire[7:0] databus; //8-bit data bus
• Represent buses
• wire[3:0] busA;
• reg [1:4] busB;
• reg [1:0] busC;
• Left number is always MSB.
• Vector assignment by position also possible.
• busB[1] = busA[3];
• busB[2] = busA[2];
• busB[3] = busA[1];
• busB[4] = busA[0];

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 Data Types-Time
▪ Used to Store the simulation time.

▪ Keyword – time.

▪ Simulation time measured in terms of seconds.

▪ $time – is invoked to get simulation time

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 Data Types-Usage restrictions
Data Flow and Structural Modeling
• Can use only wire data type.
• Cannot use reg data type.
Behavioral Modeling
• Can use only reg data type (within initial and always constructs).
• Cannot use wire data type. (within initial and always constructs).

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 OPERATORS
➢ Operators are used in expressions to produce values from operands.

➢ Operators perform an operation on one or more operands.

➢ The operators in Verilog are similar to those in the C programming.

➢ The operands may be either net or register data types.

➢ They may be scalar, vector, or bit selects of a vector.

➢ Operators which return a True/False result will return a 1-bit value

where 1 is True, 0 is False, and X is indeterminate. 56

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Operators
Many types of operators are supported by Verilog HDL. They are
• Arithmetic Operators.
• Logical Operators.
• Relational Operators.
• Equality Operators.
• Bitwise Operators.
• Reduction Operators.
• Shift Operators.
• Concatenation Operators.
• Conditional Operators.

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 OPERATORS
ARITHMETIC OPERATORS
➢ Arithmetic operators: Unary:(+, -), Binary: (+, -, *, /, %)

➢ Unary operators take precedence over the binary operators

➢ If any operand bit value is (x), then entire result is x

If a = 5, b=10, c=2’b01

➢ Integer division truncates any fractional part.

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 OPERATORS
BITWISE OPERATORS
➢ This operator compares each bit in one operand to its equivalent bit in
the other operand to calculate one bit for the result
➢ If operands are of unequal, the shorter operand is zero-filled in MSB
➢ Values X or Z will be treated as unknown value (X)
➢ If a = 3’b101, b=3’b110 and c=3’b01X, d=3’b1z0

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 OPERATORS
REDUCTION OPERATORS
➢ Unary reduction operators perform a bit-wise operation on a single
multi-bit operand to produce a single bit result.
➢ If there are the characters z and x the result can be a known value.
➢ If a = 5’b10101, b = 4’b0011, c = 3’bz00 and d = 3’bx011

First do the AND operation then NOT

First do the OR operation then NOT

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First do the XOR operation then NOT

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 OPERATORS
LOGICAL OPERATORS
➢ The operators logical AND (&&) and logical OR (||) compare operands
and results a 1-bit scalar Boolean value
➢ The unary logical negation operator (!) converts 0 to 1 and 1 to 0
➢ Always result is ONE bit value: 0, 1 or x
➢ An ambiguous truth value (x or z) remains as x
➢ If a = 3’b010 and b = 3’b000

a &&b = 1’b0
a ||b = 1’b1
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 OPERATORS
RELATIONAL OPERATORS
➢ Result is one bit value: 0, 1 or x
➢ If a = 3’b010, b = 3’b100, c = 3’b111, d = 3’b01z and e = 3’b01X.

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 OPERATORS
EQUALITY OPERATORS
➢ Compare operands bit for bit, with zero filling if the two operands are
of unequal bit-length.
➢ logical equality (==), logical inequality(!=) returns 0, 1, or x
➢ case equality (===), case inequality (!==) returns 0 or 1

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 OPERATORS
➢ If a = 3’b010, b = 3’b100, c = 3’b111, d = 3’b01z and e = 3’b01X

a = = e ; o/p = 1’bx
a == = e ; o/p = 1’b0

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 OPERATORS
SHIFT OPERATORS

➢ Regular shift operators: Left shift (<<), Right shift (>>) perform left and
right shifts on their operand by the number of bit positions specified

➢ Both shift operators fill the vacated bit positions with zeroes

➢ Arithmetic Shift operations can be used for dividing or multiplying an

integer variable.

➢ The arithmetic shift operators (<<< and >>>) work the same as
regular shift operators on unsigned numbers. 67

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 OPERATORS
SHIFT OPERATORS
➢ For signed numbers,
➢ Arithmetic shift left is same as regular shift left operator
➢ Arithmetic shift right, MSB (sign bit) copied as well as shifted right
➢ If a = 4’b1010 and b = 4’b10X0

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 OPERATORS
CONCATINATION OPERATOR
➢ A concatenation is the joining together of bits resulting from two or more expressions
➢ The concatenation is expressed using the brace characters { and }, with commas
separating the expressions within
➢ Syntax: concatenation ::= {expression, {expression }}
➢ Unsized constant numbers are not allowed in concatenations

➢ Examples: {4{w}} // This is equivalent to {w, w, w, w}

{b, {3{a, b}}} // This is equivalent to {b, a, b, a, b, a, b}

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•Example:
reg a;
reg [2:0] b, c;
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!

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 Replication Operator
❑ Replication Operator {{ }}.

❑ Repetitive concatenation of the same number can be expressed by using a

replication constant.

❑ A replication constant specifies how many times to replicate the number inside
the bracket ({}).

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 OPERATORS
CONDITIONAL OPERATOR

➢ Conditional operator has three operands separated by two operators.

➢ Syntax: <cond_expr> ? <true_expr> : <false_expr>

➢ If <cond_expr> evaluates to false, then <false_expr> is evaluated

➢ If <cond_expr> evaluates to true, then <true_expr> is evaluated

➢ Examples:
Y = (sel) ? A : B; // If sel=1 then Y=A, else Y=B
Out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); // Nested conditional operator
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 OPERATORS
OPERATORS PRECEDENCE

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MODULE-2 BECE102L-DIGITAL SYSTEM DESIGN 73

 VERILOG MODELLING
➢ Any combinational or sequential logic circuit can be realized in Verilog
HDL using one of the following four modelling approaches.
1. Behavioural modelling - Uses procedural & conditional statements,
circuit behaviour described as Truth table is known
2. Data flow modelling - Uses assignment statement and operators,
logical expression must be known
3. Gate level modelling - Uses various gate primitives, logic
diagram must be known
4. Switch level modelling - Uses various transistor level primitives,
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CMOS logic diagram must be known

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 VERILOG MODELLING

BEHAVIORAL

DATA FLOW Our focus

STRUCTURAL /
GATE LEVEL

SWITCH
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STRUCTURAL / GATE-LEVEL
MODELLING
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 STRUCTURAL MODELLING
➢ At gate level modelling, the circuit is described in terms of gates.

➢ It is possible to have a one-to-one correspondence between the logic

circuit diagram and the Verilog description.
➢ All the basic gates are available as “Primitives” in Verilog. Primitives
are generalized modules that already exist in Verilog.

➢ There are three classes of basic gate primitives.

(1). Multiple-input gates : and, or, nand, nor, xor, xnor
(2). Multiple-output gates : buffer, not
(3). Tristate gates : bufif0, bufif1, notif0, notif1 77

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STRUCTURAL MODELLING

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STRUCTURAL MODELLING

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Structural Modelling

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Structural Modelling

module example (y,a,b,c,d)

output y; /* output port declaration */
input a, b, c, d; /* input port declaration */
wire w1, w2, w3; /* internal wires declaration */
xor x1 (w1, b, c);
and a1 (w2, a, w1);
and a2 (w3, d, w1);
or o1 (y, w2, w3);
endmodule

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DATA FLOW MODELLING

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 DATA FLOW MODELLING
➢ Dataflow level description of a digital circuit is at higher level; it makes
the circuit description more compact than design through gate primitives.

➢ Dataflow modelling provides the means of describing combinational

circuits by their function rather than by their gate structure.
➢ Design implement using dataflow modelling uses a continuous
assignment statement and Verilog provides different operators to
perform a function.
➢ The assignment statement start with the keyword assign and results are
assigned to nets. 84

84
DATA FLOW MODELLING
AND GATE EXAMPLE

86

Basic 2-input AND gate (Data-flow modelling)

86
Dataflow Modelling

87
Dataflow Modelling-Examples

88
 BEHAVIOURAL
MODELLING
89

MODULE-2 BECE102L-DIGITAL SYSTEM DESIGN 89

 BEHAVIOURAL MODELLING
➢ Behavioural model enables you to describe the system at a higher level
of abstraction i.e it specifies the circuit in terms of behaviour.
➢ Behavioural modelling is done using two constructs: initial and always.
➢ Describe the behaviour of the design in terms of action & timing control.
➢ Action - How the model of our circuit should behave?
➢ Timing control - At what time do what thing & At what condition do what thing
➢ Verilog supports the following construct to model circuit behaviour
➢ Procedural block
➢ Procedural assignment statement
➢ Timing controls
➢ Block statement 90
➢ Conditional statement
 BEHAVIOURAL MODELLING
PROCEDURAL BLOCK
➢ In Verilog procedural block are the basic of behaviour modelling
➢ Describe one logic in one procedural block
➢ Procedural block types: (i) initial (ii) always
➢ All initial & always statement execute concurrently starting at time t=0
➢ A module may contain any number of initial & always statement
Type of block: initial or always
type-of-block @ (sensitivity list)
Symbol used to signifies event
begin : name-of-block; (only for always block)
local variable declaration; Specify the event which starts the execution of the block
procedural assignment statements; (only for always block)
end A block can assign a name for the block

Variables which are local to the block are defined here

This form the body of the block

91

All action within blocks are enclosed by begin-end construct

 Behavioral Model – AND gate design

module andgate(y,a,b);
input a,b;
module andgate (y,a,b); output y;
input a,b; reg y;
output y; always @(a or b)
reg y; begin
always @ (a or b) case ({a, b})
begin 2'b00: out = 0;
if (a == 1 && b == 1) 2'b01: out = 0;
y = 1; 2'b10: out = 0;
else 2'b11: out = 1;
y = 0; endcase
end end
endmodule endmodule
92
 module half_adder (sum,carry, a,b);
Behavioral Model – half Adder output sum,carry;
input a,b;
reg sum,carry;
always @ (a or b)
module half_adder (sum,carry, a,b); begin
output sum,carry; case ({a, b})
input a,b; 2'b00: begin
reg sum,carry; sum = 1'b0;
carry = 1'b0;
always @ (a or b) end
begin 2’b01: begin
if (a == 0 && b == 0) sum = 1’b1;
sum = 0; carry =0; carry = 1'b0;
end
elseif (a == 0 && b == 1) 2’b10: begin
sum = 1; carry =0; sum = 1’b1;
elseif (a == 1 && b == 0) carry = 1'b0;
sum = 1; carry =0; end
elseif (a == 1 && b == 1) 2’b11: begin
sum = 1'b0;
sum = 0; carry =1; carry = 1’b1;
end end
endmodule endcase
end
endmodule 93
 BEHAVIOURAL MODELLING
PROCEDURAL STATEMENT
➢ The assignment statement within an initial statement or always statement
is called procedural statement.

➢ It is used to assign to only a register data type such as reg, integer,

time, real, and memory.
➢ The variables will retain their values until updated by another
procedural assignment.
➢ Two types of procedural assignments are:
(i) blocking assignment
(ii) non-blocking assignment 95
Behavioural Modelling

96
 BEHAVIOURAL MODELLING
PROCEDURAL STATEMENT – BLOCKING ASSIGNMENT
➢ A blocking assignment statements are executed in the order they are
specified in a sequential block.
➢ The execution of next statement begins only after the completion of the
present blocking assignments.
➢ A blocking assignment will not block the execution of the next statement
in a parallel block.
➢ This type of assignment is majorly used in combinational circuit
modelling.
97

➢ The blocking assignments are made using the operator =.

The #10 delay depends on the timescale directive at the top of your Verilog file.

BEHAVIOURAL MODELLING
BLOCK STATEMENT – SEQUENTIAL BLOCK

Example-1: Example-2:
//Sequential block without delay // Sequential blocks with delay
reg X, Y; reg x, y;
• #10 : delay of 10 simulation time units.
reg [1:0] z, w; reg [1:0] z , w; • The #10 delay depends on the timescale
directive at the top of Verilog file.
initial initial • If timescale = 1ns , #10 means 10 ns
begin begin
x = l'b0; x = l'bo; //completes at simulation time 0
y = l‘b1; #5 y = l'bl; //completes at simulation time 5
z = {x, y}; #10 z = {x, y};//completes at simulation time 15
w = {y, x}; #20 w = {y, x); //completes at simulation time 35
end end 98
The #10 delay depends on the timescale directive at the top of your Verilog file.

BEHAVIOURAL MODELLING
NON BLOCK STATEMENT – SEQUENTIAL BLOCK

Example-1: Example-2:
//Sequential block without delay // Sequential blocks with delay
reg X, Y; reg x, y;
• #10 : delay of 10 simulation time units.
reg [1:0] z, w; reg [1:0] z , w; • The #10 delay depends on the timescale
directive at the top of Verilog file.
initial initial • If timescale = 1ns , #10 means 10 ns
begin begin
x <= l'b0; x <= l'bo; //completes at simulation time 0
y <= l‘b1; #5 y <= l'bl; //completes at simulation time 5
z <= {x, y}; #10 z <= {x, y};//completes at simulation time 10
w <= {y, x}; #20 w<= {y, x); //completes at simulation time 20
end end 99

All statements start in parallel at time 0. Hence, the block

finishes at time 20 instead of time 35.
 Determine the values of a and b ,c of below verilog program at reg a,b,c;
t=0ns,5ns,and 10 ns ,15ns ,20ns initial
Begin
reg a,b,c;
a=1
initial
b=1
Begin
c=1
a=1
a <= #5 3’d2;
b=1
b <= #5 3’d4;
c=1
c <= #10 3’d5;
a = #5 3’d2;
end
b = #5 3’d4;
c = #10 3’d5;
end Time (ns) a b C
0 1 1 1
Time (ns) a b C 5 2 4 1
0 1 1 1 10 2 4 5
5 2 1 1 15 2 4 5
10 2 4 1 20 2 4 5
15 2 4 1
20 2 4 5 100
module two_initial_blocks;
reg a, b, c;

initial begin
a = 1; // At t=0 in Verilog, if a module contains multiple initial blocks, all initial
#5 a = 2; // At t=5 blocks execute concurrently and begin execution at the same
end
simulation time (t=0ns). Each initial block runs independently,
initial begin and any delays (#) in one block do not affect the execution of
b = 1; // At t=0
#10 b = 3; // At t=10 the other blocks.
end

initial begin
c = 0; // At t=0
#15 c = 5; // At t=15
end
endmodule
TEST BENCH

102
 TEST BENCH
➢ After modelling our digital circuit using either one of the modelling, we
need to apply appropriate stimulus to the design to test it.

➢ Stimulus is nothing but the application of various permutations and

combinations of inputs at various points of time and, looking for correct
results produced by the design.

➢ This can be done by writing another Verilog code called Test Bench and
it is used to simulate your design without physical hardware.

➢ This is written as a separate file, different from the design file(s).

103
 TEST BENCH
➢ The design module is implemented using any one of the Verilog
modelling (and_gate.v), then test bench (tb_and_gate.v) is created with
possible set of inputs for which output need to be verified.
➢ To verify the design, test cases from test bench are applied to design
module and output response will be received.
module test_module_name;
//declare local reg and wire identifiers.
//instantiate the design module under test
//generate stimulus using initial and always.
// display output response
104
endmodule
 TEST BENCH – AND GATE
//TESTBENCH
module andgate_tb;
reg a,b;
Structural/Gate Level wire y;
andgate dut(y,a,b);
module andgate(y,a,b);
initial begin
input a,b;
a=0; b=0; //This is input a=0,b=0
output y;
#10;
and (y,a,b);
a=0; b=1; //This is input a=0,b=1
endmodule
#10;
a=1; b=0; //This is input a=1,b=0
#10;
a=1; b=1; //This is input a=1,b=1
#10;
end
initial begin
$monitor(“a=%b, b=%b, y=%b",a,b,y);
//if any changes in variables include inside monitor, it takes effect
// $monitor("name=%d",variable_name)
end
endmodule

105
Test Bench -Half adder-Design
// Half_adder_tb
module half_adder _tb;
reg a;
reg b;
wire sum;
wire carry;
half_adder dut (sum,carry, a,b);
initial begin
a=1'b0; b=1'b0; // This is input a=0,b=0
#10 a=1'b0; b=1'b1; // This is input a=0,b=1
#10 a=1'b1; b=1'b0; // This is input a=1,b=0
#10 a=1'b1; b=1'b1; // This is input a=1,b=1
#10 $stop;
end
initial begin
$monitor($time, "a=%b, b=%b, sum=%b,carry=%b", a,b,sum,carry);
end
endmodule

106
module test_bench();
reg A, B, C;
wire SUM, CARRY;
integer i;
FullAdder dut (SUM, CARRY, A, B, C);
initial begin
for (i = 0; i < 8; i = i + 1)
begin
{A, B, C} = i; // Assign binary value of i to inputs
#10; // Wait for 10 time units
end
end
// Monitor and display outputs
initial begin
$monitor($time, " A = %b, B = %b, C = %b, SUM = %b,
CARRY = %b", A, B, C, SUM, CARRY);
#60 $finish; // End simulation after 60 time units
end
endmodule

107