VLSI DESIGN LAB 2025
Experiment-10
Aim: Consider two inputs of 8-bit and 3-bit sequences I1, SEQ respectively. Develop a verilog
code in Vivado to count the detection of SEQ sequence in I1. For the
a) Non-Overlapping case
b) Overlapping case
c) Program the codes in Basys3 board, take I1 and SEQ from the switches and show the outputs
on LEDs.
Apparatus: Vivado Software, Basys3 FPGA board and USB to C type cable
Verilog Code:
1. Non-Overlapping case:
module Sequence_Detector_Non_Overlapping(
input [7:0] I1,
input [2:0] SEQ,
output reg [2:0] count
);
integer i;
reg [2:0] temp;
always @(*) begin
count = 0;
i = 0;
// Check position 0
if (I1[7:5] == SEQ) begin
count = count + 1;
i = 3; // Move to position 3
end else begin
i = 1; // Move to position 1
end
// Check position 1
if (i == 1) begin
if (I1[6:4] == SEQ) begin
count = count + 1;
i = 4; // Move to position 4
end else begin
U22EC070 Page 162
VLSI DESIGN LAB 2025
i = 2; // Move to position 2
end
end
// Check position 2
if (i == 2) begin
if (I1[5:3] == SEQ) begin
count = count + 1;
i = 5; // Move to position 5
end else begin
i = 3; // Move to position 3
end
end
// Check position 3
if (i == 3) begin
if (I1[4:2] == SEQ) begin
count = count + 1;
i = 6; // Move out of bounds
end else begin
i = 4; // Move to position 4
end
end
// Check position 4
if (i == 4) begin
if (I1[3:1] == SEQ) begin
count = count + 1;
i = 7; // Move out of bounds
end else begin
i = 5; // Move to position 5
end
end
// Check position 5
if (i == 5) begin
if (I1[2:0] == SEQ) begin
count = count + 1;
end
end
U22EC070 Page 163
VLSI DESIGN LAB 2025
end
endmodule
2. Overlapping case:
module Sequence_Detector_Overlapping(
input [7:0] I1,
input [2:0] SEQ,
output reg [2:0] count
);
integer i;
reg [2:0] temp;
always @(*) begin
count = 0;
for (i = 0; i <= 5; i = i + 1) begin
temp = I1[7 - i -: 3]; // Extract 3 bits
if (temp == SEQ) begin
count = count + 1;
end
end
end
endmodule
[Link] file:
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {I1[0]}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {I1[1]}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {I1[2]}]
set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {I1[3]}]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {I1[4]}]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {I1[5]}]
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {I1[6]}]
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {I1[7]}]
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {SEQ[0]}]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {SEQ[1]}]
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {SEQ[2]}]
U22EC070 Page 164
VLSI DESIGN LAB 2025
## LEDs
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports
{count[0]}]
set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports
{count[1]}]
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports
{count[2]}]
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
## SPI configuration mode options for QSPI boot, can be used for all designs
set_property [Link] TRUE [current_design]
set_property [Link] 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
Outputs:
1. Non-Overlapping case:
a. I1=11111111, SEQ=111, count=010:
U22EC070 Page 165
VLSI DESIGN LAB 2025
b. I1=10001001, SEQ=100, count=010:
c. I1=10101010, SEQ=101, count=010:
U22EC070 Page 166
VLSI DESIGN LAB 2025
2. Overlapping case:
a. I1=11010011, SEQ=101, count=001:
b. I1=11111111, SEQ=111, count=110:
U22EC070 Page 167
VLSI DESIGN LAB 2025
c. I1=10101010, SEQ=101, count=011:
Conclusion:
This experiment demonstrates the implementation of sequence detection in digital systems using
Verilog. It highlights the difference between overlapping and non-overlapping sequence
detection, where the latter skips the detected pattern entirely, while the former advances by just
one bit. The FPGA-based implementation allows students to observe real-time sequence
detection through user-controlled inputs and visual LED feedback. The finite state machine
design showcases a practical application of sequential logic circuits fundamental to digital
systems design.
SIGNATURE
U22EC070 Page 168
VLSI DESIGN LAB 2025
Experiment-11
Aim: Implement 6-T SRAM in Cadence Virtuoso and a) Simulate the half circuit for read
operation for the static characteristic (VTC) obtain optimum noise margin. b) Simulate the half
circuit for write operation for the static characteristic (VTC) obtain optimum noise margin. c)
Validate your design for cell ratio (CR) and pull-up ratio (PR).
Apparatus: Cadence Virtuoso Software
Schematic:
6T SRAM:
Half circuit for size calculation:
U22EC070 Page 169
VLSI DESIGN LAB 2025
Cell ratio estimation:
Pull-up ratio estimation:
NMOS sizing:
U22EC070 Page 170
VLSI DESIGN LAB 2025
PMOS sizing:
Read Static Noise Margin calculation:
Write Static Noise Margin calculation:
U22EC070 Page 171
VLSI DESIGN LAB 2025
Calculations:
Conclusion:
SIGNATURE
U22EC070 Page 172
VLSI DESIGN LAB 2025
Experiment-12
Aim: Verilog implementation of 4 bit Full Adder from the concept of control path and data path.
Apparatus: Vivado Software
Code:
module top(
input ip_clk,
input ip_rst_n,
input [1:0] cmd,
input [7:0] op_1,
input [7:0] op_2,
input carry_in,
output [7:0] out,
output carry_out
);
wire [7:0] op_1_w, op_2_w, out_w;
wire carry_in_w, carry_out_w, load, execute, store;
control_unit control(
.ip_clk(ip_clk),
.ip_rst_n(ip_rst_n),
.cmd(cmd),
.load(load),
.execute(execute),
.store(store)
);
register ip_reg_1(
.ip_clk(ip_clk),
.load(load),
.data_in(op_1),
.data_out(op_1_w)
);
register ip_reg_2(
.ip_clk(ip_clk),
.load(load),
U22EC070 Page 173
VLSI DESIGN LAB 2025
.data_in(op_2),
.data_out(op_2_w)
);
reg_1bit ip_carry(
.ip_clk(ip_clk),
.load(load),
.data_in(carry_in),
.data_out(carry_in_w)
);
adder adder_unit(
.ip_clk(ip_clk),
.execute(execute),
.op_1(op_1_w),
.op_2(op_2_w),
.carry_in(carry_in_w),
.out(out_w),
.carry_out(carry_out_w)
);
register op_reg(
.ip_clk(ip_clk),
.load(store),
.data_in(out_w),
.data_out(out)
);
reg_1bit op_carry(
.ip_clk(ip_clk),
.load(store),
.data_in(carry_out_w),
.data_out(carry_out)
);
endmodule
U22EC070 Page 174
VLSI DESIGN LAB 2025
module control_unit(
input ip_clk,
input ip_rst_n,
input [1:0] cmd,
output reg load,
output reg execute,
output reg store
);
always@(posedge ip_clk) begin
if(!ip_rst_n) begin
load <= 0;
execute <= 0;
store <= 0;
end
else begin
case(cmd)
2'b00: begin
load <= 0;
execute <= 0;
store <= 0;
end
2'b01: begin
load <= 1;
execute <= 0;
store <= 0;
end
2'b10: begin
load <= 0;
execute <= 1;
store <= 0;
end
2'b11: begin
load <= 0;
execute <= 0;
store <= 1;
end
endcase
end
end
U22EC070 Page 175
VLSI DESIGN LAB 2025
endmodule
module register(
input ip_clk,
input load,
input [7:0] data_in,
output reg [7:0] data_out
);
always@(posedge ip_clk) begin
if(load) begin
data_out <= data_in;
end
end
endmodule
module reg_1bit(
input ip_clk,
input load,
input data_in,
output reg data_out
);
always@(posedge ip_clk) begin
if(load) begin
data_out <= data_in;
end
end
endmodule
module adder(
input ip_clk,
input [7:0] op_1,
input [7:0] op_2,
input carry_in,
input execute,
output reg [7:0] out,
output reg carry_out
);
U22EC070 Page 176
VLSI DESIGN LAB 2025
always@(posedge ip_clk) begin
if(execute) begin
{carry_out, out} <= op_1 + op_2 + carry_in;
end
end
endmodule
Testbench:
`timescale 1ns/1ps
module top_tb();
// Define the test parameters
parameter CLK_PERIOD = 10; // 10ns clock period (100MHz)
parameter SIM_TIME = 1000; // Simulation time in clock cycles
// Define the DUT signals
reg ip_clk;
reg ip_rst_n;
reg [1:0] cmd;
reg [7:0] op_1;
reg [7:0] op_2;
reg carry_in;
wire [7:0] out;
wire carry_out;
// Instantiate the DUT
top DUT (
.ip_clk(ip_clk),
.ip_rst_n(ip_rst_n),
.cmd(cmd),
.op_1(op_1),
.op_2(op_2),
.carry_in(carry_in),
.out(out),
.carry_out(carry_out)
);
// Clock generation
initial begin
ip_clk = 0;
U22EC070 Page 177
VLSI DESIGN LAB 2025
forever #(CLK_PERIOD/2) ip_clk = ~ip_clk;
end
// Define command values (these should be adjusted according to your control_unit's actual
implementation)
localparam CMD_IDLE = 2'b00;
localparam CMD_LOAD = 2'b01;
localparam CMD_EXECUTE = 2'b10;
localparam CMD_STORE = 2'b11;
// Test vectors
integer i;
reg [7:0] expected_out;
reg expected_carry;
// Test procedure
initial begin
// Initialize inputs
ip_rst_n = 0;
cmd = CMD_IDLE;
op_1 = 0;
op_2 = 0;
carry_in = 0;
// Apply reset
#(CLK_PERIOD*2);
ip_rst_n = 1;
#(CLK_PERIOD);
// Test case 1: Simple addition without carry
$display("Test Case 1: 25 + 17 without initial carry");
op_1 = 8'd25;
op_2 = 8'd17;
carry_in = 1'b0;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Execute addition
U22EC070 Page 178
VLSI DESIGN LAB 2025
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
// Store result
cmd = CMD_STORE;
#(CLK_PERIOD);
// Check result
expected_out = 8'd42;
expected_carry = 1'b0;
if (out !== expected_out || carry_out !== expected_carry) begin
$display("ERROR: Test Case 1 failed!");
$display("Expected out = %d, carry_out = %b", expected_out, expected_carry);
$display("Got out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Test Case 1 passed: out = %d, carry_out = %b", out, carry_out);
end
// Test case 2: Addition with overflow/carry
$display("Test Case 2: 200 + 100 (with overflow)");
op_1 = 8'd200;
op_2 = 8'd100;
carry_in = 1'b0;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Execute addition
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
// Store result
cmd = CMD_STORE;
#(CLK_PERIOD);
// Check result (200 + 100 = 300, which overflows 8 bits to 44 with carry)
expected_out = 8'd44; // 300 % 256 = 44
expected_carry = 1'b1;
if (out !== expected_out || carry_out !== expected_carry) begin
U22EC070 Page 179
VLSI DESIGN LAB 2025
$display("ERROR: Test Case 2 failed!");
$display("Expected out = %d, carry_out = %b", expected_out, expected_carry);
$display("Got out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Test Case 2 passed: out = %d, carry_out = %b", out, carry_out);
end
// Test case 3: Addition with input carry
$display("Test Case 3: 10 + 20 with input carry");
op_1 = 8'd10;
op_2 = 8'd20;
carry_in = 1'b1;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Execute addition
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
// Store result
cmd = CMD_STORE;
#(CLK_PERIOD);
// Check result (10 + 20 + 1 = 31)
expected_out = 8'd31;
expected_carry = 1'b0;
if (out !== expected_out || carry_out !== expected_carry) begin
$display("ERROR: Test Case 3 failed!");
$display("Expected out = %d, carry_out = %b", expected_out, expected_carry);
$display("Got out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Test Case 3 passed: out = %d, carry_out = %b", out, carry_out);
end
// Test case 4: Check reset functionality
$display("Test Case 4: Testing reset");
// First load some values
U22EC070 Page 180
VLSI DESIGN LAB 2025
op_1 = 8'd123;
op_2 = 8'd45;
carry_in = 1'b1;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Apply reset
ip_rst_n = 0;
#(CLK_PERIOD*2);
// Release reset
ip_rst_n = 1;
#(CLK_PERIOD);
// Execute and store (should not produce the expected result since reset was applied)
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
cmd = CMD_STORE;
#(CLK_PERIOD);
// For this test, we need to know the reset behavior of your design
// Assuming the reset state has output and carry_out set to 0
expected_out = 8'd0;
expected_carry = 1'b0;
if (out !== expected_out || carry_out !== expected_carry) begin
$display("NOTE: Reset behavior might differ from expected. Actual behavior:");
$display("out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Test Case 4 passed: Reset correctly sets outputs to zero");
end
// Test case 5: Random test cases
$display("Test Case 5: Random addition tests");
for (i = 0; i < 10; i++) begin
op_1 = $random & 8'hFF;
op_2 = $random & 8'hFF;
carry_in = $random & 1'b1;
U22EC070 Page 181
VLSI DESIGN LAB 2025
// Calculate expected results
{expected_carry, expected_out} = op_1 + op_2 + carry_in;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Execute addition
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
// Store result
cmd = CMD_STORE;
#(CLK_PERIOD);
// Check result
if (out !== expected_out || carry_out !== expected_carry) begin
$display("ERROR: Random Test %0d failed!", i);
$display("Inputs: op_1 = %d, op_2 = %d, carry_in = %b", op_1, op_2, carry_in);
$display("Expected out = %d, carry_out = %b", expected_out, expected_carry);
$display("Got out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Random Test %0d passed: %d + %d + %b = %d with carry %b",
i, op_1, op_2, carry_in, out, carry_out);
end
end
// Test case 6: Command sequence test (Idle states in between)
$display("Test Case 6: Testing with idle states between commands");
op_1 = 8'd75;
op_2 = 8'd50;
carry_in = 1'b0;
// Load values
cmd = CMD_LOAD;
#(CLK_PERIOD);
// Idle
cmd = CMD_IDLE;
#(CLK_PERIOD*2);
U22EC070 Page 182
VLSI DESIGN LAB 2025
// Execute
cmd = CMD_EXECUTE;
#(CLK_PERIOD);
// Idle
cmd = CMD_IDLE;
#(CLK_PERIOD*2);
// Store
cmd = CMD_STORE;
#(CLK_PERIOD);
// Check result
expected_out = 8'd125;
expected_carry = 1'b0;
if (out !== expected_out || carry_out !== expected_carry) begin
$display("ERROR: Test Case 6 failed!");
$display("Expected out = %d, carry_out = %b", expected_out, expected_carry);
$display("Got out = %d, carry_out = %b", out, carry_out);
end else begin
$display("Test Case 6 passed: out = %d, carry_out = %b", out, carry_out);
end
// End simulation
$display("All test cases completed!");
#(CLK_PERIOD*5);
$finish;
end
// Optional: Dump waveform file for viewing in a waveform viewer
initial begin
$dumpfile("top_tb.vcd");
$dumpvars(0, top_tb);
end
endmodule
U22EC070 Page 183
VLSI DESIGN LAB 2025
Outputs:
Simulation:
RTL schematic:
Synthesis design:
U22EC070 Page 184
VLSI DESIGN LAB 2025
Implementation schematic:
Synthesis Power:
Implementation Power:
U22EC070 Page 185
VLSI DESIGN LAB 2025
Synthesis Utilization:
Conclusion:
SIGNATURE
U22EC070 Page 186