8086 Microprocessor

Overview
First 16 - bit processor released by Addressable memory space is
INTEL in the year 1978 organized in to two banks of 512 KB
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
Originally HMOS, now manufactured select even bank and control signal 𝐁𝐇𝐄
using HMOS III technique is used to access odd bank

Uses 16 bit data bus.

Approximately 29, 000 transistors, 40
pin DIP, 5V supply Operates in two modes: minimum mode
and maximum mode, decided by the
signal at MN and 𝐌𝐗 pins.
Does not have internal clock; external
asymmetric clock source with 33% It has 20,000 instructions
duty cycle It supports multiplication and division

20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.

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8086 Microprocessor
Common signals

Pins and Signals AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address (ALE=1) the symbol A is
used instead of AD, for example A0-A15.

When data are transmitted (ALE=0)over

AD lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

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8086 Microprocessor
Common signals

Pins and Signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable the transfer of data

over higher order bus D8-D15. It is
multiplexed with status signal S7.

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8086 Microprocessor
Common signals

Pins and Signals

BM=Bus Master

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8086 Microprocessor
Common signals

Pins and Signals

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8086 Microprocessor
Common signals

Pins and Signals

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.

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8086 Microprocessor
Common signals

Pins and Signals TEST

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’

instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
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The signal is active high.
 8086 Microprocessor
Common signals

Pins and Signals

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

The 8086 does not have on-chip clock

generation circuit. Hence the clock
generator chip, 8284 is connected to the
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CLK pin of 8086.
8086 Microprocessor

Clock Pin

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8086 Microprocessor
Common signals

Pins and Signals RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized.

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8086 Microprocessor
Min/ Max Pins

Pins and Signals

The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

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8086 Microprocessor
Minimum mode signals

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
𝐃𝐄𝐍 (Data Enable) DT/ R̅ is an output control signal to
control the direction of data flow on the data bus
through an external bidirectional transceiver.

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
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8086 Microprocessor

Pins and Signals

Minimum mode signals

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DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.
 8086 Microprocessor
Minimum mode signals

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor from the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

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8086 Microprocessor
Maximum mode signals

Pins and Signals During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

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8086 Microprocessor
Maximum mode signals

Pins and Signals During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

 These signals provide the status of instruction queue. 18

8086 Microprocessor
Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

Pins and Signals grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏

𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

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