Basic Electronics
Engineering
(Spring 2024)
Resources of PPT:
[Link]
Digital Design, 4th Edition
M. Morris Mano and Michael D. Ciletti
Sequential Circuit
A sequential circuit is one whose output depends upon both present and past inputs.
Sequential Circuit
Sequential Circuit
Sequential Circuit: Latches
Latches are digital circuits that store a single bit of information and hold its value until it is updated by new
input signals. The latches have low and high two stable states. Due to these states, latches also refer to
as bistable-multivibrators.
S-R Type Latch:
S-R (Set-Reset) Latches: S-R latches are the simplest form of latches and are implemented using two
inputs: S (Set) and R (Reset). The S input sets the output to 1, while the R input resets the output to 0.
When both S and R are at 1, the latch is said to be in an “undefined” state.
Under normal conditions, both the input remains 0.
Sequential Circuit: Latches
Sequential Circuit: Latches
Sequential Circuit: Latches
Sequential Circuit: Latches
Forbidden State!
Sequential Circuit: Latches
Sequential Circuit: Latches
D Latch:
Sequential Circuit: Latches
JK Latch
The JK Latch is the same as the SR Latch. In JK latch, the unclear states are removed, and the output is
toggled when the JK inputs are high. The only difference between SR latch JK latches is that there is no output
feedback towards the inputs in the SR latch, but it is present in the JK latch.
Sequential Circuit: Latches
T Latch
The T latch forms by shorting the JK latch inputs. The output of the T latch toggle when the input set
to 1 or high.
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Sequential Circuit: Flipflop
Conversion of D-Flipflop to T-Flipflop
Step 1: Consider the following characteristic table of T flip-flop.
Step 2:
We know that D flip-flop has single input D. So,
write down the excitation values of D flip-flop for
each combination of present state and next
state values. The following table shows the
characteristic table of T flip-flop along with
the excitation input of D flip-flop.
𝐷 = 𝑇 ′ 𝑄(𝑡) + 𝑇𝑄′ (𝑡) = 𝑇 ⊕ 𝑄(𝑡)
Further resource:
[Link]
onversion_of_flip_flops.htm
Sequential Circuit: Register
Shift Register:
Serial Input Serial Output
Serial Input Parallel Output
Parallel Input Serial Output
Parallel Input Parallel Output
Serial Input Serial Output Register
Serial Input Serial Output Register
Serial Input Serial Output Register
Serial Input Parallel Output Register
Parallel Input Parallel Output Register
Parallel Input Serial Output Register
Source: [Link]
Asynchronous Counter
Asynchronous Counter
Negative Edge Triggered
Clock frequency in both FFs are not same Asynchronous Counter
Asynchronous Counter
Asynchronous Counter
Asynchronous Counter
Total number of states to count: 4
Source:
[Link]
ex=179
Asynchronous Counter
In synchronous: Clock frequency is same for all flipflops.
In asynchronous: Clock frequency is different for each flipflop.
Asynchronous Counter
Asynchronous Up Counter
Source:
[Link]
x=180
Asynchronous Up Counter
Timing Diagram/ Clock Diagram:
Asynchronous Up Counter
Truth Table Based on the Timing Diagram/ Clock Diagram:
Asynchronous Down Counter
Method 1: Down Counter
Up Counter Output is taken from 𝑸’
Output is taken from 𝑸 Clock signal is taken from 𝑸
Clock signal is taken from 𝑸
Method 2: Down Counter
Output is taken from Q
Clock signal is taken from 𝑸’
Asynchronous Down Counter
Up Counter
Method 1: Down Counter
Source:
[Link]
x=182
Asynchronous Mod Counter
No. of bits: n
Modulus (Mod) number: 2𝑛
Design an Mod-6 Counter:
No. of states: 6
Maximum count: 6-1=5
Lowest order Bit number ?
22 < 6 < 23
𝑛=3
Asynchronous Mod Counter
Asynchronous Mod Counter
Asynchronous Mod Counter
2-bit Synchronous Up Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip flop so output changes in parallel. The one
advantage of synchronous counter over asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does not have
cumulative delay because of same clock is given to each flip flop. It is also called as parallel counter.
3-Bit Synchronous Down Counter
Design : The steps involves in design are
1. Decide the number of Flip flops –
2. Write excitation table of FF –
3. Draw State diagram and circuit excitation table –
3-Bit Synchronous Down Counter
Here T = 1, then there is output state(next state changes from
previous state) changes i.e Q changes from 0 to 1 or 1 to 0
T= 0 then, there is no state output state changes i.e Q remains
same
4. Find simplified equation using k map –
3-Bit Synchronous Down Counter
Source: [Link]
4-Bit Synchronous Counter
From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Source: [Link]