Organization of 8085 microprocessor

– Mrs. Rama M. Warang

Features of 8085 chip is available in 40 pin plastic ceramic DIP package.

microprocessor It is an 8 bit microprocessor

8085 : It has 8-bit data bus width which indicates that 1 byte of
data can be passed on this bus.
It has 16 bit address bus that means it can address a physical memory
of 216 = 64 kilo bytes.
Address bus is divided into two groups :
• The least significant 8 bits of address bus are transferred on same
eight lines of the data bus .Such bus is called as multiplexed bus.
• Most significant 8 bits of address are transmitted on address bus.

To select external memory or I/O devices, microprocessor 8085 uses

I/O mapped I/O system.
To communicate with external devices, microprocessor 8085 uses
interrupt method(Hardware interrupt).

The microprocessor requires +5V single power supply and can

operate with 3MHz single-phase clock.
Pin Diagram
of
Microprocessor
8085
 • These are crystal clock input signals which drives the internal
circuitry of the microprocessor.
• It produces a suitable dock for the operation of
X1,X2 microprocessor.
• The frequency is internally divided by two, so the crystal
should operate twice the operating frequency.
• The operating frequency range of 8085 is 500 KHz to 3MHz.

• The whole circuitry is synchronized with chock.

CLK OUT • The speed of the system depends on the clock frequency.

• When the input signal on this pin goes low, the program
counter is set to 0000H
Reset in • The microprocessor unit is held in reset condition a long as
RESET is applied.
 • It is active high output signal which indicates that the MPU is
Reset out being reset.
• It is connected to peripherals to reset them when MPU is reset.

• SOD is Serial Output Data line.

SOD • The 7th bit of the accumulator is outputted on SOD line when
SIM instruction is executed.

• SID is Serial Input Data line.

• The data on the SID line will be inputted to 7 bit of the
th
SID accumulator when RIM instruction is executed.
 • This input signal is used to interrupt the microprocessor.
• It has the highest priority among all other interrupts.
• It is a non-maskable interrupt.
TRAP • When this interrupt is recognized, the next instruction is
executed from a fixed memory location i.e., 4.5*8=0024H. So,
it is vectored interrupt.
• RESTART INTERRUPT 7.5 input signal is used to interrupt
the microprocessor.
• It is a maskable interrupt
RST 7.5 • When this interrupt is recognized, the next instruction is
executed from a fixed memory location i.e., 7.5*8=003CH. So,
it is vectored interrupt.
• RESTART INTERRUPT 6.5 input signal is used to interrupt
the microprocessor.
RST 6.5 • It is a maskable interrupt
• When this interrupt is recognized, the next instruction is
executed from a fixed memory location i.e., 6.5*8=0034H. So,
it is vectored interrupt.
 • RESTART INTERRUPT 5.5 input signal is used to interrupt
the microprocessor.
• It is a maskable interrupt
RST 5.5 • When this interrupt is recognized, the next instruction is
executed from a fixed memory location i.e., 5.5*8=002CH. So,
it is vectored interrupt.

• This input signal is used to interrupt the microprocessor.

• It has the lowest priority among all other interrupts.
INTR • It is a maskable interrupt
• When this interrupt is recognized, the address of the next
instruction to be executed depends on the instruction. So, it is
non-vectored interrupt.

• It is an active low output signal.

INTA • A low on this pin indicates that processor has acknowledged
an INTR interrupt.
 • The signal lines AD0 to AD7 are bidirectional. They serve a dual
purpose. They are used as the low-order address bus as well as
the data bus.
AD0-AD7 • In executing an instruction, during the earlier part of the cycle,
these lines are used as the low-order address bus. During later
part of the cycle, these lines are used as the data bus.
• The eight signal lines (A8-A15) which are unidirectional and used
as the high-order address bus.
• The most significant bits (A8-A15) of the address bus are
A8-A15 separate. The least significant bits (A0-A7) are multiplexed with
the bits of the bidirectional data bus (D0-D7).
• It is an input signal used by microprocessor to sense whether a
peripheral is ready to transfer data or not.
• If READY is high, the peripheral is ready. If it is low, the
READY microprocessor waits for an internal number of clock cycles until
it goes high.
• It is used to synchronize slower peripheral to faster
microprocessor.
 • ALE is Address Latch Enable. This is special output signal to
indicate the beginning of the operation.
ALE • When it is high during first clock cycle of machine state, it
indicates that bits on AD0-AD7 are address bits.
• Later on, when it is low, AD0-AD7 changes over to data bus.

• It is active low read control signal.

RD • This signal indicates that selected I/O or memory device is to
be read and data is available on data bus.

• This is active low write control signal.

WR • This signal indicates that the data available on data bus is to
be written into selected I/O or memory device.
 • These are status signals sent by microprocessor to distinguish
the various operations or type of machine cycle in progress.
• Status Code for Intel 8085 is :

S0,S1 S1 S0 Operations
0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH

• It is a status signal indicates whether the address bus is for I/O

device or for memory
IO/M • When it goes high, the address on the address bus is referring
I/O device and when it goes low, the address on the address
bus is referring memory.
 • This input signal indicates that a peripheral such as DMA
(Direct Memory Access) controller is requesting the access of
address and data buses.
HOLD • Having received a HOLD request, the microprocessor releases
the use of the buses as soon as the current machine cycle is
completed.

• This output signal is for HOLD ACKNOWLEDGEMENT.

• A HLDA signal indicates to a peripheral that a HOLD request
HLDA has been received and that the microprocessor will relinquish
control of buses in the next clock cycle.
 M U LT I P L E X E D A D D R E S S / D ATA B U S I N M I C R O P R O C E S S O R

1. Microprocessor 8085 has 8-bit data bus and 16-bit address bus.

2. The least significant 8-bits of address bus are passed on the same eight lines as that of
data bus i.e. on the signal lines AD7-AD0. Hence, these signal lines are bi-directional.

3. They are used for dual purpose for lower order 8-bit of address and as well as 8-bit of
data. This is known as multiplexing and such bus is known as multiplexed bus.

4. To multiplexed means, first to select one and then other. In executing an instruction,
during earlier part of cycle, these lines are used as the lower order address bus. During
later part of cycle, these lines are used as data bus.

5. The 8085 has a special signal called ALE(Address Latch Enable) for informing the
peripheral when address/data bus is sending address and when it is sending data.

6. If signal of pin ALE is high(1), then the bits on AD0-AD7 are address bits else they are
data bits.
 A D D R E S S & D ATA B U S S T R U C T U R E O F 8 0 8 5
1. With added functions of the 8085, one 40 pin DIP did not have enough pins for all the
inputs and outputs.

2. Manufacturer uses pins 12 to 19 as dual purpose address/data bus lines (AD0-AD7). The
unit is said to have an 8-bit multiplexed address/data bus.

3. The least significant 8 address lines share pins with the 8 data bus lines.

4. To multiplexed means to first select one and then another. Multiplexed address/data bus
means to first use the bus to send the address and next to send or receive data with
same bus.

5. The 8085 have special signal ALE for informing peripherals when the address/data bus
sending on address and when the it is sending data.

6. During the first cycle, the address is sent out. The lower 8-bits are latched into the
peripherals by the Address Latch Enable. During the rest of the machine cycle the data
bus is used memory or I/O data.
D E M U LT I P L E X I N G O F A D D R E S S & D ATA B U S O F 8 0 8 5
 ADDRESSING I/O DEVICES

Microprocessor is connected to various other devices such as memory and I/O

devices. There are two schemes by which these devices are addressed :

01 Memory mapped I/O Scheme :

1. In memory mapped I/O scheme, whenever an address appearing on address
bus is for an I/O device, then there is no other information on corresponding
memory location.
2. e.g. Address is 0002 is for output device and whenever this address appears
on address bus and is to be used to select output device, there is no
information on memory location 0002.
3. When an address is used to select I/O device, then that address is not used
for any memory location.
 02 I/O mapped I/O Scheme : Status Signals Machine
IO/M S1 S0 Cycle Status
1. In I/O mapped I/O, same address may be 0 0 1 Memory write
used for I/O devices as well as memory.
Microprocessor 8085 uses I/O mapped I/O 0 1 0 Memory used

scheme to address I/O devices. 1 0 1 I/O write

2. Using status signal IO/M, differentiation 1 0 I/O read
1
between I/O and memory is done .
3. When the signal is IO/M high, the address on 0 1 1 Opcode fetch

the address bus is for an I/O device and 1 1 1 Interrupt acknowledge

when it is low, the address on the address Floating 0 0 Halt
bus is for a memory location.
4. The instruction IN and OUT are used to
Floating unused unused Hold

address I/O devices. Floating unused unused Reset

5. The various operations to be carried out are

identified by using status signals S0 and S1:
 INTERRUPTS
1. An interrupt is a subroutine called, initiated by 6. Hardware interrupts are less
external device through hardware (hardware priority than software interrupts.
interrupt) or microprocessor itself (software They are non-maskable and
interrupt). maskable. Also they are
2. It can be viewed as signal, which suspends the vectored and non-vectored.
normal sequence of microprocessor (main
program)and then the microprocessor gives
service to the device which had given the signal.
After completing the service (ISR), microprocessor
again returns to the main program.
3. Microprocessor is connected to different
peripheral devices. To communicate with them,
microprocessor uses interrupt method.
4. Microprocessor 8085 has 2 types of interrupts
Software interrupts and Hardware interrupts
5. Software interrupts have more priority than
hardware interrupts. They are all non-maskable
and vectored.
 S O F T WA R E I N T E R R U P T S O F 8 0 8 5 M I C R O P R O C E S S O R
1. The normal operation of a microprocessor can be
interrupted by special instruction. Such an
interrupt is called software interrupt.
2. 8085 microprocessor provides 8 software
interrupts RST 0 to RST 7.
3. These interrupts are non-maskable i.e., they cannot
be disabled or ignored. Hence, they have higher
priority than hardware interrupts.
4. These interrupts are vectored and when these
interrupts are called, the control is transferred to a
specific memory location.
5. After execution of these interrupts, program
counter (PC) gets incremented.
6. Microprocessor does not execute any interrupt
acknowledge cycle.
7. They are not used to interface peripherals and
hence they do not improve the throughput of the
system.
 H A R D WA R E I N T E R R U P T S O F 8 0 8 5 M I C R O P R O C E S S O R
1. The normal operation of a microprocessor can be
interrupted by external device. Such an interrupt is
called hardware interrupt.
2. 8085 microprocessor provides 5 hardware interrupts
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
3. The priority decreases from TRAP to INTR.
4. TRAP is non-maskable i.e., it cannot be disabled or
ignored while others are maskable.
5. INTR is non-vectored while others are vectored i.e.,
the control is transferred to a specific memory
location.
6. After execution of these interrupts, program counter
(PC) is not incremented.
7. Microprocessor executes an interrupt acknowledge
cycle.
8. They are used to interface peripherals and hence
they improve the throughput of the system
 S O F T WA R E I N T E R R U P T S H A R D WA R E I N T E R R U P T S

1. These interrupts are not requested by 1. These interrupts are requested by

external device but by microprocessor external device.
itself.
2. After execution of these interrupts, 2. After execution of these interrupts,
program counter is incremented. program counter is not incremented.
3. Microprocessor does not execute 3. Microprocessor executes interrupt
interrupt acknowledge cycle. acknowledge cycle.
4. These are all non-makable interrupts. 4. These are non-maskable and maskable
interrupts.
5. They have higher priority than hardware 5. They have lower priority than software
interrupts. interrupts.
6. They do not improve the throughput of 6. They improve the throughput of the
the system. system.
7. They do not affect interrupt control logic. 7. They affect interrupt control logic.
8. They are not used to handle 8. They are used to handle asynchronous
asynchronous events. events.
 NON-MASKABLE INTERRUPTS MASKABLE INTERRUPTS

1. They cannot be masked or cannot be 1. They can be masked or can be kept

kept pending. pending.

2. They disable all maskable interrupts. 2. They cannot disable any non-maskable
interrupt.

3. They have higher priority than 3. They have lower priority than non-
maskable interrupts. maskable interrupts.

4. They are always vectored interrupt. 4. They can be vectored or non-vectored

interrupt.

5. Response time is low. 5. Response time is high.

FUNCTIONAL BLOCK D IAGR AM OF 8085 MICROPROCESSOR
PROGRAMMING MODEL OF 8085 MICROPROCESSOR /
R E G I S T E R A R R AY O F 8 0 8 5 M I C R O P R O C E S S O R
• 8085 Microprocessor uses both 8-bit and 16-bit registers.
• It has 8 addressable 8-bit registers out of 6 can be used as 8-bit registers or
16-bit register pairs.
• In addition, it contains 2 more 16-bit registers.

8085 registers are as follows:

➢ Accumulator- 8-bit register used to store data and result of any arithmetic
and logic operation.
➢ Flag register- 8-bit register out of which 5-bits are used as 1-bit flags to
store CPU status information.
➢ General purpose registers- They can be used as six 8-bit registers
(B,C,D,E,H,L) or three 16-bit registers(BC,DE,HL). HL register pair is normally
used for address pointing. B,C,D,E are normally used as general purpose
data registers and sometimes if used as BC, DE register pairs for address
pointing.
➢ Program Counter- 16-bit register which contains the address of the next
executable instruction.
➢ Stack Pointer- 16-bit register which contains the address of the top of the
memory location stack.
 TIMING DIAGRAM OF 8085 MICROPROCESSOR

➢ Instruction cycle : An instruction cycle is defined

as the time required to complete the execution
of an instruction. 8085 instruction cycle
contains 1-5 Machine cycles.

➢ Machine cycle : A machine cycle is defined as

the time required to complete any operation of
either accessing memory or I/O device which is
a subpart of instruction. 8085 machine cycle
contains 3-6 T-states.

➢ T-state : T-state is defined as the sub-division of

an operation which is performed in one clock
cycle.
FL AG R EGISTER OF 8085 MICROPROCESSOR
Example of Flag register being affected by result of operation in ALU
PROBLEMS ON FL AG R EGISTER OF 8085 MICROPROCESSOR

1. The flag register of 8085 microprocessor contains 45H. Interpret its

meaning.
Flag D7 D6 D5 D4 D3 D2 D1 D0
Register S Z - AC - P - CY
45H 0 1 0 0 0 1 0 1

i. Sign flag – It is reset. This means that MSB of result in accumulator is reset
and hence result is positive.
ii. Zero flag – It is set. This means that result is zero after an arithmetic or
logic operation.
iii. Auxiliary carry flag – It is reset. This means that there is no carry generated
from D3 bit to D4 bit in accumulator during arithmetic operation.
iv. Parity flag – It is set. This means that result in accumulator contains even
number(0) of 1’s.
v. Carry flag – It is set. This means that there is a carry generated from D7 bit
in accumulator during arithmetic operation.
PROBLEMS ON FL AG R EGISTER OF 8085 MICROPROCESSOR

1. The flag register of 8085 microprocessor contains 96H. Interpret its

meaning.
Flag D7 D6 D5 D4 D3 D2 D1 D0
Register S Z - AC - P - CY
95H 1 0 0 1 0 1 1 0

i. Sign flag – It is set. This means that MSB of result in accumulator is set and
hence result is negative.
ii. Zero flag – It is reset. This means that result is non-zero after an arithmetic
or logic operation.
iii. Auxiliary carry flag – It is set. This means that there is a carry generated
from D3 bit to D4 bit in accumulator during arithmetic operation.
iv. Parity flag – It is set. This means that result in accumulator contains even
number of 1’s.
v. Carry flag – It is reset. This means that there is no carry generated from D7
bit in accumulator during arithmetic operation.
PROBLEMS ON FL AG R EGISTER OF 8085 MICROPROCESSOR

1. The flag register of 8085 microprocessor contains A3H. Interpret its

meaning.
Flag D7 D6 D5 D4 D3 D2 D1 D0
Register S Z - AC - P - CY
95H 1 0 1 0 0 0 1 1

i. Sign flag – It is set. This means that MSB of result in accumulator is set and
hence result is negative.
ii. Zero flag – It is reset. This means that result is non-zero after an arithmetic
or logic operation.
iii. Auxiliary carry flag – It is reset. This means that there is no carry generated
from D3 bit to D4 bit in accumulator during arithmetic operation.
iv. Parity flag – It is reset. This means that result in accumulator contains odd
number of 1’s.
v. Carry flag – It is set. This means that there is a carry generated from D7 bit
in accumulator during arithmetic operation.
THANK YOU !!!