Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 1 of 14

General Instructions
* Please read the instructions carefully. Item numbers preceded by ‘H’ are homework exercises. Item numbers preceded
by ‘S’ are LTspice simulation exercises, to be completed along with homework. Item numbers preceded by ‘L’ are
laboratory exercises, but the design should be completed before coming to the lab. Item numbers preceded by ‘PL’
are post laboratory exercises.

* Please maintain a neat record of the work done.

* lease take safety-related issues seriously. Please wear shoes while in the lab.
* how Pre-lab Reports to TAs as per the schedule. You will not be allowed to perform the experiments
without satisfactory pre-lab reports.

* Review the datasheets of LM555, LT1017 and LM339 for the lab exercises.
* Add power supply decoupling capacitors to the ICs in each experiment.

1 Saw-tooth waveform generator

H1. Understand the working of the circuit shown in Fig. 1 and draw the voltage across the capacitor and output voltage
(at pin-3 of LM555) and mark the salient features.

Figure 2: Labelled circuit for saw-tooth genera-

Figure 1: Saw-tooth wave form generator using tion
555 timer IC.

Working Principle : Referring to Figure 2, Constant current source sub-circuit uses T1 in active region to generate a
constant current. The value of constant current can be calculated by considering transistor T1 as shown:

Vb = V1 − VR2 − VD1
Vb = 15 − 3.3 × 103 × IR2 − 0.6
∴ Vb = 14.4 − 3.3 × 103 × IR2
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Applying KVL through the transistor T1

Vb = V1 − IR1 R1 − Veb
Vb = 15 − IR1 R1 − 0.6
Vb = 14.4 − IR1 R1
Equating the two expressions of Vb
14.4 − 3.3 × 103 × IR2 = 14.4 − IR1 R1
3.3 × 103
∴ IR1 = IR2
R1
V1 − VD1 15 − 0.6
where IR2 = = mA = 1.007 mA
R2 + R3 3.3 + 11
3.3 × 103
∴ IR1 = 1.007 × mA
R1

For R1 = 3.3 kΩ, current IR1 = IC1 = 1.007 mA charges the capacitor Figure 3: Internal architecture of 555 Timer
C1 from 0V to 2Vcc /3. From Figure 3, it can be noted that comparator
2 trips when it gets input greater than 2Vcc /3 and resets the SR flip-flop making Q̄ high thus turning ON the discharge
NPN transistor. The capacitor discharges until it reaches Vcc /3 at which point comparator 1 trips and sets the SR flip-
flop. The capacitor stops discharging as the NPN turns off and constant current circuit starts charging the capacitor.
The process repeats over and over again creating a triangular voltage waveform at the capacitor and pulsed output at the
output pin (pin 3). The corresponding waveforms of capacitor voltage and output pin voltage are shown in Figure 4. The
output voltage swings between Vcc /3 and 2Vcc /3 with a frequency dictated by the charging current (1 mA in this case)
and the value of capacitance C1 .

Figure 4: Capacitor voltage and Output pin voltage

S2. Derive the expression for the frequency of the saw-tooth waveform in-terms of Is . Simulate the circuit in Fig. 1 and
measure the frequency.

Assuming the charging time to be T1 and discharging time to be T2 , the frequency of sawtooth waveform is then by
definition f0 = 1/(T1 + T2 ). The current flowing through capacitor C2 and the voltage across its terminals can be used to
calculate T1 as shown:
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dvc (t)
IC2 = Is = C
dt
Z T1 Z 2Vcc /3
Is dt = Cdvc (t)
0 Vcc /3
 
2Vcc Vcc
T1 Is = C −
3 3
Vcc C
∴ T1 =
3Is
1 1
∴ f0 = = Vcc C
T1 + T2 3Is + T2
!
3Is 1
f0 =
CVcc 1 + 3I s T2
CVcc

3Is
if T2 << (Discharge time of capacitor is very less) then
CVcc
3Is
f0 ≈
CVcc

Using above formulae, the expected frequency of ramp waveform for circuit is f0 = (3 × 10−3 )/(0.1 × 10−6 × 15) = 2 kHz.
From simulation result shown in Figure 5, the observed frequency is 1.98 kHz which is in agreement with the calculated
value.

Figure 5: Transient simulation- Measured frequency of capacitor voltage

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L3. Assemble the circuit in Fig. 1 and verify calculated frequency in S2.(Show to TA)

S4. Modify the resistor values of the constant current source part to get a saw-tooth waveform of 50kHz. Simulate the
circuit in Fig. 1 with modified resistors and measure the frequency.

The RC time constant created by C1 and R4 creates a time constant of RC = 4.7 µs. 50 kHz wave has a time period of
20 µs which is comparable to T2 . Hence T2 cannot be ignored. T2 is thus calculated by using the discharging transient
equation of RC circuit as shown below:

vc (t) = v0 (e−t/R4 C1 )
1 2
Vcc = Vcc (e−t/4.7µs )
3 3
−t/47µs 1
e =
2
T2 = 4.7 × 10−6 × ln(2)
T2 ≈ 3.26 µs

Using result from S2

!
3Is 1
f0 = 3Is T2
CVcc 1+ CVcc
Is
0.025 =
1 + 6.4Is
0.025 = 0.84Is
∴ Is ≈ 29.76 mA

The required value of R1 is thus

Figure 6: Transient Simulation- Measured frequency of capacitor voltage (50kHz)
1.007 × 3.3 1.007 × 3.3
R1 = = ≈ 111.7Ω
IR1 29.76 × 10−3
Figure 6 shows the simulation result for R4 = 111.7 Ω. The circuit produces saw-tooth of frequency f0 = 42.2 kHz. The
error is pre-dominantly due to current source not providing the required current, still the frequency error is within ±20%.

L5. Modify the circuit in Fig. 1 with the resistor values calculated in S4 and verify the frequency.(Show to TA)
Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 5 of 14

2 Inverting Comparator

H6. What is the maximum sinking current of the LT1017? What is the value of minimum pull-up resistor, Rp(min) you
would use with ±15 V supply?

According to the data sheet of LT1017, the maximum sinking current is 65 mA. Maximum sinking current condition
corresponds to the output pin being low. The current through pull up resistor Rp is Ip and given by

Vpos − Vneg
Ip =
Rp
Vpos − Vneg
Rp(min) =
Ip(max)
30
Rp(min) = ≈ 460 Ω
65 × 10−3

H7. Fig. 2 shows an inverting comparator, draw the voltage transfer characteristics and mark the salient features.

Figure 7: Inverting comparator with hysteresis.

The addition of R2 and R1 network adds positive feedback to the comparator circuit and hence the threshold voltages for
rising voltage and falling voltage inputs are different which are calculated below:

1. Rising Voltage : Vin < V+ and hence V+ = (Vcc − Vref ) × R1 /(R1 + R2 + Rp ) + Vref due to pull up. Thus the rising
threshold voltage is Vth+ given by

R1
Vth+ = (Vcc − Vref ) × + Vref
R1 + R2 + Rp

If R1 >> Rp and R2 >> Rp then

R1
Vth+ ≈ (Vcc − Vref ) × + Vref
R1 + R2
Vcc R1 + Vref R2
Vth+ ≈
R1 + R2

2. Falling Voltage : Vin > V+ and so Vout = −Vcc hence V+ = (Vref + Vcc ) × R2 /(R1 + R2 ) − Vcc . Thus the falling
threshold is Vth− given by

Vref R2 − Vcc R1
Vth− =
R1 + R2
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3. Hysteresis: The difference between the rising and falling threshold of Vin creates the hysteresis band which is given
by
Vcc R1 + Vref R2 Vref R2 − Vcc R1
Vhys = Vth+ − Vth− = −
R1 + R2 R1 + R2
2Vcc R1
Vhys =
R1 + R2

Figure 8 shows the voltage transfer characteristics of the inverting comparator circuit with thresholds Vth+ , Vth− and the
hysteresis Vhys labelled.

Figure 8: Voltage transfer characteristics of inverting comparator with hysteresis

H8. Select the suitable resistor values to get a hysteresis of 1 V (±10% variation) for the circuit shown in Fig. 7. Use
2Rp(min) ≤ Rp ≤ 4Rp(min) .

Choosing Rp = 2.5Rp(min) = 2.5 × 460 ≈ 1.2 kΩ. Let R1 = 22 kΩ >> Rp , then R2 is calculated as shown below:

2Vcc R1
Vhys = =1
R1 + R2
R2
∴1+ = 2 × Vcc = 30
R1
∴ R2 = 29R1 = 638 kΩ

Using standard resistor values of R1 = 22 kΩ and R2 = 680 kΩ, we get a hysteresis band of
Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 7 of 14

2Vcc R1
Vhys =
R1 + R2
2 × 15 × 22 kΩ
Vhys = ≈ 0.94 V
680 kΩ + 22 kΩ

Above value is within ±10% tolerance band specified in design constraint so Rp = 1.2 kΩ, R1 = 22 kΩ and R2 = 680 kΩ
can be used.

H9. For Vin triangle waveform of 20 V pk-pk and a Vref = +5 V , draw the input and output waveforms and mark the
salient features. Repeat this for Vref = −5 V .

1. Vref = +5 V : The rising threshold and falling threshold are calculated as shown below:

Vcc R1 + Vref R2
Vth+ =
R1 + R2
15 × 22 + 5 × 680
Vth+ =
22 + 680
Vth+ ≈ 5.313 V
Vref R2 − Vcc R1
Vth− =
R1 + R2
5 × 680 − 15 × 22
Vth− =
22 + 680
Vth− ≈ 4.373 V
Vhys = V+ − V−
Vhys = 5.313 − 4.373 = 0.94 V

The output for inverting comparator for Vref = +5 V is shown in Figure 9.

Figure 9: Transient waveforms for comparator with Vref = +5V

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2. Vref = −5 V : The rising threshold and falling threshold are calculated as shown below:

Vcc R1 + Vref R2
Vth+ =
R1 + R2
15 × 22 − 5 × 680
Vth+ =
22 + 680
Vth+ ≈ −4.373 V
Vref R2 − Vcc R1
Vth− =
R1 + R2
−5 × 680 − 15 × 22
Vth− =
22 + 680
Vth− ≈ −5.313 V
Vhys = V+ − V−
Vhys = −4.373 + 5.313 = 0.94 V

The output for inverting comparator for Vref = −5 V is shown in Figure 10.

Figure 10: Transient waveforms for comparator with Vref = −5V

H10. For a small 1.5 V step change in Vref as in H9, what is the fastest and slowest response obtained from the circuit
in Fig. 7? What should be the maximum slew rate in the reference to prevent multiple switching?

Fastest response is when the comparator output turns from actively driven low state to high impedance pull-up state.
For Rp = 1.2 kΩ, the delay is about 5.57 µs. Slowest response is observed when the comparator output turns from high
impedance pull-up state to actively driven low state with propagation delay of 9.69 µs. Change in reference voltage Vref
also results change in threshold which leads to multiple switching of output when the input is in the neighbourhood of
threshold voltage as shown in Figure 11.
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Figure 11: Transient waveforms showing multiple switching when Vref changes

S11. For circuit given in Fig. 7 give any three reference voltages and appropriate magnitude and frequency triangle
waveform as an input. Tabulate the reference, upper and lower threshold voltages. Simulate the circuit and compare the
voltages obtained.

Calculated Simulated
S No.
Vref V+ V- Vref V+ V-
1 2 2.407 1.467 2 2.453 1.435
2 6 6.282 5.342 6 6.346 5.333
3 -3 -2.436 -3.376 -3 -2.41 -3.42

Table 1: Comparison of calculated thresholds and simulated thresholds

Figure 12: Transient waveforms for comparator with Vref = 2V

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Figure 13: Transient waveforms for comparator with Vref = 6V

Figure 14: Transient waveforms for comparator with Vref = −3V

L12. Assemble the circuit in Fig. 7 give any three reference voltages through a 10 kΩ pot and appropriate magnitude and
frequency triangle wave form from function generator as an input. Verify calculated voltages in S11 .(Show to TA)
Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 11 of 14

L13. Is the hysteresis constant in all the cases of L12 and equal to the designed value? Write your comments on the
obtained results.(Show to TA)

S14. Give a reference voltage of +VCC /2 and saw-tooth waveform generated in S2(Fig. 1) as input to the comparator
LT1017. Simulate the circuits in Fig. 1 and Fig. 2. Measure the delay between falling edge of the ramp and transition of
the comparator output voltage level and the settling time.

Figure 15: Circuit for transient simulation of PWM generation circuit

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Figure 16: Transient simulation of PWM generation circuit

From Figure 17, the delay between falling edge of ramp and rising edge of comparator output is roughly 6.25 µs and the
10% − 90% settling time is around 2.74 µs.

Figure 17: Transient simulation- Delay measurement

L15. Give sawtooth waveform generated by circuit in Fig. 1 as input to the circuit in Fig. 7 with comparator LT1017
and reference voltage of +VCC /2 and verify S14.(Show to TA).
Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 13 of 14

S16. Repeat the simulation S14 with comparator LM339. Comment on the results obtained.

Replacing the comparator IC LT1017 with LM339 and simulating we get propagation delay of about 1.038 µs and a
settling time of 210 ns as shown in Figure 18. This disparity in performance is expected as the datasheet of LT1017
clearly indicates that the response time is in the order of 10 µs where as it is around 1.5 µs for LM339.

Figure 18: Transient simulation- Delay measurement for LM339 comparator

L17. Give sawtooth waveform generated by circuit in Fig. 1 as input to the circuit in Fig. 7 with comparator LM339 and
reference voltage of +VCC /2 and verify S14.(Show to TA)
Vibhore Jain 25705 E6 221 SMPC Experiment 4 page 14 of 14

3 Post Laboratory Exercise

PL18. What are the key takeaways from this lab exercise? (Only bullet points are sufficient)

PL19. How do you modify the inverting-hysteresis circuit to avoid the effect of the source impedance?

PL20. Why do comparators exhibits faster dynamics compared op-amps? Can an op-amp be used in place of a comparator?