Vivado and Xilinx’s Vitis Tutorial: VGA

Controller
ENSC 452 Tutorial

Simon Fraser University

Written by: Zavier Aguila

Last Modified: January 16, 2020
Overview: 4

Gathering Important Information: 5

Display: 5

Zedboard I/O: 7

Image to display: 7

Vivado: 9
Setting up your project: 9
Using the project wizard to setup your project: 9
Adding Constraints and what they are: 10
Adding zedboard_master.xdc as a constraints file: 10
Accessing and opening the constraints file: 11
Editing the constraints file: 12
Adding RTL Files (Not needed for this tutorial, but very important for your projects): 13
Adding Custom IP Cores to your Project: 13
Setting up the Zynq Chip Environment then Adding VGA Core: 14
Creating a Block Design: 14
Adding IPs to the Block Diagram: 14
Customizing the Zynq Chip: 15
Connecting the ZYNQ to external pins: 16
Connecting the ZYNQ to the Clocking Wizard manually: 16
Customizing the Clocking Wizard: 16
Connecting the Processor System Reset: 17
Connecting the VGA Controller: 17
Customizing the VGA Controller: 18
Connecting the AXI timer: 18
Connecting the SmartConnect: 18
Assigning Addresses to Peripherals: 18
Synthesize the Design: 19
Synthesize, Implement, Generate Bitstream: 19
Program the FPGA: 20
Preparing the Zedboard: 20
(Option A) Programming through Vivado: Error! Bookmark not defined.
(Option B) Programming through the Vitis: 22

Vitis: 22
Setting up Vitis Project: 22
Adding the software code: 23
Program the FPGA: 23

2
Run the software: 23
Load images into memory: 24

3
Overview:
This tutorial will guide you through the process of being able to display images to a screen.

It will have you interact with Vivado and the Xilinx Vitis, and will point out some of the important
features found in each. It will also make use of some the Zedboard and Zync Documentation to
show you where you might look to find technical details that might be needed during your ENSC
452 Project. You will be provided with a VGA core that you are also free to use in your
project.

With that being said, this VGA core uses the DDR memory of the Zedboard to hold its image
buffer data. It has the ability to switch between two buffers to enable double-buffering to mitigate
screen tearing. It has been tested to display up to 1080p (1920 x 1080). For some applications
(such as low resolution or highly pixelated output), other approaches might be more applicable.

Even if this tutorial will not explain how to design a VGA Controller, this’ll still be quite the ride,
so buckle up, and enjoy the ride.

4
Gathering Important Information:
Let us remind ourselves what our goal is: Display images to a screen from the Zedboard.
Given this goal we will need to find a couple key pieces of information. Can you already think of
some? For the following section we will tackle it using the following categories: Display,
ZedBoard I/O, Image to Display.

Display:
In the Labs, the screens might have multiple display inputs: VGA, HDMI, Displayport. Looking at
the Zedboard itself and its Hardware User Guide (Page 4):

[Link]
(This is a good place to look at the I/O’s of the Zedboard)

We note that it has an HDMI and VGA Port. We will be using the VGA port because it is
simpler, resources are more readily available, and will suffice for our goal.

Ok, we know what port we’ll use, what about what resolution we will display at? For this tutorial
let’s settle with 1280 x 1024 @ 60fps for now. (You can choose the resolution to any that your
screen supports).

This tutorial will not discuss the inner-workings of the core and how a single frame is displayed
to the screen. If you’re interested, a quick google of VGA Specification (even the wikipedia
page) will give you the resources you can read. The “Video Signals in Brief” section from the
website:

[Link]

has a good preliminary explanation of VGAs.

5
The VGA core will need a couple parameters:

H - Horizontal
V - Vertical

Parameter Value

H Back Porch

H Front Porch

H Sync Polarity “1” or “0”

including quotation marks

H Sync Pulse

Horizontal Length (Visible Area)

Image Buffer1 Baseaddr

V Back Porch
V Front Porch

V Sync Polarity “1” or “0”

including quotation marks

V Sync Pulse

V Length (Visible Area)

Image Buffer2 Baseaddr

Pixel Clock

From the website: [Link] (Again, a quick google of VGA timing will give
you this great resource), fill out the table above. Leave the Baseaddr entries blank for now.

Remember we are displaying at 1280x1024 @60fps.

If you had wanted a different resolution, this is where you can change that.

This table will be used later on, so don’t forget about it.

6
Zedboard I/O:
We’ve gathered key information needed to display to VGA. Now, how does the VGA interface
with the Zedboard? We don’t know? Well, it’s a good thing there’s the Zedboard Hardware
User’s Guide:

[Link]

In the VGA Connector section (page 17), it actually details what each pin in the VGA is. Pay
attention to VGA Pin 1,2 and 3. First notice that each VGA Pin corresponds to four Zynq Pins.
Second notice that it says this VGA controller allows 12 bit colour. This means each colour in
RGB only has 4 bits which is not exactly the best, this often means that the colour that will be
displayed will not be the original color of the image but it’s what we have to work with.

Back to the pins, fill out the tables below with which Zynq Pins corresponds to the which VGA
pins. Again, we’ll use this information later on.

VGA Pin Colour Zynq Pin

VGA Pin Zynq Pin

HSync

VSync

7
Image to display:
You have been provided multiple 1280x1024 images to display. Note that you have been given
a .jpg and a .data variant of the same image. Most image formats will have some level of
compression done on the image data and it will also have a header containing information
regarding the image. This core does not have the ability to parse through that compression or
remove the header information (Project Idea, anyone?), it only takes in the RGB data. Luckily
the desktop program GIMP has an option to do just this, and the output is the .data file.

For now, you will just use the given .data files.

Awesome now we have all the information needed to get started, let’s get onto Vivado!

8
Vivado:
Setting up your project:
Using the project wizard to setup your project:

1. !"#$%!&'()*+!)%*!,-$).$!)!%$/!0-+1$,.!23'4$!5!0-+1$,.!5!6$/78
2. Click Next.
3. Provide a name and a location for your project.
4. Check the “create project sub-directory” option.
5. Click Next.
6. Choose RTL Project at this time.
7. Click Next.
8. Set Target language to VHDL.
9. We will not add files right now (we will later).
10. Click Next.
11. We will not add constraints right now (we will later).
12. Click Next.
13. Change the view from Parts to Boards.
14. Choose Zedboard Zynq Evaluation and Development Kit.

9
 15. Click Next.
16. Click Finish.

Adding Constraints and what they are:

One of the files given to you is an zedboard_master.xdc file, this is the constraints file. What it is
will be discussed after we add it to the project.

Adding zedboard_master.xdc as a constraints file:

1. !9$4$,.!3'4$!5!:**!9+;-,$<888
2. Select “Add or Create Constraints”.
3. Click Next.
4. Check “Copy constraints file into project”.
5. Select “Add Files” and direct it to zedboard_master.xdc.
6. Click Finish.

10
Accessing and opening the constraints file:
[Link] the Sources section of the Vivado window, make sure Hierarchy is selected.

The sources section is your one-stop-shop to the files you have added to your project.
There are 3 main options to view the files. Hierarchy, Libraries and Compile order. Each
of them are self-explanatory, I hope, if not:

Hierarchy - Project Hierarchy or what files call what files.

Libraries - Just a list of all the files.

Compile Order – The compile order of the files. Vivado does a decent job at figuring this
order out, but of course, sometimes it doesn’t and that might break your designs.

It also has a search function, so if you have a large amount of files, this could prove
useful.

2. Expand the Constraints folder.

3. Expand the constrs_1.

4. Doubleclick the zedboard_master.xdc to open.

Looking inside it’s a bunch of commented lines:

11
#set_property PACKAGE_PIN <zynq pin> [get_ports {<given signal name>}]

Example:

set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}];

zynq pin = AB1

given signal name = AC_ADR0

These lines assign a name to each zynq pin that provides more information regarding what the
zynq pins are for, and we will use these signal names instead in our design. Feel free to change
the given signal name to anything you might think might be a more appropriate name.

Remember those Zynq pins you noted down? Time to uncomment and edit their respective
entries.

Editing the constraints file:

1. Uncomment all “set_property...” lines that correspond to the VGA Zync pins. There should
be (12 + 2) lines that are going to be uncommented.

2. For the RGB pins (VGA_B1, VGA_B2…), we will change them to exist as arrays, this is
important for the core. When you design cores, sometimes it’ll be easier to use an array as
opposed to separate signals (think of loops!).

Example:

Remember arrays start at index 0.

! &=:>?@!! 5! &=:>?ABC

! &=:>?D! !5! &=:>?A@C

! &=:>?E!! 5! &=:>?ADC

! &=:>?F!! 5! &=:>?AEC

Do this for all colours (Red, Green, Blue).

Your constraints have been set, now those I/O can be used by your project.

12
Adding RTL Files (Not needed for this tutorial, but very
important for your projects):
As the title heavy handedly suggests, you don’t need to do this for this tutorial, but is placed for
reference.
1. G4',H!3'4$!5!:**!9+;-,$<I
2. Select “Add or Create Design Sources”.
3. Specify the file of files desired.
4. Click OK.
5. Click Finish.

Adding Custom IP Cores to your Project:

Vivado’s IP Catalog already comes with a number of IP Cores, but we we still ad one more to
the list, the VGA controller.

1. Select Flow Navigator -> IP Integrator -> IP Catalog.

2. In the IP Catalog, right click and select Add Repository…

3. Navigate to the vga_controller_ip folder.
4. Click Select.
5. Click OK.
a. This will add a “User Repository” to the list. Make sure that under User
Repository -> UserIP vga_controller_v1_0 is present.

13
Setting up the Zynq Chip Environment then Adding VGA Core:
Get comfy because this is probably the most intense part of this tutorial. You can do it, and don’t
hesitate to ask for help!

Something that is quite nice with Vivado is how it visually represents a system with different
chips, I/O and modules. We will utilize something called a Block Design to help us setup an
environment on the zedboard.

Creating a Block Design:

1. In the Flow Navigator Section of Vivado and under “IP Integrator”, press Create Block
Design.
2. Provide a design name. design_1 will suffice.
3. Make sure Directory is set to “Local to Project”.
4. Make sure source set is Design Sources.
5. Click OK, a new and empty Diagram should appear.
6. In the Sources section, right click on design_1, and select create HDL Wrapper, allow
Vivado to manage the wrapper.
7. Click OK.

Adding IPs to the Block Diagram:

1. From the Flow Navigator, select 0-+1$,.!J)%)K$-5!L0!G).)4+K.

a. This will bring up a giant list of IP Cores that comes preloaded with Vivado. This
is another good place to see what are some of the IP cores that are available.
Don’t fully understand how to use the cores? No worries, Google the core’s
name, and you should be able to find documentation.
b. You can also right click right click on the diagram itself and chose “Add IP”.
2. Search and add (by double clicking and choosing “Add IP to Block Design”. Don’t
worry we will customize them soon enough):
a. ZYNQ7 Processing System
b. Clocking Wizard
c. Processor System Reset
d. AXI Timer
e. AXI smartconnect
f. vga_controller

14
Customizing the Zynq Chip:
1. Run Block Automation.
a. In the top left corner of the block diagram, you should see “Run Block
Automation.” Click on this.

b. Ensure that processing_system is checked.

c. Click OK.

15
 2. Activate the High Performance (HP) AXI Slave ports
a. In the diagram double-click on the ZYNQ7 Processing System to open the Re-
customize IP window.
b. L%!.M$!0)K$!6)('K).+-N!%)('K).$!.+!.M$!09O0P!G+%Q'K;-).'+%!5!R0!94)($!:SL!

L%.$-Q),$!5S AXI HP0 interface.

c. Enable the HP0 Interface.
i. Data width is 64 bits.
3. Activate and change the FCLK_CLK0 Frequency to 120 Mhz
a. G4+,H!G+%Q'K;-).'+%!5!0P!3)T-',!G4+,H8
4. Change CPU Clock to 200 Mhz
a. G4+,H!G+%Q'K;-).'+%!5!0-+,$<<+-UJ$V+-W!G4+,H<8
5. Activate PL to PS interrupts
a. L%.$--;#.<!5!3)T-',!L%.$--;#.<!50P!O!09!5 IRQ_F2P[15:0]

Connecting the ZYNQ to external pins:

1. Connect the FCLK_CLK0 to M_AXI_GP0_ACLK and S_AXI_HP0_ACLK.
a. In the Diagram, hover over the “black pin” beside the FCLK_CLK0 signal of the
Zynq until the mouse turns into a pencil, now click and drag to the “black pin”
beside M_AXI_GP0_ACLK. This should connect the pins
b. Continue draggin to S_AXI_HP0_ACLK. Click to connect.
i. Pressing any key will cancel out of it.

Connecting the ZYNQ to the Clocking Wizard manually:

1. Connect the FCLK_CLK0 to clk_in1 of the clocking wizard.

Customizing the Clocking Wizard:

1. Similar to the Zynq, open the Re-customize IP window of the Clocking Wizard.
2. In the Output Clocks tab, change clk_out1’s Requested Frequency to the Pixel Clock
you recorded for your desired resolution. Remember, you should have recorded the
Pixel along along with the VGA specifications.
a. You will see the actual frequency the wizard can produce, sometimes this will not
be exactly what you requested.
b. You are free to change the port name as well, for now, we can leave it as
clk_out1.
3. In the Output Clocks tab, change the reset type to Active Low.
a. You’ll see that the reset will change to resetn.
4. Click OK.
5. Connect reset to Zynq’s FLCK_RESET0_N pin.

16
Connecting the Processor System Reset:
1. Connect the slowest synchronous clock.
a. In our case the slowest will be our pixel clock, clk_out1, (108 Mhz), so connect
the Clocking Wizard’s output pin to Processor System Reset’s
slowest_sync_clk pin.
2. Connect FLCK_RESET0_N to Processor System Reset’s ext_reset_in pin.
a. Note: unlike the clocking wizard’s reset pin being default active high, this pin’s
default is active low which is denoted by that bubble by its black pin.

Connecting the VGA Controller:

1. Connect the clk to FLCK_CLK0(Zynq).
2. Connect the pixel_clk to clk_out1.
3. Connect both the rstn and the pixel_rstn to the peripheral_aresetn.
4. Connect fifo_rst to the peripheral_reset
5. Expand the S_AXI_HP0_FIFO_CTRL on the ZYNQ, connect
S_AXI_HP0_RCOUNT[7:0] to to rfifo_count[7:0].
6. Connect the M_AXI pin the the ZYNQ’s S_AXI_HP0.
7. Make the VGA_HS, VGA_VS, VGA_R[3:0], VGA_G[3:0] and VGA_B[3:0] external
pins.
a. Right Click on the pins, and choose Make External.
8. Change the name of the external pins to the name you gave in the constraints file. Do
you still remember what they were?
a. Click on each external pin, an External Port Properties should appear.
b. Change the auto generated name.

17
Customizing the VGA Controller:
1. Remember that bigger table you were supposed to fill out, time to use it!
2. In the diagram double-click on the vga controller to open the Re-customize IP window.
3. Fill it up!
a. Remember, for the H/V Sync Polarity, you must include the quotation marks
in “1” or “0”.
b. “1” is positive and “0” is negative.

Connecting the AXI timer:

1. Connect s_axi_aclk and s_axi_arestn to Zynq’s FLCK_CLK0 and
peripheral_aresetn, respectively.
2. Connect the AXI Timer’s S_AXI port to the smartconnect’s M00_AXI pin.
3. Connect the interrupt pin to Zynq’s IRQ_F2P
a. The IRQ_F2P will resize itself depending on what you connect to it which is
pretty cool.

Connecting the SmartConnect:

1. Connect aclk and arestn to Zynq’s FLCK_CLK0 and interconnect_aresetn,
respectively.
2. Connecting S00_AXI to Zynq’s M_AXI_GP0.

Assigning Addresses to Peripherals:

Awesome, we are almost there. Now, despite the Axi timer being connected to the Zynq, the
Processor has no way to communicate with it, we still have to give it an address. What address
are we going to use? Well, the Zynq has reserved memory address for specific parts, so let’s
take a look at the Zynq Technical Manual:
([Link]
Page 112, System Address.

Since we are using M_AXI_GP0, we can use any address from 4000_0000 to 7FFF_FFFF.

1. Navigate to the Address Editor Tab

2. XY#)%*!#-+,$<<'%K><W<.$VZ>B!5![).)!5!\%V)##$*!94)($<
3. Right Click on the S_AXI row, select Assign Address
a. This will assign it an address, double check that it is in the range we want.

On the VGA side, it’s a bit different. It doesn’t need an address because it is a master that is
directly connected to the HP port of the Zynq, so if you use Assign Address it will set it to a
value of 0, this is expected.

18
 1. XY#)%*!#-+,$<<'%K><W<.$VZ>B!5![).)!5!\%V)##$*!94)($<
2. Right Click on the S_AXI_HP0 row, select Assign Address. This will assign it 0.

Remember you left those baseaddr field we left blank? We now need to assign a field to that.
The VGA is connected to the HP port, from the System Address table we note that the AXI_HP
port has access to the DDR through the addresses 0008_0000 to 000F_FFFF. So pick an
address from this range. For this tutorial, we will only use one of the buffers so only baseaddr1
has to have a value.

1. Recustomize the vga_controller and set your chosen address in the Image Buffer1
Baseaddr.
a. For this tutorial, let’s select 0x00900000.
By the end of all this you should have a diagram that looks like:

Synthesize the Design:

Synthesize, Implement, Generate Bitstream:

You can do these steps one-by-one or you can also press Generate Bitstream and it will do
whatever step has not been completed first.

1. Press Run Synthesis. Let it finish.

2. Press Implementation. Let it finish.
3. Generate Bitstream. Let it finish.

19
Program the FPGA:
There are two ways to program the board, though Vivado and through the Vitis, and they are not
the same.

Programming through Vivado will not bring the board out of reset and will not program the Zynq
Chip, additional commands must be given (which will be detailed below), but if you are focusing
on creating logic on the PL, this method is quicker.

Programming through the Vitis will bring the board out of reset, program your chip and add
whatever software code you’ve made.

For this tutorial, we’ll program it using the Vitis as there is software that needs to be
programmed as well, but you can also try programming using Vivado only, and the VGA
controller will still work, but the image on the screen will not change automatically.

Preparing the Zedboard:

1. Make sure the jumpers are in this order. Sig connected to GND
a. Other jumper positions correspond to different boot modes which might be
important for some of your future projects.

b.
2. Connect the Prog micro usb to the computer.
a. The one to the right of the power supply input.
3. Connect the VGA display.
4. Connect the power supply.
a. Top left of the board.

20
5. Turn the board on.
a. Top left of the board,under the AC port.
1. From the Flow Navigator, press Open Hardware Manager.
a. A hardware window will replace the Sources window.
2. In the Hardware window, press the Auto Connect button.
a. It should now look like:

3. Right click on xc7z020_1.

4. Select Program Device...
5. Click Program. Let it finish.
a. Vivado will usually pick the correct bitstream file.
b. Now your hardware logic is on the FPGA fabric, but it has not been brought out
of reset.
6. In Windows search for the program Vivado Tcl Shell and type in the following
commands.
xsdb
connect
target 1
source <file name to this file:
project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system
7_0_0/ps7_init.tcl>
i. You’ll need to look for the ps7_init.tcl. The above file path can guide to
the correct folder
ps7_init
Ps7_post_config
dow -data <path to [Link]> <Address of Image Buffer 1>

21
(Option B) Programming through the Vitis. Export .XSA file:
1. 9$4$,.!3'4$!5!XY#+-.!5!R)-*/)-$I
2. Make sure Include bitstream is selected
3. Click OK.
4. 9$4$,.!]++4<!5!P);%,M!&'.'<!L[X!

Vitis:
So if you look at older examples or tutorials, they might mention the Xilinx SDK. The SDK has
now been replaced by Vitis. There are some changes that you have to account for. The one that
applies to you will probably be bringing in your hardware from Vivado to SDK.

Note: There is Vitis HLS and XIlinx Vitis, they are not the same. We want Xilinx Vitis

Setting up a Vitis Platform Project:

1. 6)('K).$!.+!3'4$!!5!6$/!5!Platform Project…
2. Give your platform a name.
3. Click Next.
4. In the Next window, under the “create a new platform from hardware”, click “Browse…”
5. Navigate to where you exported the .xsa file in the previous section.
6. Click Finish.

Setting up Vitis Project:

1. 6)('K).$!.+!3'4$!!56$/!5!Application Project…
2. When asked to select a platform, select the one added in the previous section.
3. Click Next.
4. Click Next.
5. Give your project a name
6. Pick “Empty Application (C++), as your template.
7. Click Finish.
8. From the project explorer, select your project.

22
Adding the software code:
1. Copy the contents of vga_software(This is found in the zip file given to you) to the
[Link] of the previously created Application project.

Program the FPGA:

1. Either through clicking the Icon or navigating to Xilinx -> Program FPGA.
2. Click Program.

Run the software:

1. Click on the down arrow beside either Debug/Run Icon

a. For now, let’s use Debug.
2. Select Debug as...
3. Select Launch on Hardware.
a. This will automatically create the configuration.

23
 b. After it is created you can edit it to program the FPGA before you program the
software.

Load images into memory:

1. Find the XSCT Console in the Vitis’s debug perspective.

2. Enter the commands:

dow -data <path to [Link]> 0x018D2008
dow -data <path to [Link]> 0x020BB00C
dow -data <path to [Link]> 0x028A4010
dow -data <path to [Link]> 0x0308D014
dow -data <path to [Link]> 0x03876018

If everything has gone right, the VGA display should start cycling between highly pixelated
display of Vivado, a sight that will fill you with excitement or dread, maybe both at the same
time, throughout the semester.

24