1
Govt. College of Engineering, Kannur
Session on Adders (VLSI)
THOMAS MOHAN,
Asst. Professor,
Department of ECE,
M A College of Engineering,
Kothamangalam
2
Contents
Full Adder
Ripple-Carry Adder
Carry-Bypass Adder
Linear Carry-Select Adder
Square-root Carry-Select Adder
3
Full Adder
To add 2 bits along with an input carry
Input bits: A & B
Carry input: Ci
Sum: S
Carry output: Co
4
Static Adder
(Static Complementary CMOS implementation of Full Adder)
Equation of Sum in an FA can be
modified to use the carry output
also.
5
Ripple-carry Adder
To add two N-bit numbers
N-bit ripple carry adder constructed by cascading N full adders
Carry bit ripples from one stage to another
6
Ripple-carry Adder (contd.)
Worst case delay
Propagation delay that occurs when carry has to propagate from least significant bit to the most significant bit
Eg: Inputs 0001 and 0111 produces worst case delays for a 4-bit addition
Propagation delay of ripple-carry adder,
tadder = (N-1)tcarry + tsum
where N = number of stages
tcarry = propagation delay from Ci to Co
tsum = propagation delay from Ci to S
Delay for carry to propagate through (N-1) lower stages + delay for sum calculation at MSB
Delay is a major issue for large word lengths (128 bit adder)
7
Carry-Bypass Adder (or Carry-skip adder)
An alternative to ripple carry adder for adding bigger numbers (64 bit,
128 bit, etc.)
Generate (G), Delete(D) & Propagate(P) signals
Generate: G=1 ensures that Co will be generated (equal to 1) independent of
Ci
Delete: D=1 ensures that Co will be deleted (equal to 0) independent of Ci
Propagate: P=1 ensures that Ci will propagate to Co (Co will be equal to Ci)
G, D & P are functions of A & B alone. So can be calculated before carry
arrives from previous stage
Sum and Carry out are rewritten in terms of new signals
8
Carry-Bypass Adder (contd.)
In a 4-bit adder, if P0P1P2P3 = 1, then carry input =1 will propagate through all 4 full adders and
produce an output carry
i.e. if Bypass signal BP = P0P1P2P3 = 1, then Co,3 = Ci,0
Carry-bypass adder uses this theory to speed up operation
9
Carry-Bypass Adder (contd.)
Adder can be considered to consist of a carry propagation section and a sum calculation
section
Carry propagation section is shown below
If BP = 1, then the entire carry propagation section is bypassed
10
Carry-Bypass Adder (contd.)
To create an N-bit adder, the total adder is divided into N/M bypass stages
Each stage contains M bits
11
Worst case delay path identification
Sample case 1: Sample case 2: Sample case 3 (Worst case path):
A: 1111 1111 1111 1111 A: 1111 1111 1111 1111 A: 0111 1111 1111 1111
B: 0000 0000 0000 0001 B: 0000 0000 1000 0001 B: 0000 0000 0000 0001
G: 0000 0000 0000 0001 G: 0000 0000 1000 0001 G: 0000 0000 0000 0001
P: 1111 1111 1111 1110 P: 1111 1111 0111 1110 P: 0111 1111 1111 1110
BP: 1 1 1 0 BP: 1 1 0 0 BP: 0 1 1 0
Worst case delay path is shown in gray colour in previous figure
12
Carry-Bypass Adder – Propagation delay
Propagation delay of N-bit adder,
tp = tsetup + Mtcarry + (N/M – 1)tbypass + (M-1)tcarry +tsum
tsetup : Time to create G and P signals
tcarry: Propagation delay through one Full Adder
tbypass: Propagation delay through one multiplexer
tsum: Time to calculate sum in final stage
13
Linear Carry-Select Adder
Instead of waiting for carry output from previous FAs,
results for both possibilities are evaluated in
advance
Once real value of carry is know, a multiplexer is
used to select he correct result
4-bit linear carry-select module
14
Linear Carry-Select Adder (contd.)
16-bit linear carry-select adder
Critical path is marked in gray
colour
Worst case Propagation delay:
Delay is proportional to N
15
Linear Carry-Select Adder (contd.)
Signal timings of a Linear carry-select
adder
(Assuming that a full adder and mux has
same delay)
Arrival times are shown in brackets
In last stage mux input, big mismatch
between arrival times of inputs from
previous stage and upper carry blocks
16
Square-root Carry-Select Adder (contd.)
In square-root carry-select
adder, mismatch in arrival times
reduced by varying the number
of bits in each stage
Number fo bits is consecutive
stages:
2,3,4,5,6 etc.
This results in reduced
propagation delay
17
Square-root Carry-Select Adder (contd.)
In an N-bit square-root carry-select adder,
18
Propagation delay comparison
19
THANK YOU