Name of Institution
Amity School of Engineering &
Technology
[Link]. CSE, Semester V
Computer Architecture Module - 2
1
Basic Computer Organizations and
NameDesign
of Institution
The organization of the computer is defined by its internal
registers, the timing and control structure, and the set of
instructions that it uses.
▪ Internal organization of a computer is defined by the sequence
of micro-operations it performs on data stored in its registers.
➢ User controls this process by means of a Program.
Program: set of instructions that specify the operations,
operands, and the sequence by which processing has to occur.
Instruction: a binary code that specifies a sequence of micro-
operations for the computer. 2
Instruction Codes Name of Institution
Instruction code is a group of bits that instruct the computer to
perform a specific operation.
An instruction consists of fields which include:
➢ Address – where address to memory is stored.
➢ Opcode – Operation code .
➢ Addressing mode – Effective address to operand.
I (15) Opcode (12-14) Address (0-11)
Addressing mode 3
Basic Computer Organizations and
NameDesign
of Institution
• Instruction code is a collection of binary codes.
• It represents the operations that a computer processor can
perform.
• The structure of an instruction code can vary and depends
on the architecture of the processor but generally consists
of the following parts:
✓ Opcode
✓ Operand
✓ Mode 4
Basic Computer Organizations and
NameDesign
of Institution
Opcode: An opcode specifies the operation to be performed.
➢ It consist of n bits for a given 2𝑛 operations.
Operand: It is an address that specifies the memory
locations where operand is to be found.
Addressing mode: Effective address to operand.
It might indicate that the operand is a direct address in
memory, an indirect address or an immediate value. 5
Basic Computer Organizations and
NameDesign
of Institution
Addressing of Operand:
1. immediate operand
2. direct address
3. indirect address
Direct Indirect
6
Computer Registers Name of Institution
Register is a small but high speed storage area within the
CPU. All data must be temporarily stored in a register before
it can be processed.
A Register is a group of flip-flops with each flip-flop
capable of storing one bit of information.
The number of registers that a CPU has and the size of
each (number of bits) help determine the power and
speed of a CPU.
The list of registers are mentioned in the next slide.
7
Computer Registers Name of Institution
8
Computer Registers Name of Institution
Register Symbol Number of bits Function
Data register DR 16 Holds memory operand
Address register AR 12 Holds address for the memory
Accumulator AC 16 Processor register
Instruction register IR 16 Holds instruction code
Program counter PC 12 Holds address of the instruction
Temporary register TR 16 Holds temporary data
Input register INPR 8 Holds input character
Output register OUTR 8 Holds output character
9
Name of Institution
Combinational Logic
ALU
10
Name of Institution
Common Bus System for
basic computer register
The basic computer has eight
registers, a memory unit and a
control unit.
The outputs of 7 registers and
memory are connected to the
common bus.
The specific output that is
selected for the bus lines at any
given time is determined from
the binary value of the selection
variables S2, S1, and S0.
11
Name of Institution
Clock Signal provides timing signal for synchronization
among different components and also controls LD (load), INR
(increment), and CLR (Clear register) commands by the control
unit.
Note: Content of any register can be sent onto the BUS and
operation can be performed in ALU during same clock pulse only.
12
Computer InstructionsName of Institution
The basic computer has three instructions code formats.
1. 1. Memory reference instruction
2. 2. Register reference instruction
3. 3. Input / output instruction
Each format has 16 bits.
13
Computer InstructionsName of Institution
A memory-reference instruction uses 12 bits to specify an
address and one bit to specify the addressing mode I.
I is equal to 0 for direct address and to 1 for indirect address. 14
Memory reference instruction
Name of Institution
In Memory reference instruction:
✓ First 12 bits (0-11) specify an address which is denoted by
three x ’ s (in hexadecimal notation) and is equivalent to
12-bit address.
The last addressing mode bit of the instruction
represents by symbol I.
When I = 0, the last four bits of an instruction
have a hexadecimal digit equivalent from 0 to 6.
When I = 1 the last four bits of an instruction
have a hexadecimal digit equivalent from 8 to E.
15
Computer InstructionsName of Institution
Symbol Hexadecimal code Description
I=0 I=1
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx ADD memory word to AC
LDA 2xxx Axxx LOAD Memory word to AC
STA 3xxx Bxxx Store content of AC in
memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return
address
ISZ 6xxx Exxx Increment and Skip if zero
16
Register Reference Instructions
Name of Institution
The register reference instructions are recognized by
the operation code 111 with a 0 in the leftmost bit (bit
15) of the instruction.
• A register-reference instruction specifies an operation
on or a test of the AC register.
• An operand from memory is not needed; therefore,
the other 12 bits are used to specify the operation or
test to be executed.
17
Register Reference Instructions
Name of Institution
Symbol Hexadecimal Description
code
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction is AC is
negative
SZA 7004 Skip next instruction is AC is 0
SZE 7002 Skip next instruction is E is 0
HLT 7001 Halt computer 18
Input Output Instructions
Name of Institution
An input-output instruction does not need a reference to
memory.
It is recognized by the operation code 111 with a 1 in the
leftmost bit of the instruction.
The remaining 12 bits are used to specify the type of
input-output operation or test performed.
19
Input Output Instructions
Name of Institution
Symbol Hexadecimal Description
Code
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt On
IOF F040 Interrupt Off
20
Timing and Control Name of Institution
The timing for all registers in the basic computer is
controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers
in the system, including the flip-flops and registers in the
control unit.
✓ Clock pulses cannot change the state of register
unless enabled by a control signal.
The control signals are generated in the control unit and
provide control inputs for the multiplexers in the
common bus, control inputs in processor registers, and
microoperations for the accumulator.
21
Timing and Control Name of Institution
There are two major types of control organization:
1. Hardwired control
2. Microprogrammed control
Hardwired Microprogrammed
The control logic is implemented The control information is stored
with gates, flip-flops, decoders, in a control memory. Control
and other digital circuits. memory is programmed to initiate
the sequence of microoperations.
It can be optimized to produce a Compared with the hardwired
fast mode of operation. control operation is slow.
Requires changes in the wiring of Any required changes can be
various components if the design done by modifying the
has to be modified or changed. microprogram in control memory.
22
Name of Institution
Block diagram
of Control Unit
23
Timing and Control Name of Institution
Components of Wired Control unit are:
1. Two decoders
2. A sequence counter
3. Control logic gates
An instruction read from memory is placed in the
instruction register (IR).
The operation code in bits 12 through 14 are decoded
with a 3 X 8 decoder. The eight outputs of the decoder are
designated by the symbols D0 through D7.
24
Timing and Control Name of Institution
15th bit of the instruction is transferred to a flip-flop designated by
the symbol I.
Bits 0 to 11 are applied to the control logic gates.
The 4‐bit sequence counter can count in binary from 0 through 15.
The outputs of counter are decoded into 16 timing signals T0
through T15.
The sequence counter (SC) can be incremented or cleared
synchronously. Once in awhile, the counter is cleared to 0, causing
the next timing signal to be T0.
25
Name of Institution
As an example, consider the case where SC is incremented to
provide timing signals 𝑇0 , 𝑇1 , 𝑇2 , 𝑇3 and 𝑇4 in sequence.
At time 𝑇4 , SC is cleared to 0 if decoder output 𝐷3 is active.
𝐷3 𝑇4 : SC ← 0
Timing Diagram:
The timing diagram shows the time relationship of the control
signals.
The sequence counter SC responds to the positive transition of
the clock.
26
Name of Institution
Example of control timing signals 27
Timing and Control Name of Institution
• Initially, the CLR input of SC is active.
• The first positive transition of the clock clears SC to 0, which in turn
activates the timing T0 out of the decoder.
• T0 is active during one clock cycle.
• The positive clock transition labeled T0 in the diagram will trigger only
those registers whose control inputs are
• connected to timing signal T0.
• SC is incremented with every positive clock transition, unless its CLR
input is active.
• This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and
so on.
• If SC is not cleared, the timing signals will continue with T5, T6, up to
T15 and back to T0.
28
Instruction Cycle Name of Institution
A program stored in the memory unit of the computer consists
of a sequence of instructions.
In the basic computer each instruction cycle consists of
the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to
fetch, decode, and execute the next instruction. 29
Instruction Cycle Name of Institution
Fetch and Decode:
Initially PC is loaded with the address of the first
instruction in the program.
SC is cleared to 0 providing a decoded timing signal T0.
SC is incremented to 1 so that timing signals go through
𝑇0 through 𝑇15 .
30
Instruction Cycle Name of Institution
The microoperations for fetch and decode phases are:
𝑇0 :AR←PC
At 𝑇0 Transfers the address from PC to AR.
𝑇1 :IR←M[AR], PC ← PC+1
At T1, Instruction read from memory is placed in IR and PC is
incremented by 1 to get the address of next instruction.
𝑇2 :𝐷0 , 𝐷1 . . 𝐷7 ←Decode IR(12-14), AR←IR(0- 11), I←IR(15)
At 𝑇2 opcode in IR is decoded , Indirect bit is transferred to
flipflop I & address part is transferred to AR.
After decoding, next step is to determine the type of instruction.
31
Instruction Cycle Name of Institution
After decoding, timing signal active is T3 during which
instruction type is identified.
Memory Reference
If 𝐷7 =0 opcode will be 000 through 110
If 𝐷7 =0 and I=1,indirect and 𝐷7 =0 and I=0 direct
Microoperations for indirect address should be initially
AR←M[AR]
Register reference and Input-Output
If 𝐷7 =1 and I=0 – Register
If 𝐷7 =1 and I=1 – I/O
32
Instruction Cycle Name of Institution
Explanation:
Decoder output 𝐷7 is equal to 1 if the operation code is
equal to binary 111.
We determine that if 𝐷1 = 1, the instruction must be a
register-reference or input-output type.
If 𝐷7 = 0, the operation code must be one of the other seven
values 000 through 110, specifying memory -reference
instruction.
Control then inspects the value of the first bit of the
instruction, which is now available in flip-flop I
33
Instruction Cycle Name of Institution
If 𝐷7 = 0 and I = 1, we have a memory-reference
instruction with an indirect address.
It is then necessary to read the effective address from
memory.
The microoperation for the indirect address condition can
be symbolized by the register transfer statement
AR ← M [AR]
34
Instruction Cycle Name of Institution
The 3 instructions subdivided into 4 paths:
𝐷7 ’ I 𝑇3 : AR←M[AR] (Mem reference and indirect)
𝐷7 ’ I’ 𝑇3 : Nothing(Mem reference and direct)
r 𝐷7 I’ 𝑇3 : Execute register reference
p 𝐷7 I 𝑇3 : Execute IO instruction
35
Instruction Cycle Name of Institution
When a memory-reference instruction with I = 0 is
encountered, it is not necessary to do anything since the
effective address is already in AR.
However, the sequence counter SC must be incremented
when 𝐷7 ′ 𝑇3 = 1, so that the execution of the memory-
reference instruction can be continued with timing
variable 𝑇4 .
A register-reference or input-output instruction can be
executed with the clock associated with timing signal 𝑇3 .
After the instruction is executed, SC is cleared to 0 and
control returns to the fetch phase with 𝑇0 = 1. 36
Instruction Cycle Name of Institution
The timing signal that is active after the decoding is 𝑇3 .
During time 𝑇3 , the control unit determines the type of
instruction that was just read from memory.
The flowchart presents an initial configuration for the
instruction cycle and shows how the control determines
the instruction type after the decoding.
37
Name of Institution
38
Instruction Cycle Name of Institution
Note: Sequence counter (SC) is either incremented or
cleared to 0 with every positive clock transition.
We will adopt the convention that if SC is incremented,
we will not write the statement SC ← SC + 1, but it will
be implied that the control goes to the next timing signal
in sequence.
When SC is to be cleared, we will include the statement
SC ← 0
39
Register reference instruction
Name of Institution
When the register-reference instruction is decoded, 𝐷7 bit is set to 1.
▪ Each control function needs the Boolean relation, r = 𝐷7 𝐼 ′ 𝑇3
40
Memory-Reference Instructions
Name of Institution
Memory-reference instruction can be explained precisely
with the help of register-reference instruction.
When the memory-reference instruction is decoded,
D7 bit is set to 0.
This table lists seven memory-reference instructions;
41
Name of Institution
The effective address of the instruction is in the address
register, AR and was placed there during timing signal T2
when I = 0, or during timing signal T3 when I = 1.
The execution of the memory-reference
instructions starts with timing signal T4.
AND to AC
This performs the AND logic operation on pairs of bits in
AC and the memory word specified by the effective
address.
The result of the operation is transferred to AC.
𝐷0 𝑇4 : DR ← M[AR]
𝐷0 𝑇5 : AC ← AC ˄ DR, SC ← 0
42
Name of Institution
ADD to AC
This instruction adds the content of the memory word
specified by the effective address to the value of AC.
The sum is transferred into AC and the output carry
𝐶𝑜𝑢𝑡 is transferred to the E (extended accumulator) flip-
flop.
𝐷1 𝑇4 : DR ← M[AR]
𝐷1 𝑇5 : AC ← AC + DR, E ← 𝐶𝑜𝑢𝑡 , SC ← 0
43
Name of Institution
LDA: Load to AC
This instruction transfers the memory word specified by
the effective address to AC.
The microoperations needed to execute this
instruction are:
𝐷2 𝑇4 : DR ← M[AR]
𝐷2 𝑇5 : AC ← DR, SC ← 0
STA: Store AC
This instruction stores the content of AC into the memory
word specified by the effective address.
Since the output of AC is applied to the bus
and the data input of memory is connected to the bus, we
can execute this instruction with one microoperation.
𝐷3 𝑇4 : M[AR] ← AC, SC ← 0 44
Name of Institution
BUN: Branch Unconditionally
This instruction transfers the program to the instruction
specified by the effective address.
The BUN instruction allows the programmer
to specify an instruction out of sequence and we say that
the program branches (or jumps) unconditionally.
The instruction is executed with one microoperation:
𝐷4 𝑇4 : PC ← AR, SC ← 0
45
Name of Institution
BSA: Branch and Save Return Address
This instruction is useful for branching to a portion of the
program called a subroutine or procedure.
When executed, the BSA instruction stores the
address of the next instruction in sequence (which is
available in PC) into a memory location specified by the
effective address.
This operation can be specified with the
following register transfer:
M[AR] ← PC, PC← AR+1
M[135] ← 21, PC← 135+1=136
46
Name of Institution
Example to demonstrates how this instruction is used
It is not possible to
perform the operation
of the BSA instruction
in one clock cycle when
we use the bus system
of the basic computer.
To use the memory and
the bus properly, the
BSA instruction must
be executed with a
sequence of two
microoperations:
𝐷5 𝑇4 : 𝑀[𝐴𝑅] ← 𝑃𝐶, 𝐴𝑅 ← 𝐴𝑅 + 1
𝐷5 𝑇5 : 𝑃𝐶 ← 𝐴𝑅, 𝑆𝐶 ← 0 47
Name of Institution
ISZ: Increment and Skip if Zero
This instruction increment the word specified by the
effective address, and if the incremented value is equal to 0,
PC is incremented by 1 to skip the next instruction in the
program.
• Since it is not possible to increment a word inside the
memory, it is necessary to read the word into DR,
increment DR, and store the word back into memory.
This is done with the following sequence of
microoperations:
𝐷6 𝑇4 : DR ← M[AR]
𝐷6 𝑇5 : DR ← DR + 1
𝐷6 𝑇4 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
48
Name of Institution
Flowchart for memory-reference instructions 49
Input-Output and Interrupt
Name of Institution
Input-output configuration of basic computer
A computer can serve no useful purpose unless it
communicates with the external environment.
To exhibit the most basic requirements for input and
output communication, we will use a terminal unit with a
keyboard and printer.
The terminal sends and receives serial information and
each quantity of information has eight bits of an
alphanumeric code.
50
Input-Output and Interrupt
Name of Institution
Input-output configuration of basic computer
51
Input-Output and Interrupt
Name of Institution
• The serial information from the keyboard is shifted
into the input register INPR.
• The serial information for the printer is stored in the
output register OUTR.
• These two registers communicate with a
communication interface serially and with the AC in
parallel.
➢ The transmitter interface receives serial information
from the keyboard and transmits it to INPR.
➢ The receiver interface receives information from
OUTR and sends it to the printer serially.
52
Input-Output and Interrupt
Name of Institution
➢ The 1-bit input flag FGI for input and FGO for output
is a control flip-flop.
• If FGI is set to 1 when new information is available in
the input device and is cleared to 0 when the
information is accepted by the computer.
• The flag is needed to synchronize the timing rate
difference between the input device and the computer.
• The reverse case applies to FGO.
53
Input-Output and Interrupt
Name of Institution
The process of input information transfer:
• Initially, the input flag FGI is cleared to 0. When a key is
struck in the keyboard, an 8-bit alphanumeric code is shifted
into INPR and the input flag FGI is set to 1.
• As long as the flag is set, the information in INPR cannot be
changed by striking another key.
• The computer checks the flag bit; if it is 1, the information
from INPR is transferred in parallel into AC and FGI is
cleared to 0.
• Once the flag is cleared, new information can be shifted into
INPR by striking another key. 54
Input-Output and Interrupt
Name of Institution
The process of outputting information:
• The output register OUTR works similarly but the direction of
information flow is reversed.
• Initially, the output flag FGO is set to 1. The computer checks the
flag bit; if it is 1, the information from AC is transferred in parallel
to OUTR and FGO is cleared to 0.
• The output device accepts the coded information, prints the
corresponding character, and when the operation is completed, it
sets FGO to 1.
• The computer does not load a new character into OUTR when FGO
is 0 because this condition indicates that the output device is in the
55
process of printing the character.
Name of Institution
Input Output Instructions
• Input and output instructions are needed for transferring
information to and from AC register, for checking the flag bits,
and for controlling the interrupt facility.
• Input-output instructions have an operation code 1111 and are
recognized by the control when D7 = 1 and I = 1.
• The remaining bits of the instruction specify the particular
operation.
56
Name of Institution
The control functions and microoperations for the input-output
instructions.
𝑝𝐵11
𝑝𝐵10
𝑝𝐵9
𝑝𝐵8
𝑝𝐵7
𝑝𝐵6
Where, p = 𝐷7 I𝑇3
57
Interrupt Cycle Name of Institution
An interrupt is the interruption of normal sequence of
execution.
When interrupt processing is completed, execution resumes.
✓ Hardware implementation of Branch and Save Return address.
Working mechanism of Interrupt Cycle can be better
explained by the flowchart:
• Added to instruction cycle
• Processor checks for interrupt
- Indicated by presence of an interrupt signal
• If no interrupt, fetch next instruction 58
Interrupt Cycle Name of Institution
• If interrupt waiting:
- Suspend execution of current program.
- Save context. i.e. save the address of next
instruction to be executed (in current program) and
any other data relevant to processor’s current activity.
- Set PC to start address of interrupt handler routine
- Process the interrupt task
- Restore context and continue interrupted program
59
Interrupt Cycle Name of Institution
Flowchart for interrupt cycle
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Design of Accumulator Logic
Name of Institution
Circuits associated with Accumulator
61
Design of Accumulator Logic
Name of Institution
In order to design the logic associated with AC, it is necessary
to go over the register transfer statements and extract all the
statements that change the content of AC.
Operations associated with Accumulator
62
Design of Accumulator Logic
Name of Institution
Gate structure
for controlling
the LD, INR,
and CLR of AC
63
Design of Accumulator Logic
Name of Institution
One stage of Adder and Logic Circuit
64
Name of Institution
Thank You!
65