Name of Institution

Amity School of Engineering &

Technology
[Link]. CSE, Semester V
Computer Architecture Module - 3

1
 Name of Institution

Module – 3
Central Processing Unit

2
 Central Processing Unit
Name of Institution

The part of the computer that performs the bulk

of data processing operations is called the
Central Processing Unit (CPU).
Its purpose is to interpret instruction
cycles received from memory and perform
arithmetic, logic and control operations with data
stored in internal register, memory words and I/O
interface units.
The CPU is made up of three
major parts as shown in next slide. Additionally,
there is a BUS system for data inter-transfer.
3
 Central Processing UnitName of Institution

Register Set

Control Unit
Arithmetic Logic
Unit (ALU)
1. Register set stores the intermediate data used during the execution
of the instructions.
2. Arithmetic Logic Unit (ALU) performs the required
microoperations for executing the instructions.
3. Control unit supervises the transfer of information among the
registers and instructs the ALU as to which operation to perform. 4
 General Register Organization
Name of Institution

Types of CPU Organizations:

1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization
As memory access is the most time consuming operation in a
computer. It is more convenient and more efficient to store
these intermediate values in processor register.
When a large number of registers are included in the CPU, It is
most efficient to connect them through a common bus system.
5
 Name of Institution

Block Diagram 6
 General Register Organization
Name of Institution

The output of each register is connected to two multiplexers

(MUX) to form the two buses A and B.
The selection lines in each multiplexer
select one register or the input data for the particular bus.
The A and B buses form the inputs to a common arithmetic
logic unit (ALU).
The operation selected in the ALU
determines the arithmetic or logic microoperation that is to
be performed.
7
 General Register Organization
Name of Institution

The result of the microoperation is available for output data

and also goes into the inputs of all the registers.
The register that receives the information
from the output bus is selected by a decoder.
The decoder activates one of the register load
inputs, which provides a transfer of data between the output
bus and the inputs of the selected destination register.
The control unit that operates the CPU bus
system directs the information flow through the registers and
ALU by selecting the various components in the system. 8
 General Register Organization
Name of Institution

Example:
To perform the operation: R1← R2 + R3
the control must provide binary selection variables to the
following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic
addition A + B.
4. Decoder destination selector (SELD): to transfer the content of
the output bus into R1.
9
 Control Word Name of Institution

There are 14 binary selection inputs in the unit, and their

combined value specifies a control word.
▪ It consists of 4 fields.

SELA SELB SELD OPR

Control Word
▪ Three bits of SELA select a source register for the A input of the
ALU.
▪ The three bits of SELB select a register for the B input of the
ALU.
▪ The three bits of SELD select a destination register using the
decoder and its seven load outputs.
▪ The five bits of OPR select one of the operations in the ALU. 10
 Control Word Name of Institution
Encoding of the register selection fields

For SELA or SELB is 000, the corresponding multiplexer

selects the external input data.
For SELD = 000, no destination register is selected but the
contents of the output bus are available in the external output. 11
 Control Word Name of Institution
The ALU provides arithmetic and logic operation. In addition,
the CPU must provide shift operations.
OPR Select Operation Symbol
00000 Transfer A TSFA
Encoding of ALU
00001 Increment A INCA
Operations for the 00010 Add A + B ADD
CPU. 00101 Subtract A - B SUB
00110 Decrement A DECA
01000 ADD A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA 12
 Control Word Name of Institution

Example of Microoperation:
The subtract microoperation given by the statement
R1← R2 - R3

00101

13
 Control Word Name of Institution

Examples of microoperations for the CPU

14
 Stack Organization Name of Institution
Stack is a storage device that stores information in such a
manner that the last item stored is the first item retrieved.
Based on LIFO – Last-in-first-out.
✓ Stack in digital computers is a group of memory
locations with a address register that can count.
✓ The register that holds the address of top element of the
stack is called a Stack Pointer (SP).
The two operations of a stack are:
Push : Inserts an item on top of stack
Pop : Deletes an item from top of stack 15
 Register Stack Name of Institution

In digital computers, stack can be implemented in two ways:

• Register Stack
• Memory Stack
Register Stack:
Having limited stack depth and can be placed as a portion of large memory.

Implementation of push operation in sequence:

▪ SP←SP + 1 Increment stack pointer
▪ M[SP] ← DR Write item on top of the stack
▪ If (SP = 0) then (FULL ← 1) Check if stack is full
▪ EMTY ← 0 Mark the stack not empty
16
 Register Stack Name of Institution
Implementation of pop operation in sequence:
▪ DR←M[SP] Read item from top of the stack
▪ SP←SP-1 Decrement stack pointer
▪ If (SP = 0) then (EMTY← 1) Check if stack is empty
▪ FULL ← 0 Mark the stack not full

Stack pointer
contains 6 bits
∴ 26 = 64 address

Block diagram of
64-word stack
17
 Memory Stack Name of Institution

Memory Stack:
Stack depth is flexible.
Exist stand-alone or can be
implemented in RAM.
✓ Uses processor register as SP.

✓ The 3 registers are connected to

a common address bus.
✓ PC is used during fetch phase
✓ AR is used during execute phase
✓ SP is used to Push or Pop items
into stack 18
 Memory Stack Name of Institution

Push Operation – new item is inserted

SP←SP-1 Decrement stack pointer

M[SP]←DR Memory write operation

Pop Operation – new item is deleted

DR←M[SP] Read item from top of the stack

SP←SP+1 Increment stack pointer

19
 Instruction Formats Name of Institution
Computers usually have a variety of instruction code
formats.
The function of the control unit within the CPU is
to interpret each instruction code and provide the
necessary control functions needed to process the
instruction.
The format of an instruction is usually represented
by a rectangular box.
Instructions are a series of bits (0 and 1). The bits
of the instruction are divided into groups called fields. 20
 Instruction Formats Name of Institution
The most common fields found in instruction formats
are:
1. An operation code field that specifies the operation
to be performed.
2. An address field that designate a memory address or
a processor register.
3. A mode field that specifies the way the operand or the
effective address is determined.

21
 Instruction Formats Name of Institution
Computers may have instructions of several different
lengths containing varying number of address.
The number of address fields in the instruction
format of a computer depends upon the international
organization of its registers.
Types of CPU Organizations:
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization 22
 Instruction Formats Name of Institution
1. Single Accumulator Organization
This type of computer uses one address field.
ADD X AC ← AC+M[X]
2. General Register Organization
It uses two or three address fields in their
instruction format.
ADD R1, X R1 ← R1+M[X]
3. Stack Organization
Stack computer consists of op-code only with no
address.
e.g. - ADD
It can have PUSH or POP instructions that needs an
address field.
e.g. – PUSH X 23
 Instruction Formats Name of Institution

Based on the number of address fields used in the

instruction, instruction formats are classified into:

1. Zero-Address Instructions

2. One-Address Instructions

3. Two-Address Instructions

4. Three-Address Instructions

24
 Instruction Formats Name of Institution
Three-Address Instructions
Computers with three-address instruction formats
can use each address field to specify either a processor
register or a memory operand.
To evaluate a arithmetic expression X=(A+B)(C+D)
the following are the register transfer
operation of each instruction.
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 * R2

Advantage Disadvantage
results in short programs when Binary coded instructions require too
evaluating arithmetic expressions many bits to specify three addresses
25
 Instruction Formats Name of Institution
Two-Address Instructions
Most common in commercial computers.
Here, each address field can specify either a processor
register or a memory word.
The program to evaluate X = (A + B) (C + D)

MOV R1, A R1 ← M [A]

ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1 * R2
MOV X, R1 M [X] ← R1

26
 Instruction Formats Name of Institution
One-Address Instructions
It uses an implied accumulator (AC) register for all data
manipulation. The program to evaluate: X = (A + B) (C + D)

LOAD A AC ← M [A]
ADD B AC ← AC + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC * M [T]
STORE X M [X] ← AC

All operations are done between the AC register and

a memory operand. T is the address of a temporary memory
location required for storing the intermediate result. 27
 Instruction Formats Name of Institution
Zero-Address Instructions
A stack-organized computer does not use an address field
for the instructions ADD and MUL.
The PUSH and POP instructions, however, need an
address field to specify the operand that communicates with
the stack. TOS stands for top of stack
The program to evaluate: X = (A + B) (C + D)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A +B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C +D)
MUL TOS ← (C +D) * (A +B)
POP X M [X] ← TOS 28
 Addressing Modes Name of Institution

Computer use addressing mode for the purpose of

giving programming versatility to the user by
providing:
➢ indexing of data
➢ to reduce the no. of bits in the addressing field
➢ pointer to the memory
➢ program relocation

29
 Addressing Modes Name of Institution

Addressing modes can be divided into :

▪ Implied Mode
▪ Immediate Mode
▪ Register mode
▪ Register Indirect mode
▪ Autoincrement or Autodecrement Mode
▪ Direct Address mode
▪ Indirect Address mode
▪ Relative Address mode
▪ Indexed Address mode
▪ Base Register Addressing mode
30
 Addressing Modes Name of Institution

Implied mode
Operand is specified implicitly in the definition
of instructions.
Used for zero-address or one-address instruction
Example: Complement AC, Increment AC,

Implied mode is simple and gets executed faster as

instruction length is shorter. 31
 Addressing Modes Name of Institution

Immediate mode
• Operand is part of instruction
• Operand = address field
e.g. ADD 5
—Add 5 to contents of accumulator
—5 is operand
• No memory reference to fetch data

32
 Addressing Modes Name of Institution

Register mode
Operand is present in register named in address field.
Example : LD R1 AC ← R1
Instruction Registers

Opcode Register Address R

• EA = R
Operand
• Limited number of registers
• Very small address field needed
—Shorter instructions
—Faster instruction fetch
• No memory access
• Very fast execution
33
 Addressing Modes Name of Institution

Register Indirect mode

The selected register contains the address of the operand
rather than the operand itself.
• Large address space (2n)
• Example : LD (R1) AC ← M[R1]

34
 Addressing Modes Name of Institution

Autoincrement or Autodecrement Mode

It is a special case of register indirect addressing
mode.
➢ designed to efficiently access sequential data in
memory.

the content of the

register is automatically
incremented.

35
 Addressing Modes Name of Institution

Direct address mode

The address field of the instruction contains
the effective address of the operand.
Example : AC ← AC + [X]

36
 Addressing Modes Name of Institution

Indirect address mode

• The address field of the instruction specifies the
address of memory location that contains the
effective address of the operand.
• Two references to memory are required to fetch the
operand.
• Example : AC ← AC + [[X]]

37
 Addressing Modes Name of Institution

Relative address mode

the content of the program counter is
added to the address part of the instruction in order to
obtain the effective address.

Effective Address =
Content of Program Counter +
Address part of the instruction

effective address computation

for the relative address mode is
826 + 24 = 850 38
 Addressing Modes Name of Institution

Indexed address mode

the content of an index register is added to the
address part of the instruction to obtain the effective
address.
✓ index register is a special CPU register that
contains an index value.

Effective Address
= Content of Index Register +
39
Address part of the instruction
 Addressing Modes Name of Institution

Base register addressing mode

the content of an base register is added to the
address part of the instruction to obtain the effective
address.

Effective Address
= Content of Base Register +
Address part of the instruction 40
 Data Transfer and Manipulation
Name of Institution

The instruction set of different computers differ from

each other mostly in the way the operands are
determined from the address and mode fields.
Most computer instructions can be classified into
three categories:
1. Data Transfer Instructions
2. Data Manipulation Instructions
3. Program Control Instructions

41
 Data Transfer Instructions
Name of Institution

Data transfer instructions cause transfer of data from one

location to another without changing the binary
information content.
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP 42
 Data Transfer Instructions
Name of Institution

o Load instruction transfers the content of memory

location to a processor register, usually an accumulator.
o Store instruction transfers the content of a processor
register into memory.
o Move instruction transfer data from one register to
another, data transfers between CPU registers and
memory or between two memory words.
o Exchange instruction swaps information between two
registers or a register and a memory word.
o Input and Output instructions transfer data among
processor registers and input or output terminals.
o Push and Pop instructions transfer data between
processor registers and a memory stack.
43
 Data Manipulation Instructions
Name of Institution

Data manipulation instructions perform operations on

data and provide computational capabilities for the
computer.
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions

1. Arithmetic instructions:
The four basic arithmetic operations are addition,
subtraction, multiplication and division.
Arithmetic instructions may specify fixed-point
or floating-point data, binary or decimal data, single-
precision or double-precision data.
44
 Data Manipulation Instructions
Name of Institution

Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negate(2’s complement) NEG

45
 Data Manipulation Instructions
Name of Institution

(1) The increment instruction adds 1 to the value stored in a

register or memory word.
(2) The decrement instruction subtracts 1 from a value stored in a
register or memory word.
(3) The add, subtract, multiply, and divide instructions may be
available for different types of data. The execution of these
arithmetic operations is included in the definition of the operation
code.
(4) The Add with carry instruction performs the addition on two
operands plus the value of the carry from the previous computation.
(5) The Subtract with borrow instruction subtracts two words and
a borrow which may have resulted from a previous subtract
operation.
(6) The negate instruction forms the 2’s complement of a number,
effectively reversing the sign of an integer when represented in the
signed-2’s complement form. 46
 Data Manipulation Instructions
Name of Institution

2. Logical and bit Name Mnemonic

manipulation instructions:
Logical instructions Clear CLR
perform binary operations Complement COM
on strings of bits stored in AND AND
registers.
OR OR
By proper
application of the logical Exclusive-OR XOR
instructions, it is possible to Clear Carry CLRC
change bit values, to clear a Set Carry SETC
group of bits, or to insert
Complement Carry COMC
new bit values into operands
stored in registers or Enable Interrupt EI
memory words. Disable Interrupt DI
47
 Data Manipulation Instructions
Name of Institution

3. Shift instructions:
There are four types of shift instructions:
▪ Logical shift instructions
▪ Arithmetic shifts instructions
▪ Rotate instructions
▪ Rotate through carry instruction

48
 Data Manipulation Instructions
Name Mnemonic
Name of Institution

Logical shift right SHR

Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC

49
 Program Control InstructionsName of Institution

Each time an instruction is fetched from memory, the

program counter (PC) is incremented so that it contains
the address of the next instruction in sequence. After the
execution of a data transfer or data manipulation
instruction, control returns to the fetch cycle with the
program counter containing the address of the instruction
next in sequence.
On the other hand, a program control instruction,
when executed, may change the address value in the
program counter and cause the flow of control to be
altered.
In other words, program control instructions
specify conditions for altering the content of the program
counter. 50
 Program Control Instructions
Name of Institution

The change in value of the program counter as a result of

the execution of a program control instruction causes a
break in the sequence of instruction execution.

Instruction name Mnemonic

Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by Logical AND) TST
51
 Program Control Instructions
Name of Institution

• The Branch and Jump instructions are used interchangeably

to mean the same thing, but sometimes they are used to denote
different addressing modes. Branch and jump instructions may
be conditional or unconditional.
• The Skip instruction does not need an address field and is
therefore a zero-address instruction. A conditional skip
instruction will skip the next instruction if the condition is met.
• The Call and Return instructions are used, in conjunction with
subroutines.
• The compare and Test instructions do not change the program
sequence directly and does not retain the result of operation.
The compare instruction performs a subtraction between
two Operands.
The test instruction performs the logical AND of two
operands and updates status bits. 52
 Computer Instruction Set
Name of Institution

The design of the instruction set for the processor is an

important aspect of computer architecture. Early computers
had small and simple instruction sets to minimize the
hardware used to implement them.
As digital hardware became cheaper with the advent
of integrated circuits, computer instructions tended to increase
both in number and complexity.
According to their instruction set:
1. Complex Instruction Set Computer (CISC)
2. Reduced Instruction Set Computer (RISC)
53
 Computer Instruction Set
Name of Institution

Complex Instruction Set Computer (CISC)

Computers that can handle large number of
instructions.

Major characteristics of the CISC

• A large number of instructions typically from 100 to
250 instructions.
• Variable-length instruction formats.
• Some instructions that perform specialized tasks and
are used frequently.
• A large variety of addressing modes, typically from 5
to 20 different modes.
• Instructions that manipulate operands in memory.
54
 Computer Instruction Set
Name of Institution

Reduced Instruction Set Computer (RISC)

Computers which use fewer instructions with
simple constructs so they can be executed much faster
within the CPU without having to use memory as often.

Major characteristics of the RISC

• Relatively few instructions.
• Fixed-length instruction, can be easily decoded.
• Relatively few addressing modes.
• Memory access limited to load and store instructions.
• All operations done within the registers of the CPU.
• Single-cycle instruction execution.
• Hardwired rather than microprogrammed control.
55
 Computer ArithmeticName of Institution
Introduction:
Data is manipulated by using the arithmetic instructions in
digital computers.
Data is manipulated to produce results necessary to
give solution for the computation problems.
Basic arithmetic operations:
1. Addition
2. Subtraction
3. Multiplication
4. Division
To execute arithmetic operations there is a separate section
called arithmetic processing unit in CPU.
The arithmetic instructions are performed generally on
binary or decimal data. Fixed-point numbers are used to
represent integers or fractions. 56
 Computer ArithmeticName of Institution
Addition and Subtraction
Addition and Subtraction with Signed-Magnitude Data
Operation Add Subtract Magnitudes
Magnitudes
When A > B When A < B When A = B
(+ A) + (+ B) +(A + B)
(+ A) + (– B) + (A – B) – (B – A) + (A – B)
(– A) + (+ B) – (A – B) + (B – A) + (A – B)
(– A) + (– B) – (A + B)
(+ A) – (+ B) + (A – B) – (B – A) + (A – B)
(+ A) – (– B) +(A + B)
(– A) – (+ B) – (A + B)
(– A) – (– B) – (A – B) + (B – A) + (A – B)
57
 Computer ArithmeticName of Institution
Multiplication Algorithm
Multiplication of two binary numbers in signed-magnitude
representation is done by successive shift and add operation.

23 10111 Multiplicand
19 x 10011 Multiplier
10111
10111
00000
00000
10111____
437 110110101 Product

58
 Computer Arithmetic Name of Institution

Hardware for multiply operation

B reg for multiplicand

Q reg for multiplier 59
 Computer Arithmetic Name of Institution

Hardware for multiply operation

Registers Q and B are used to store multiplicand and
Multiplier, respectively, and register A store's partial
products during multiplication.
➢ As, Bs and Qs are flip-flops to store their sign bit.
➢ Flip flop E - stores carry bits generated.

The sequence counter(SC) at the beginning is set to a

number equal to the number of bits in the Multiplier, and
the counter is decremented by one after forming each partial
product.
The product begins and when the counter reaches
zero, the process stops.
60
Multiplicand B=10111 E A Q SC
Multiplier in Q
Computer Arithmetic
00000
Name of Institution
10011 101
0
𝑄𝑛 = 1; add B 10111
First partial product 0 10111
Shift right EAQ 0 01011 11001 100
𝑄𝑛 = 1; add B 10111
Second partial product 1 00010
Shift right EAQ 0 10001 01100 011
𝑄𝑛 = 0; shift right EAQ 0 01000 10110 010
𝑄𝑛 = 0; shift right EAQ 0 00100 01011 001
𝑄𝑛 = 1; add B 10111
Fifth partial product 0 11011
Shift right EAQ 0 01101 10101 000
Final Product in AQ = 0110110101 61
 Computer ArithmeticName of Institution
• We compare the signs of registers B(Bs) and Q(Qs) using the
functionality of XOR and output stored in As (the sign of A register).
Note: Initially, register A and E flip flops have a value 0. The
sequence counter is initialized with the value n, n is the number of
bits in the Multiplier.
• Now we check the least significant bit of Multiplier. Add the
multiplicand (register B) with the content of register A if it is 1. The
result is assigned in A register with a carry bit in flip flop E. Content of E
A Q is shifted to the right by one position, i.e., the content of E is shifted
to most significant bit (MSB) of A, and least significant bit of A is
shifted to the most significant bit of Q.
• If Qn = 0, only shift right operation on the content of E A Q is
performed similarly.
• Content of Sequence counter is decremented by 1.
• Check the content of the Sequence counter (SC) content; if it is 0, end
the process, and the final product is present in registers A and Q, or
repeat the process. 62
 Computer ArithmeticName of Institution
Division Algorithm:
Division of two binary numbers is done by successive
compare, shift and subtract operation.
The binary division is simpler than decimal because
the quotient is either 0 or 1.

63
 Computer ArithmeticName of Institution
Floating-Point Arithmetic Operations
Floating-point arithmetic is a method for representing real
numbers in a way that can support a wide range of values.
The term "floating-point" refers to the fact that a
number's decimal point can “float”.
This flexibility allows for the representation of very large and
very small numbers needed for scientific computations and
where the precision of calculations is essential.
There are two part of a floating-point number in a
computer - a mantissa m and an exponent e.
± 𝑚 × 𝑟𝑒
For example: The decimal number 537.25 is represented in a
register with m = 53725 and e = 3 and is interpreted to
represent the floating-point number.
0.53725 × 103 64
 Computer ArithmeticName of Institution
Normalization: A floating-point number is said to be
normalized, if the most significant digit of the mantissa in
non-zero.
It can be done by shifting the mantissa.
Example: 350 normalized
0035 not normalized

Registers for
Floating Point
Arithmetic ops.

65
 Computer ArithmeticName of Institution
Arithmetic operations with floating-point numbers
Addition
Subtraction
Multiplication
Subtraction

Floating point addition and subtraction

It can be divided into 4 steps:
1. Check for zeros
2. Align the Mantissa
3. Add or subtract the Mantissa
4. Normalize the result

66
 Computer ArithmeticName of Institution
1. Check for zeros:
Registers: AC & BR

Addition Case 1: AC=0 , BR=0.786

AC+BR=0+0.786
AC=0.786
Case 2: AC=0.786 , BR=0
AC+BR=0.786+0
AC=0.786
Subtraction Case 1: AC=0.786 , BR=0
AC-BR=0.786-0
AC=0.786
Case 2: AC=0 , BR= 0.786
AC-BR=0-0.786
AC= - 0.786 67
 Computer ArithmeticName of Institution
2. Align the Mantissa:
Registers: AC = 0.583123 × 103
BR = 0.123000 × 10−1
Case 1: -1 to +3
3-(-1)=4 Shift right operation
0.123000 × 10−1 → 0.000012 × 103

AC = 0.583123 × 103
BR = 0.000012 × 103 one bit lost (preferable)
Case 2: +3 to -1
3-(-1)=4 Shift left operation
0.583123 × 103 → 0.23000 × 10−1

AC = 0.23000 × 10−1 4 bits lost (not preferable)

BR = 0.123000 × 10−1 68
 Computer ArithmeticName of Institution
3. Add or Subtract the Mantissa:
AC = 0.583123 × 103
BR = 0.000012 × 103 one bit lost (preferable)

Addition: 0.583135 × 103

Subtraction: 0.583111 × 103

4. Normalize the result:

Addition: 0. 𝟓83135 × 103
Subtraction: 0. 𝟓83111 × 103
both values are normalized because MSB bit ≠ 0

69
 Computer ArithmeticName of Institution
Another example
Addition: 0.532 × 103
0.712 × 103
𝟏. 244 × 103
This is overflow
1. Perform ShR 2. Increment the exponent
= 0.1244 × 104
It is normalized as MSB=1

Subtraction: 0.532 × 103

0.521 × 103
0. 𝟎11 × 103 not normalized
This is underflow
1. Perform ShL 2. Decrement the exponent
= 0. 𝟏10 × 102 It is normalized as MSB=1
70
 Computer ArithmeticName of Institution
Floating point multiplication
It can be divided into 4 steps:
1. Check for zeros
2. Add the exponents
3. Multiplying the Mantissa
4. Normalize the result

BR = 0.12 × 104
QR = 0.23 × 103

Check for zeros:

BR=0 or BR≠ 0, QR=0, output will be zero
When BR≠ 0, QR ≠ 0 , then we can go for step 2 (Add exponents)

71
 Computer ArithmeticName of Institution
For BR = 0.12 × 104
QR = 0.23 × 103
Add the exponents: b=4, q=3
a=b+q=3+4=7

Multiplying the Mantissa

0.12
0.23
0.0276 × 107 not normalized
This is underflow
Solution: 1. Perform ShL 2. Decrement the exponent
= 0. 𝟐760 × 106 It is normalized as MSB=2

72
 Computer ArithmeticName of Institution
Floating point Division
It can be divided into 4 steps:
1. Check for zeros
2. Initialize registers and evaluate the sign
3. Align the dividend
4. Subtract the exponent
5. Divide the Mantissa

BR = 1.249 × 104
QR = 0.62 × 103
Check for zeros:
𝐴𝐶 𝐴𝐶
1. 𝐵𝑅 = 0 𝐵𝑅
=
0
𝐴𝐶 0
2. 𝐵𝑅 ≠ 0 , 𝐴𝐶 = 0 𝐵𝑅
=
𝐵𝑅
3. 𝐵𝑅 ≠ 0 , 𝐴𝐶 ≠ 0 , then proceed to step 2 73
 Computer ArithmeticName of Institution
Initialize registers and evaluate the sign
a= b XOR q

Align the dividend

BR = 1.249 × 104
After align = 0.124 × 105
QR = 0.62 × 103

Subtract the exponent b=5, q=3

a=b-q = 5-3 =2

Divide the Mantissa

0.124
= × 102 = 0.2 × 102
0.62
74
 Name of Institution

Thank You!

75