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8086
&
OTHER PROCESSORS

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Introduction
The main limitation of the 8-bit microprocessors were their low speed of execution, low
memory addressing capability, limited number of general-purpose registers and less power-
ful instruction set.

All these limitations of the 8-bit microprocessors tempted the designers to go for more
powerful processors in terms of advanced architecture, more processing capability, larger
memory addressing capability and a more powerful instruction set.

The 8086 was a result of such developmental design efforts.

Main Features of 8086:

1) 16-bit microprocessor

2) 16-bit ALU

3) Maximum clock frequency is 5 MHz

4) Maximum memory that can be connected is 1 MB

5) Address range of memory is from 00000 H – FFFFF H.

6) It requires a single + 5 V power supply

7) It has 20-bit address bus

8) It supports multiprogramming

Architecture of 8086
The complete architecture of 8086 as shown in Figure can be divided into two parts:

a) Bus interface unit (BIU) and

b) Execution unit (EU)

a) Bus Interfacing Unit (BIU).

The Bus interface unit is responsible for establishing communications with external devices
and peripherals including memory via the bus.

Bus interfacing unit perform following functions:

i) It sends instruction from memory.

ii) It reads data from port/memory.

iii) It writes data into port/memory.

iv) It supports instruction queuing.

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v) It provides the address relocation facility.

To implement these functions, the BIU contains segment registers, internal communication
register, instruction pointer, instruction object code queue, address summer and bus con-
trol logic.

BIU contains a dedicated adder which is used to generate a 20-bit Physical address that
is output on the address bus.

This address is formed by adding 20-bit segment address called Base address and 16 bit
offset address called Effective address.

BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write. These signals are needed for control of the circuits in the
memory and I/O sub-systems.

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b) Execution Unit (EU)

The Execution unit contains the register set of 8086 except segment registers and Instruc-
tion pointer.

It has a 16-bit ALU, able to perform the arithmetic and logic operation.

The execution unit may pass the results to the Bus interface unit for storing them in
memory.

The execution unit is responsible for decoding and executing all instructions. It consists of
an ALU, status and control flags, eight general purpose registers, temporary registers and
queue control logic.

Execution unit extracts instruction from the top of the queue in the BIU, decodes them,
generates operands address if necessary, passes them to BIU and requests it to perform
the read or write bus cycles to memory or I/O, and performs the operation specified by
the instruction on the operands.

During execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instructions.

If the queue is empty, the EU waits for the next instruction data to be fetched and shifted
to the top of the queue.

Both units operate synchronously to give 8086 an overlapping instruction fetch and in-
struction execution mechanism.

This parallel processing of BIU and EU eliminates the time needed to fetch many of the
instructions. This results in efficient use of the system bus and significantly improve sys-
tem performance.

Instruction Queue (IQ) and Pipelining.

There are 6 eight-bit registers in the instruction queue of 8086 as shown in Figure.

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Initially the program is prepared using the instruction in form of mnemonics.

Each mnemonics is then translated into Hexadecimal codes and stored into successive
memory location. Following steps took place when microprocessor executes the pro-
gramme:

1) Initially microprocessor will read, store six bytes of instructions codes in the six regis-
ters of instruction queue. This is called prefetching.

2) For Executing the instruction codes, microprocessor will read these codes from the reg-
isters of instruction queue in FIFO (first-in-first-out) sequence.

3) When two register of instruction queue becomes vacant, then in parallel with internal
operation, microprocessor will fetch two bytes of instruction codes in sequence and store
these codes in the vacant registers of instruction queue i.e. speed increases.

4) This method of prefetching instruction codes in advance in FIFO sequence is called as

pipelining.

5) If branching instruction comes in between, then all the six registers of instruction queue
are flushed or cleared to 0000 H and the new instruction codes are read from new
branching address.

Segmentation of memory used with 8086

8086 has 20 address pins, so each memory location connected with microprocessor will
have 20 bit or five hexadecimal digit address from 00000 H up to FFFFF H.

This actual address of 20 bit of each memory location is called as Physical Address (PA).
To select any one memory location, microprocessor has to transfer 20-bit physical address
(PA) of corresponding location on 20 address pins.

The memory connected with 8086 is divided into four memory segments. These memory
segments will be maximum of 64 K memory location.

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The 20-bit starting memory location address of each memory segment is called as Base
address (BA) of the corresponding memory segment.

The 4 LSB’s of each Base address should be always 0000 = 0 H and rest of the 16
MSB’s of Base address can be from 0000 H to FFFF H. These 16 MSB’s should be trans-
ferred to the corresponding segment register as given below:

1) Code Memory Segment (CMS).

Code memory segment is used to store only instruction codes of the program. For defin-
ing Base address of Code memory segment. we have to transfer the corresponding Base
address into Code segment register.

For example:

If address in CS is 1500 H, then Base address of the Code memory segment = 15000 H.

2) Data Memory Segment (DMS).

It is used to store data as well as result. For defining Base Address of Data Memory Seg-
ment, we have to transfer 16 MSB’s of the corresponding base address into Data segment
register.

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For example:

If 2500 H is transferred into DS, then Base address of Data Memory Segment = 25000 H.

3) Extra Memory Segment (EMS)

It is used to store data as well as result. For defining Base address of Extra Memory Seg-
ment, we have to transferred 16 MSB’s of the corresponding base address into Extra seg-
ment register.

For example:

If 4000 H is transferred into ES, then Base address of EMS = 40000 H

4) Stack Memory Segment (SMS)

It is used for storing stack of useful data using PUSH and POP instruction, for defining BA
of SMS, we have to transfer 16 MSB’s of the corresponding BA into Stack segment regis-
ter.

For example:

If 9164 H is transferred into SS, then Base address of Stack Memory Segment = 91640 H

The maximum memory capacity of 8086 is 1 M Byte but for a particular base address mi-
croprocessor can use maximum 4 blocks of 64 K.

These 4 memory segments can be completely isolated or there can be partially over-lap-
ping or there can be complete overlapping.

Processor status word (Flag register)

As shown in Figure PSW is a 16 bit register which contain 16 flip-flops but 7 flip-flop’s
are unused and rest of the flip-flops are called flags. Out of these 9 flags, there are 6
status flags (CF, P, AC, Z, S, OF) and rest of the three are controlling flags (DF, IF, TF).

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Status Flags. When microprocessor performs any operation in ALU, then depending upon
the status of result obtained in ALU, microprocessor will store corresponding status bit
into the flip-flops of these status flags.

a) Carry Flag.
When microprocessor performs addition of 8/16 bit number, then last carry bit is
copied in carry flag, when microprocessor performs subtraction of 8/16 bit number
thus additional borrow required is copied into Carry flag.

b) Auxiliary Carry (AC) flags.

When microprocessor performs addition of 8-bit number, then carry bit generated
after adding 4 LSB’s is copied into AC when microprocessor perform subtraction of
8-bit numbers, then borrow required to perform subtraction of 4 LSB’s is copied
into AC flag.

c) Parity (P) flag.

When microprocessor performs any arithmetic and logical operation of 8/16 bit
number, then the parity status of only 8 LSB’s is copied into Parity flag. If the par-
ity of LSB’s of result is Even/Odd, then P = 1/0 respectively.

d) Zero (Z) flag.

When microprocessor performs arithmetic and logical operation of 8/16 bit number,
then if 8 LSB’s /16 LSB’s of the result is zero i.e. 00 H/0000 H, then Z = 1. But if
8 LSB’s/16 LSB’s is non-zero, then Z = 0.

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e) Sign (S) flag.

When microprocessor performs arithmetic and logical operation of 8/16 bit number,
then the MSB sign bit of 8/16 bit LSB’s of the result is copied into Sign Flag. If re-
sult is correct signed binary number, then sign bit will indicate correct sign of that
result, i.e., if S = 1/0, then result is -ve/+ve respectively.

f) Overflow flag (OF).

If carry into MSB = carry out of MSB, then result will be in the range and so OF =
0.

Other Processers :

Microprocessor Bit

80186 16

80286 16

80386 32

80486 32