UNIT IV
INPUT-OUTPUT ORGANIZATION:
Input-Output Interface, Asynchronous data transfer, Modes of Transfer, Priority Interrupt,
Direct memory Access
PERIPHERAL DEVICES:
Input and output devices attached to the computer are also called peripherals.
Ex: keyboards, display units, and printers.
Peripherals that provide auxiliary storage for the system are magnetic disks and tapes. Peripherals are
electromechanical and electromagnetic devices of some complexity.
Monitor and keyboard: There are different types of video monitors, but the most popular use a cathode
ray tube (CRT). The CRT contains an electronic gun that sends an electronic beam to a phosphorescent
screen in front of the tube. The beam can be deflected horizontally and vertically.
A characteristic feature of display devices is a cursor that marks the position in the screen where the next
character will be inserted. The cursor can be moved to any position in the screen, to a single character,
the beginning of a word, or to any line. Edit keys add or delete information based on the cursor position.
The display terminal can operate in a single-character mode where the computer simultaneously.
Printer: Printer provides permanent record on paper of computer output data or text.
There are three basic types of character printers:
1. Daisy wheel
2. dot matrix, and
3. laser printers.
Daisy wheel: The daisywheel printer contains a wheel with the characters placed along the
circumference. To print a character, the wheel rotates to the proper position and an energized magnet
then presses the letter against the ribbon.
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dot matrix: The dot matrix printer contains a set of dots along the printing mechanism.
Example: A 5*7 dot matrix printer that prints 80 character per line has seven horizontal lines, each
consisting of 5*80=400 dots.
laser printers: The laser printer uses a rotating photographic drum that is used to imprint the character
images.
Magnetic tape: Magnetic tapes are used mostly for storing files of data. It is one of the cheapest and
slowest methods for storage and has the advantage that tapes can be removed when not in use.
Magnetic disks: Magnetic disks have achieved by moving a read-write mechanism to attract in the
magnetized surface. Disks are used mostly for bulk storage of programs and data.
INPUT – OUTPUT INTERFACE:
Input-output interface provides a method for transferring information between internal storage and
external I/O devices. Peripherals connected to a computer need special communication links for
interfacing them with the central processing unit. The purpose of the communication link is to resolve
the differences that exist between the central computer and each peripheral.
The major differences are:
1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is
different from the operation of the CPU and memory, which are electronic devices. Therefore, a
conversion of a signal values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and each must be controlled so as
not to disturb the operation of other peripherals connected to the CPU.
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To resolve these differences, computer systems include special hardware components between
the CPU and peripherals to supervise and synchronize all input and output transfers. These
components are called interface units.
I/0 Bus and Interface Modules:
The I/O bus consists of data lines, address lines, and control lines.
The magnetic disk, printer, and terminal are employed in practically any general-purpose computer.
The magnetic tape is used in some computers for backup storage.
Each peripheral device has associated with it an interface unit.
Each interface decodes the address and control received from the I/O bus, interprets them for the
peripheral and processor.
Each peripheral has its own controller that operates the particular electromechanical device.
The I/O bus from the processor is attached to all peripheral interfaces. To communicate with a
particular device, the processor places a device address on bus, an address decoder that monitors the
address lines.
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When the interface detects its own address, it activates the path between the bus lines and the device
that it controls. All peripherals whose address does not correspond to the address in the bus are
disabled by their interface.
I/O Commands: There are four types of commands that an interface may receive. They are classified
as control, status, data output, and data input.
1. Control command: A control command is issued to activate the peripheral and to inform it what
to do.
Example: A magnetic tape unit may be instructed to backspace the tape by one record, to rewind
the tape, or to start the tape moving in the forward direction.
2. Status: A status command is used to test various status conditions in the interface and the
peripheral.
Example: The computer may wish to check the status of the peripheral before a transfer is initiated.
3. Output data: A data output command causes the interface to respond by transferring data from the
bus into one of its registers.
4. Input data: The data input command is the opposite of the data output. In this case the interface
receives an item of data from the peripheral and places it in its buffer register.
I/O versus Memory Bus: There are three ways that computer buses can be used to communicate with
memory and I/O:
1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control line.
Example of I/O Interface:
It consists of two data registers called ports, a control register, a status register, bus buffers, and
timing and control circuits.
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MODES OF TRANSFER:
Data transfer to and from peripherals may be handled in one of three possible modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
Programmed I/O:
The programmed I/O method is particularly useful in small low-speed computers. An example of data
transfer from an I/O device through an interface into the CPU is shown in fig.
The device transfers bytes of data one at a time as they are available. When a byte of data is available,
the device places it in the I/O bus and enables its data valid line.
The interface accepts the byte into data register and enables the data accepted line. The interface sets a
bit (F or “flag” bit) in the status register.
The device can now disable the data valid line, but it will not transfer another byte until the data
accepted line is disabled by the interface.
A program is written for the computer to check the flag in the status register to determine if a byte has
been placed in the data register by the I/O device. This is done by reading the status register into a CPU
register and checking the value of the flag bit.
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If the flag is equal to 1, the CPU reads the data from the data register. The flag bit is then cleared to 0 by
either the CPU or the interface. Once the flag is cleared, the interface disables the data accepted line and
the device can then transfer the next data byte.
The transfer of each byte requires three instructions:
1. Read the status register.
2. Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.
3. Read the data register.
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Interrupt initiated I/O:
Why: Programmed I/O is a time consuming
process, so in order to keep CPU on a busy state
introduce an interrupt and special commands to
inform the interface to issue an interrupt request
signal to CPU, when data are available from the
device. In the meantime, the CPU can proceed to
execute another program.
When the device is ready for data transfer, it
generates an interrupt request to the computer.
When there is an external interrupt signal is
generated, the CPU will stops the execution of
the original program and branches to service
program to process the I/O transfer and then
returns back to the original program.
The CPU responds to the interrupt signal by
storing the return addresses from program
counter into a memory stack and then control
branches to a service routine that processes the required I/O transfer.
The way the processor chooses the branch address of the service routine varies from one unit to another.
There are two methods for using this:
1. Vectored interrupt
2. Non vectored interrupt
In a vectored interrupt, the source that interrupts supplies the branch information to the computer. This
information is called the interrupt vector.
In a Non vectored interrupt, the branch address is assigned to fixed location in memory.
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PRIORITY INTERRUPT:
A priority interrupt is a system that establishes a priority over the various sources to determine
which condition is to be serviced first when two or more requests arrive simultaneously.
Devices with high-speed transfers such as magnetic disks are given high priority, and slow devices
such as keyboards receive low priority.
A polling procedure is used to identify the highest-priority source.
Daisy-Chaining Priority:
The daisy-chaining method of establishing priority consists of a serial connection of all devices that
request an interrupt.
The device with the highest priority is placed in the first position, followed by lower-priority
devices up to the device with the lowest priority, which is placed last in the chain.
The interrupt request line is common to all devices and forms a wired logic connection.
If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level
state and enables the interrupt input in the CPU.
When no interrupts are pending, the interrupt line stays in the high-level state and no interrupts are
recognized by the CPU.
The CPU responds to an interrupt request by enabling the interrupt acknowledge line. This signal is
received by device 1 at its PI (priority in) input.
The acknowledge signal passes on to the next device through the PO ( priority output) output only if
device 1 is not requesting an interrupt.
If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing
a 0 in the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the data
bus for the CPU to use during the interrupt cycle.
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A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower priority
device that the acknowledge signal has been blocked.
A device that is requesting an interrupt and has a 1 in its PI input will interrupt the acknowledge
signal by placing a 0 in its PO output.
If the device does not have pending interrupts, it transmits the acknowledge signal to the next
device by placing a 1 in its PO output. Thus the device with PI=1 and PO=0 is the one with the
highest priority that is requesting an interrupt, and this device places its VAD on the data bus.
The daisy chain arrangement gives the highest priority to the device that receives the interrupt
acknowledge signal from the CPU.
The device sets its RF flip-flop when it wants to interrupt the CPU.
If PO=0, both PO and the enable line to VAD are equal to 0, irrespective of the value of RF.
If PI=1 and RF=0, then PO=1 and vector address is disabled. This condition passes the acknowledge
signal to the next device through PO. The device is active when PI=1 and RF=1.
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Parallel Priority Interrupt:
The parallel priority interrupt method uses a interrupt register whose bits are set separately by the
interrupt signal from each device. Priority is establishing according to the position of the bits in the
register.
Mask register purpose is to control the status of each interrupt request. The mask register can be
programmed to disable lower-priority interrupts while a higher-priority device is being serviced. It
can also provide a facility that allows a high-priority device to interrupt the CPU while a lower-
priority device is being serviced.
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Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four
inputs to a priority encoder. In this way, an interrupt is recognized only if its corresponding mask bit
is set to 1 by the program.
If IEN set to 1, indicates that the interrupt facility will be used while the current program is running.
If both IEN and IST are equal to 1, the CPU goes to an interrupt cycle.
The priority encoder generates two bits of the vector address, which is transferred to the CPU.
Priority Encoder:
The x’s in the table designate don’t-care conditions.
Input I0 has the highest priority; so regardless of the values of other inputs, when this input is 1, the
output generates an output xy=00.
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I1 has next priority level. The output is 01 if I1=1 provided that I0=0, regardless of the values of the
other two lower-priority inputs.
The output for I2 is generated only if higher-priority inputs are 0, and so on down the priority level.
The interrupt status IST is set only when one or more inputs are equal to 1. If all inputs are 0, IST is
cleared to 0 and the other outputs of the encoder are not used, so they are marked with don’t-care
conditions. This is because the vector address is not transferred to the CPU when IST=0.
DIRECT MEMORY ACCESS (DMA):
Definition: Removing the CPU from the path and letting the peripheral device manage the memory
buses directly would improve the speed of transfer. This transfer technique is called “direct memory
access (DMA)”.
During DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller
takes over the buses to manage the transfer directly between the I/O device and memory.
The bus request (BR) input is used by the DMA controller to request the CPU to relinquish control
of the buses.
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When this input is active, the CPU terminates the execution of the current instruction and places the
address bus, the data bus, and the read and write lines into a high-impedance state.
The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the
high-impedance state.
The DMA that originated the bus request can now take control of the buses to conduct memory
transfers without processor intervention.
When the DMA terminates the transfers, it disables the bus request line. The CPU disables the bus
grant, takes control of the buses, and returns to its normal operation. The transfer can be made in
several ways.
DMA burst transfer: A block sequence consisting of a number of memory words is transferred in a
continuous burst while the DMA controller is master of the memory buses.
cycle stealing: It allows the DMA controller to transfer on data word at a time, after which it must
return control of the buses to the CPU.
DMA Controller:
The unit communicates with the CPU via the data bus and control lines.
The registers in the DMA are selected by the CPU through the address bus by enabling the DS
(DMA select) and RS (register select) inputs. The RD (read) and WR (write) inputs are
bidirectional.
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The DMA controller has three registers: an address register, a word count register, and a control
register.
The address register contains an address to specify the desired location in memory. The address
bits go through bus buffers into the address bus. The address register is incremented after each word
that is transferred to memory.
The word count register holds the number of words to be transferred. This register is decremented
by one after each word transfer and internally tested for zero.
The control register specifies the mode of transfer.
The CPU initializes the DMA by sending the following information through the data bus:
1. The starting address of the memory block, where data are available (for read) or where data are
to be stored (for write).
2. The word count, which is the number of words in the memory block.
3. Control to specify the mode of transfer such as read or write.
4. A control to start the DMA transfer.
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DMA
Transfer:
When the peripheral device sends a DMA request, the DMA controller activates the BR line,
informing the CPU to relinquish the buses.
The CPU responds with its BG line, informing the DMA that its buses are disabled.
The DMA then puts the current value of its address register into the address bus, initiates the RD or
WR signal, and sends a DMA acknowledge to the peripheral device.
When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write)
or receives a word from the data bus (for read).
For each word that is transferred, the DMA increments its addresses register and decrements its
word count register.
If the word count register reaches zero, the DMA stops any further transfer and removes its bus
request.
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