Ch 5.

Synchronous sequential logic

 5.1 Introduction

 In order to perform useful or flexible sequences of operations, we

need to be able to construct circuits that can store information
between the operations.
 Latches_based on input changes and Flip-Flops_ based on the clock
signal
 Sequential circuits is consisting of both Flip-Flop and combinational
logic and outputs are function of inputs and present states
 Present states are supplied by memory elements

Figure 5.1 Block diagram of sequential circuit 2

 5.2 Sequential circuits with Synchronous

 Two types of sequential circuit

 Synchronous : behavior depends on the signals having the form of a
periodic sequence of clock pulses
 Asynchronous : behavior depends on input parameters without clock
pulses

Level trigger Rising edge trigger Falling edge trigger

Figure 5.2 Synchronous clocked sequential circuit

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 5.2 Sequential circuits with asynchronous
 Asynchronous : behavior depends on input parameters without clock pulses
 The change of internal state occurs when the input variables are changed.

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 5.3 Latches - SR latch with NOR gate

 Operation state – NOR gate

NOR Q(t+Δ) = R(t) NOR Q(t)
A B
0 0 1 Q(t+Δ) = S(t) NOR Q(t)
0 1 0 where, Δ is a very short time that can
1 0 0
1 1 0 operate even in the falling or rising
times like nano or pico sec.
SR NOR Latch
S(t) R(t) Q(t) Q(t) Q(t+Δ) Q(t+Δ) Q(t+2Δ) Q(t+2Δ) Q(t+3Δ) Q(t+3Δ)
0 0 0 1 0 1 0 1 0 1 S R Q(t+1) Q(t+1)
0 0 1 0 1 0 1 0 1 0 0 0 No change
0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 0 0 1 0 1 0 1 0 1
1 0 0 1 0 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1 0
1 1 0 1 0 0 0 0 0 0 1 1 Forbidden
1 1 1 0 0 0 0 0 0 0

Q(t+2Δ) = R(t) NOR Q(t+Δ) Q(t+3Δ) = R(t) NOR Q(t+2Δ)

Q(t+2Δ) = S(t) NOR Q(t+Δ) Q(t+3Δ) = S(t) NOR Q(t+2Δ)
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 5.3 Latches - SR latch with NAND gate

 Operation state – NAND gate

Q(t+Δ) = S(t) NAND Q(t)
A B NAND
0 0 1 Q(t+Δ) = R(t) NAND Q(t)
0 1 1
1 0 1 where, Δ is a very short time that can
1 1 0 operate even in the falling or rising
times like nano or pico sec.
SR NAND Latch
S(t) R(t) Q(t) Q(t) Q(t+Δ) Q(t+Δ) Q(t+2Δ) Q(t+2Δ) Q(t+3Δ) Q(t+3Δ)
0 0 0 1 1 1 1 1 1 1 S R Q(t+1) Q(t+1)
0 0 1 0 1 1 1 1 1 1
0 1 0 1 1 1 1 0 1 0 0 0 Forbidden
0 1 1 0 1 0 1 0 1 0 0 1 1 0
1 0 0 1 0 1 0 1 0 1
1 0 1 0 1 1 0 1 0 1 1 0 0 1
1 1 0 1 0 1 0 1 0 1 1 1 No change
1 1 1 0 1 0 1 0 1 0

Q(t+2Δ) = S(t) NAND Q(t+Δ) Q(t+3Δ) = S(t) NAND Q(t+2Δ)

Q(t+2Δ) = R(t) NAND Q(t+Δ) Q(t+3Δ) = R(t) NAND Q(t+2Δ)
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 5.3 Latches

 SR latch : consist of two cross-coupled NOR gates

Figure 5.3 SR latch with NOR gates

 S R latch with NAND gates : the complement value of NOR latch

Figure 5.4 S R latch with NAND gates

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 5.3 JK Flip/Flop

 Operation state –JK F/F with SR NOR Latch

YK ★ Let's set initial condition(I.C) for YK(t) and
K Q(t) YJ(t) are 0 to solve complexity. Therefore,
CP YK(t+Δ) = K(t) AND Q(t) = YK(t+2Δ) = K(t) AND Q(t+Δ)
YJ(t+Δ) = J(t) AND Q(t) = YJ(t+2Δ) = J(t) AND Q(t+Δ)
YJ Q(t)
J
Q(t+Δ) = YK(t) NOR Q(t) = Q(t)
Q(t+Δ) = YJ(t) NOR Q(t) = Q(t)
J(t) K(t) Q(t) Q(t) YK(t+Δ) YJ(t+Δ) Q(t+Δ) Q(t+Δ) Q(t+2Δ) Q(t+2Δ) YK(t+3Δ) YJ(t+3Δ) Q(t+3Δ) Q(t+3Δ) Q(t+4Δ) Q(t+4Δ)
0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1
0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1
0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1
1 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0
1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1
S R NOR Q(t+2Δ) = YK(t+Δ) NOR Q(t+Δ) Q(t+3Δ) = YK(t+2Δ) NOR Q(t+2Δ) J K Q(t+1) Q(t+1)
0 0 1 Q(t+2Δ) = YJ(t+Δ) NOR Q(t+Δ) Q(t+3Δ) = YJ(t+2Δ) NOR Q(t+2Δ) 0 0 No change
0 1 0 0 1 0 1
1 0 0 YK(t+3Δ) = K(t) AND Q(t+2Δ) Q(t+4Δ) = YK(t+3Δ) NOR Q(t+3Δ) 1 0 1 0
1 1 0 YJ(t+3Δ) = J(t) AND Q(t+2Δ) Q(t+4Δ) = YJ(t+3Δ) NOR Q(t+3Δ) 1 1 Toggle
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5.3 Flip/Flop- Truth, Characteristic Equation, Excitation Table

State table ( )
S R Q(t+1) Q(t+1) D Q(t+1) Q(t+1) J K Q(t+1) Q(t+1) T Q(t+1) Q(t+1)
0 0 No change 0 0 1 0 0 No change 0 No change
0 1 0 1 0 1 0 1 1
1 1 0 Toggle
1 0 1 0 1 0 1 0
1 1 Forbidden 1 1 Toggle

Characteristic Eq. Table ( )

S R Q(t) Q(t+1) D Q(t) Q(t+1) J K Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 1 0 0 0 1 1 0 1 1
0 1 0 0 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0
1 0 0 1 1 1 1 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0

Characteristic Eq. ( ) Excitation Table ( )

SR : Q(t+1) = S + R Q(t) Q(t) Q(t+1) S R J K D T
D: Q(t+1) = D 0 0 0 0 0 0
0 1 1 0 1 1 1
T: Q(t+1) = T  Q(t) 0 1 1 0 1
1 0
JK : Q(t+1) = J Q(t) + K Q(t) 1 1 0 0 1 0
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5.3 Latches - SR latch

 SR latch with control input

- Add two NAND gate and control signal(Enable input)
- En=0(no action and no change), En=1(act as SR latch with SR)

Figure 5.5 SR latch with control input

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5.3 Latches - D latch

 Eliminate indeterminate state in SR latch

- If En = 1, output value is equal to D

Figure 5.6 D latch

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5.3 Latches – Graphic symbols for latches

 Graphic symbols for latches

Figure 5.7 Graphic symbols for latches

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 5.4 Flip-Flops

 Latch : case (a), output changes as input changes

 Flip-flop : output only changes at clock edge
★If F/F is operated as level trigger, toggle is occurred continuously

Figure 5.8 Clock response in latch and flip-flop

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5.4 Flip-flops – Level, Rising-edge, Falling-edge Triggered Flip-Flop

 Clk=0 : master disable, slave enable

 Clk=1 : master enable, slave disable

Figure 5.9 Master–slave D flip-flop

Figure 5.11 Graphic symbol for edge-triggered D flip-flop

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 5.4 Flip-flops - Other Flip-Flop
Characteristic Eq. Table ( )
Excitation Table
S R Q(t) Q(t+1) D Q(t) Q(t+1) J K Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q(t) Q(t+1) S R J K D T
0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1
1 0 0 1 1 1 1 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1 1 0 0 1 1 0 1
1 1 0 1 1 0 1 1 1 0 0 1 0
1 1 1 1 1 1 0

- D F/F implementation using JK F/F

J map = D K map = D
D Q(t) Q(t+1) J K
Q Q
D Q(t) 0 0 0 0 D 0 1 D 0 1
0 1 0 1 0 0 0 1
Clk 1 0 1 1
Q(t)
1 1 1 0 1 1 1 0

- D F/F implementation using SR F/F

S map = D R map = D
D Q(t) Q(t+1) S R
Q(t) Q Q
D 0 0 0 0 D 0 1 D 0 1
0 1 0 0 1 0 0 0 0 1
Clk Q(t) 1 0 1 1 0
1 1 1 0 1 1 1 0 0
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 5.4 Flip-flops - Other Flip-Flop
Characteristic Eq. Table ( )
Excitation Table
S R Q(t) Q(t+1) D Q(t) Q(t+1) J K Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q(t) Q(t+1) S R J K D T
0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1
1 0 0 1 1 1 1 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1 1 0 0 1 1 0 1
1 1 0 1 1 0 1 1 1 0 0 1 0
1 1 1 1 1 1 0

- JK F/F implementation using D F/F J K Q(t) Q(t+1) D

0 0 0 0 0 D map = K Q + J Q
J Q(t) 0 0 1 1 1 KQ
0 1 0 0 0 J 00 01 11 10
Clk 0 1 1 0 0
K Q(t)
1 0 0 1 1 0 0 1 0 0
1 0 1 1 1
1 1 0 1 1 1 1 1 0 1
1 1 1 0 0
- SR F/F implementation using D F/F S R Q(t) Q(t+1) D
0 0 0 0 0 D map = S + R Q
0 0 1 1 1 RQ
S Q(t)
0 1 0 0 0 S 0001 11 10
Clk 0 1 1 0 0
1 0 0 1 1 0 0 1 0 0
R Q(t) 1 0 1 1 1
1 1 0 1 1 1
1 1 1
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 5.4 Flip-flops - Other Flip-Flop
Characteristic Eq. Table ( )
Excitation Table
S R Q(t) Q(t+1) D Q(t) Q(t+1) J K Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q(t) Q(t+1) S R J K D T
0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1
1 0 0 1 1 1 1 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1 1 0 0 1 1 0 1
1 1 0 1 1 0 1 1 1 0 0 1 0
1 1 1 1 1 1 0

- T F/F implementation using JK F/F

T Q(t) Q(t+1) J K J map = T K map = T
T Q(t) 0 0 Q Q
0 0 D 0 1 D 0 1
0 1 1 0 0 0
1 1
0 0
Clk 1 0
Q(t)
1 1 0 1 1 1 1 1

- T F/F implementation using D F/F

D map = T  Q
T Q(t) Q(t+1) D Q
T Q(t)
0 0 0 0 D 0 1
0 1 1 1 0 0 1
1 0 1 1
Q(t)
Clk 1 1 0 0 1 1 0
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 5.4 Flip-flops - Other Flip-Flop

 JK flip-flop
- Performs three operations
- Set(J), Reset(K), Complement(J=K=1)
- D=JQ′+K′Q

Figure 5.12 JK flip-flop

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5.4 Flip-flops - Other Flip-Flop

 T flip-flop
- Complementing flip-flop
- D=TQ′+T′Q

Figure 5.13 T flip-flop

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5.4 Flip-flops - Characteristic tables

 Flip-flop characteristic tables

Table 5.1 Flip-Flop Characteristic Tables

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5.4 D flip-flops with reset

Figure 5.14 D flip-flop with asynchronous reset

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 5.5 Analysis of clocked sequential circuit – State equation
 A sequential circuit is determined from input, output and present state
 Output, next state are a function of input and present state
 Specifies the next state and output as a function of the present state and inputs
 A(t+1)=Ax + Bx
 B(t+1)=A′x
 Y=(A+B)x′

Figure 5.15 Example of sequential circuit

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 5.5 Analysis of clocked sequential circuits - State table

 Time sequence table of inputs, outputs and flip-flop states

 Two types of state table exist
 Next state is derived by state equation A(t+1)=Ax + Bx
Table 5.2
State Table for the Circuit of Fig. 5.15 B(t+1)=A′x
Y=(A+B)x′
Table 5.3
Second Form of the State Table

First Final
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 5.5 Analysis of clocked sequential circuits - State diagram

 A kind of flow diagram

 Can be derived from state table
 State-circle, transition-line, I/O Input/Output
Table 5.2
State Table for the Circuit of Fig. 5.15 State

Figure 5.16 State diagram of the circuit

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 5.5 Analysis of clocked sequential circuits - Analysis with D flip-flops

 Input equation :
 State equation is equal to input equation

Figure 5.17 Sequential circuit with D flip-flop

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 5.5 Analysis of clocked sequential circuits - Analysis with JK flip-flops

 Determine the flip-flop input equations and then use the corresponding
F/F CE to determine the next-state values in the state table
 JK F/F Input equations
JA=B KA=Bx′
JB=x′ KB=A′x+Ax′

Figure 5.18 Sequential circuit with JK flip-flop

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 5.5 Analysis of clocked sequential circuits - Analysis with JK flip-flops

 State table and state diagram JA=B KA=Bx′

Table 5.4
JB=x′ KB=A′x+Ax′
State Table for Sequential Circuit with JK Flip-Flops

x x
x x
x x
x x
x x
x x
x x
x x Figure 5.19 State diagram of the circuit

First Final Second

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5.5 Characteristic Table and Characteristic Equation

Characteristic Eq. Table ( )

S R Q(t) Q(t+1) D Q(t) Q(t+1) J K Q(t) Q(t+1) T Q(t) Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 1 0 0 0 1 1 0 1 1
0 1 0 0 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0
1 0 0 1 1 1 1 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0

★ Another method : Substitute the input Equations into the F/F

characteristic equation to obtain the state Eqs.
Characteristic Eq. ( ) Q(t)
T : Q(t+1) = T  Q(t)
SR : Q(t+1) = S + R Q(t) T : A(t+1) = T  A(t)
D : Q(t+1) = D
T : Q(t+1) = T  Q(t) Q(t)
JK : Q(t+1) = J Q(t) + K Q(t)
JK : Q(t+1) = J Q(t) + K Q(t) JK : A(t+1) = J A(t) + K A(t)
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 5.5 Analysis of clocked sequential circuits - Analysis with T flip-flops

 Input equations and output equation

TA=B(t)x, TB=x, y=A(t)B(t)
 State equations are derived from characteristic equation
A(t+1)=TAA(t)′+TA′A(t), B(t+1)=TBB(t)′+TB′B(t)

Input
State/output

Figure 5.20 Sequential circuit with T flip-flops (Binary Counter) 29

 5.5 Analysis of clocked sequential circuits - Analysis with T flip-flops

 Input equations and output equation

TA=B(t)x, TB=x, y=A(t)B(t)
 State equations are derived from characteristic equation
A(t+1)=TAA(t)′+TA′A(t), B(t+1)=TBB(t)′+TB′B(t)
Table 5.5
State Table for Sequential Circuit with T Flip-Flops

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 5.7 State reduction and assignment

 State reduction is used to reduce the number of flip-flop

 Only input/output sequences are important
 Interested in present states that go to the same next state and have
the same output

Figure 5.25 State diagram Figure 5.26 Reduced State diagram

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 5.7 State reduction and assignment - State reduction

Table 5.6 State Table

Table 5.7 Reducing the State Table

Figure 5.25 State diagram

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 5.7 State reduction and assignment - State reduction

Table 5.8 Reduced the State Table

Figure 5.26 Reduced State diagram

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 5.7 State reduction and assignment - State assignment
 m states circuit, codes must contain n bits where 2ⁿ ≥ m
 Three possible binary state assignments
Table 5.9 Three Possible Binary State Assignments

Table 5.10 Reduced State Table with Binary Assignment 1

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 5.8 Design procedure

 Sequential circuit design : requires State Table

⇔ Combinational circuit : Truth Table
 The number of flip-flop is determined from the number of states in circuit
 If 2ⁿ states exist, there are n flip-flops
- 1 F/F ⇔ 2 state(0, 1), 4 F/F ⇔ 24 states(0000, ∙∙∙∙∙, 1111)
 Design steps
1) Derive a state diagram or state table
2) Reduce the number of states if necessary
3) Assign binary code to the state
4) Choose the type of flip-flops to be used
5) Derive the flip-flop input equations and output equations
6) Draw the logic diagram

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 5.8 Design procedure

 Derive a state diagram and assign state

- Sequential detector
- Detect a sequence of three or more consecutive 1’s in a string of bits
coming through an input line (i.e., the input is a serial bit stream)
Next state Output
Present
Implementation of state x = 0 x = 1 x = 0 x = 1
State table
S0 S0 S1 0 0
S1 S0 S2 0 0
S2 S0 S3 0 0
S3 S0 S3 1 1

Binary state assignments

S0 = 00 S1 = 01
Figure 5.27 State diagram
for sequence detector S2 = 10 S3 = 11
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 5.8 Design procedure

 Binary state assignments and state table

Binary state assignments : S0 = 00 S1 = 01 S2 = 10 S3 = 11

Table 5.11 State Table for Sequence Detector

Next state Output
Present
state x = 0 x = 1 x = 0 x = 1
00 00 01 0 0
01 00 10 0 0
10 00 11 0 0
11 00 11 1 1

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 5.8 Design procedure - Synthesis using D flip-flops

 Input equations are obtained directly from the next states

Table 5.11 State Table for Sequence Detector

Figure 5.28 K-Maps for sequence detector

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 5.8 Design procedure - Synthesis using D flip-flops

 logic diagram
DA = Ax + Bx, DB = Ax + B′x, y = AB

Figure 5.29 Logic diagram of a sequence detector

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 5.8 Design procedure - Excitation table
 Excitation Table : Input equations is evaluated from the present state to next state transition

Excitation Table Table 5.12 Flip-Flop Excitation Tables

Q(t) Q(t+1) S R J K D T
0 0 0 0 0 0
0 1 1 0 1 1 1
1 0 0 1 1 0 1
1 1 0 0 1 0

Table 5.13 State Table and JK Flip-Flop Inputs

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 5.8 Design procedure - Synthesis with JK flip-flops

 K-maps and logic diagram

Figure 5.31 Logic diagram for sequential

circuit with JK flip-flops

Figure 5.30 Maps for J and K input equations

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 5.8 Design procedure - Synthesis using T flip-flops

 3-bit binary counter

 3-bit counter has 3 flip-flops and can count from 0 to 2ⁿ-1(n=3)

Figure 5.32 State diagram of three-bit binary counter

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 5.8 Design procedure - Synthesis using T flip-flops

 State table and logic diagram

Table 5.14 State Table for Three-Bit Counter TA2 = A1A0, TA1= A0 TA0=1

Figure 5.34 Logic diagram of three-bit binary counter

Figure 5.33 Maps for three-bit binary counter

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