Department of Electrical and

Electronics Engineering

BITS Pilani Dr. Rahul Kumar,

Pilani Campus
Assistant Professor
 BITS Pilani
Pilani Campus

Semiconductor Fabrication Technology,

EEEF437
Lecture No. 13–17 (oxidation)
Fabrication Technology Steps

❖ Crystal Growth
❖ Wafer Cleaning
❖ Oxidation
❖ Epitaxy
❖ Diffusion
❖ Ion implantation
❖ Lithography
❖ Etching
❖ Metallization
❖ Packaging

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Introduction
• Oxidation: Because who doesn't want a little
more rust in their life? (Just not on their
electronics).

• Oxidation? Isn't that just rust?

• SiO2 and the Si/SiO2 interface are the principal reasons for silicon’s
dominance in the IC industry.
• No other known semiconductor/insulator combination has properties
that approach the Si/SiO2 interface.
• Si/SiO2 can be achieved by deposition or thermal oxidation.

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Introduction

➢ Dry oxidation

➢ Wet oxidation

• Seems very straightforward? devil is in the details.

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Properties

Selectively Etched

Excellent insulator ( > High breakdown field

1020 cm). (>107 V/cm)

Masks most common SiO2 Excellent junction

impurities passivation

Stable bulk Stable and

electrical reproducible
properties interface
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Properties of thermally grown SiO2

• Atomic density: 2.31022

• It is amorphous.
molecules/cm3
• Stable, reproducible and conformal SiO2
(For Si, it is 51022 atoms/cm3)
growth
• Refractive index: n=1.46
• Melting point: 1700C
• Dielectric constant: =3.9
• Density: 2.21 g/cm3 (almost the same as Si
which is 2.33 g/cm3) • Energy gap Eg=8-9 eV.
• Crystalline SiO2 [Quartz] = 2.65gm/cm3
Conformal
growth

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 The Si/SiO2 interface

Thermal oxide
(amorphous)

Si substrate
(single crystal)

• The perfect interface between Si and SiO2 is one major reason why Si
is used for semiconductor devices (instead of Ge…)
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Application of SiO2 in IC industry

STI

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Diffusion mask for common dopants

SiO2 can provide a selective mask against

diffusion at high temperatures. (DSiO2 << Dsi)
Oxides used for masking are 0.5-1μm thick.

(not good for Ga)

Can also be used for Mask thickness (m)

mask against ion
implantation

Diffusion time (hr)

SiO2 masks for B and P 10
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Use of oxide in MOSFET

Gate oxide, only ~0.8nm thick!

As an insulation material between

interconnection levels and adjacent devices

Interlayer Dielectric (ILD) LOCOS: local oxidation isolation; STI: shallow trench isolation
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Current Status: Dielectric Materials by
Application

Comparison Summary: Dielectric Materials by Application

Application Common Materials Key Goals
Gate dielectric HfO2, HfSiON, ZrO2, Al2O3 Reduce gate leakage current while
maintaining high capacitance.
Interconnect (ILD) Porous SiCOH, Nanoglass, Airgaps Reduce RC delay, power
consumption, and signal cross-talk.
Capping Layers LaOx (for NMOS), Al2O3 (for Precise control of threshold
PMOS) voltage.

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 Oxide Structure

Amorphous tetrahedral network

Basic structure of silica: a silicon atom

tetrahedrally bonds to four oxygen atoms

The structure of silicon-silicon dioxide interface:

some silicon atoms have dangling bonds.
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 Oxide Structure

Single crystal (quartz)

2.65 g/cm3

Amorphous (thermal
oxide?). 2.21 g/cm3

Devitrification: Crystallization of
amorphous SiO2 at process
temperature.
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 Thermal silicon oxidation methods

A three-tube horizontal
furnace with multi-zone
temperature control

• Wet oxidation using H2 and O2 is

Vertical furnace
more popular (cleaner) than using (not popular)
H2O vapor.
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 • Dry oxidation: It’s like a spa
day for your silicon—
relaxing and rejuvenating,
but a little steamy!

• Wet oxidation: It's like

Silicon going for a swim...
but instead of relaxing, it’s
getting a thick, protective
coat!

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 Thermal oxidation equipment

• The tubular reactor made of quartz or glass, heated by resistance.

• Oxygen or water vapor flows through the reactor and past the silicon wafers, with a typical
velocity of order 1cm/s.
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 Thermal oxidation in practice
1. Clean the wafers (RCA clean, very important)
2. Put wafers in the boat
3. Load the wafers in the furnace
4. Ramp up the furnace to process temperature in N2 (prevents oxidation from occurring)
5. Stabilize
6. Process (wet or dry oxidation)
7. Anneal in N2. Again, nitrogen stops oxidation process.
8. Ramp down

Rapid Thermal Oxidation (RTO): a recent practice

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Charge Associated with Si/SiO2 System

• Four charges are associated with

insulators and
insulator/semiconductor
interfaces.
• Qf - fixed oxide charge
• Qit - interface trapped charge
• Qm - mobile oxide charge
• Qot - oxide trapped charge

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 Thickness &
Quality
Measurements

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Surface Profilometry (Dektak):
thickness measurement
Oxide etched away by HF over part
of the wafer and a mechanical stylus
is dragged over the resulting step.
Stylus
Mirror image of stylus

stylus

Other techniques: AFM, STM, SEM, TEM, etc.

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Optical Measurements: Spectrophotometer

𝟐𝒏𝟏 𝒙𝒐 𝐜𝐨𝐬 𝜷
𝝀𝒎𝒊𝒏,𝒎𝒂𝒙 =
𝒎

𝒏𝒐 𝐬𝐢𝐧 𝝓
𝜷= 𝐬𝐢𝐧−𝟏
𝒏𝟏

• λ is varied while keeping Φ constant.

• Works very well for thickness greater than a few tens of nm.
• Refractive index (n1) should be known.
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Optical Measurements: Ellipsometry

• Works even for smaller thickness.

• Sometimes dielectric constant is not known precisely.
• Polarized light is used and change in polarization of
reflected light is measured.
• Can measure upto 1 nm.

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Optical Measurements: Ellipsometry

Very accurate (1nm accuracy)

Quarter
Light wave plate
source Filter Polarizer Analyzer Detector

Film being
measured
Substrate

• After quarter wave plate, the linear polarized light becomes circular polarized, which is
incident on the oxide covered wafer.
• The polarization of the reflected light, which depends on the thickness and refractive
index (usually known) of the oxide layer, is determined and used to calculate the oxide
thickness.
• Multiple wavelengths/incident angles can be used to measure thickness/refractive index
of each film in a multi-film stack.
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Thickness determination by looking the color

• Oxide thickness for constructive interference (viewed from above =0o) Xo=k/2n, n=1.46,
k=1, 2, 3…
• Our eye can tell the color difference between two films having 10nm thickness difference.
• Oxide smaller than 50 nm has no characteristic colour.
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 Electrical Measurement:
C-V of MOS
Small AC voltage is
applied on top of the DC
voltage for capacitance
measurement.

Substrate is N-type. Electron is majority

carrier, hole is minority carrier.
a. Accumulation: positive gate voltage
attracts electrons to the interface.
b. Depletion: negative gate bias pushes
electrons away from interface. No
charge at interface. Two capacitance in
series.
c. Inversion: further increase (negative)
gate voltage causes holes to appear at
the interface. 𝑸𝑮 = 𝑵𝑫 𝒙𝑫 + 𝑸𝑰
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Band Diagram

After Inversion, additional QG is balanced by QI and not by any QD.

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HF and LF CV curve

For low frequency, (minority) charge generation at the interface can follow the AC field to
balance the charge at the gate, so Cinv=Cox.
For high frequency, the gate charge has to be balanced by the carrier deep below the interface,
so Cinv-1 = Cox-1 + CSi-1.
Deep depletion: for high scanning speed (the DC voltage scan fast into large positive voltage),
depletion depth Xd must increase to balance the gate charge.
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Oxide charges measurement: Qf

• Qot and Qm will also show the similar shift.

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Oxide charges measurement: Qit

• HF and LF CV curve is
superimposed on each other.
• Dit don’t respond to the HF signal.
• Traps will behave as an additional C
in LF curve; hence ΔC will be
proportional to Dit.

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Oxide charges measurement: Qm

• Bias Temperature Stressing (BTS).

• Initial HF CV measurement.
• Heated at higher temperature under
applied DC bias.
• Cooled down and CV measured
• Heated at a higher temperature under
opposite polarity.
• Cooled down and CV measured
• Shift in CV curve gives the extent of
Qm.

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 Parameter from C-V measurement:
• Dielectric constant of Si & SiO2
• Capacitor area
• Oxide thickness
• Impurity profile in Si
• Threshold voltage of MOS capacitor
• Oxide charges

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IV measurement

• For thinner oxide, tunneling current can be measured.

• Dielectric breakdown strength of the oxide can be measured.
• Charge to breakdown or QBD.

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 How to minimize the charges in SiO2 and
Si/SiO2 interface?

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Origin of Oxide Charges

1. Interface Trapped Charges

• Possible origin: mechanical damage / broken bonds
• Takes part in the electronic activity

2. Fixed Oxide Charges (Positive charges)

• incomplete oxidation

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Origin of Oxide Charges (Contd.)

• Fixed Oxide Charges → unavoidable → can’t be discharged →

+ve →push the threshold voltage towards -ve
3. Oxide Trapped Charges → causes → HCE (Avalanche injection)
& radiation environment → e-h pairs (holes may get trapped)
4. Mobile Ionic Charges → sodium & potassium → +ve

Can be checked
through proper CV
analysis

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Defense against Qm

• Cleanliness in manufacturing: eliminating as many sources

of Na and K as possible

• Gettering: Na and K will segregate into phosphorus-doped

oxides

• Diffusion barriers: these contaminants diffuse much more

slowly through silicon nitride, which can thus be used as an
encapsulant to limit ambient contamination.

• Chlorine oxidation

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 Defense against Qm

• to remove/fix this mobile ionic impurity → chlorine oxidation

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Defense against Qm

Q. How does it help in fixing the mobile ions?

Ans: mobile ions: Na+ or K+ → sodium chloride and potassiumchloride

Fix the ions: no longer free to move

Cleanliness of the lab/system
No detrimental effect on electrical
performance

• Some more points on chlorine oxidation:

• Reduce oxidation induced stacking faults (OISF)

• Lifetime of the device
Broken Si bonds → interface to bulk
• Note: small quantity (less than 1015 cm-2) of Chlorine is beneficial
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 Defense against Qit

Q. Oxide trapped charges? After processing / device fabrication

Exception: ion beam etching

Problem: Spread all over the forbidden energy gap

Affect the electronic activity &

device performance

• Mostly due to dangling bonds

• Solution: post oxidation annealing in hydrogen at comparatively lower

temperature (4500C).
• Reacts with Si & satisfies the dangling bonds

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 Defense against Qf
Q. Fixed oxide charges? SiOx (incomplete oxidation) +ve

Recall the fabrication of

Hamper the Vth
enhancement nMOS
oxidation → at a very high
temperature, 12000C

the sample temperature is being

lowered

still oxidizing ambient is being

maintained.
Deal Triangle
Fixed oxide charges (1012 cm-2)
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 Cont..

• Q. What can be done to stop this incomplete oxidation process?

• At the end of the oxidation process

1. close the oxygen gas flow and create an inert ambient

(nitrogen or argon) & reduce the T.

2. It will stop the oxidation (no incomplete oxidation)

• At the end of the oxidation process → before taking out the samples → nitrogen
flushing for 15/20 minutes → to remove the traces of oxygen before the temperature is
lowered → fixed oxide charges < 1010 cm-2

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Different Usage Different Requirement

Different requirements

Mask Gate oxide

Thick oxide Thin oxide

Little worry about More Concern about

the quality the quality

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Volume Expansion during thermal oxidation
• It has to be a chemical reaction between silicon and oxygen
• In CVD, it can be done by Oxidation
• Substrate is reacting with the gas that is oxygen or steam or some
oxygen containing species and forming silicon dioxide.

• Si+O2 → SiO2

Si
Si

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 Cont..

• Silicon is being consumed in order to form the silicon dioxide.

Q. How much it is below and how much above?

Si + O2 SiO2
28 32 60

• 60 grams of silicon dioxide will be formed by consuming 28 grams of silicon

Volume * Density

𝑉𝑆𝑖𝑂2 × 𝜌𝑆𝑖𝑂2 = 60 𝑉𝑆𝑖 × 𝜌𝑆𝑖 = 28 𝑉𝑆𝑖𝑂2

28 = 2.2
60 𝑉𝑆𝑖
𝑉𝑆𝑖𝑂2 = 𝑉𝑆𝑖 =
2.27 2.33
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Thickness expansion

A x tox x ρSiO2 → WSiO2 A x tSi x ρSi → WSic

𝑡𝑆𝑖𝑂2
= 2.2
𝑡𝑆𝑖

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 Cont..

• One expression for the silicon thickness that is consumed

• One expression for the oxide thickness that is grown
tSi 28 A 2.27
=  = 0.45
tox A 2.33 60

• if 1000 A0 of silicon dioxide is grown → consumed 450 A0 of silicon

SiO2 550A0
450A0

Si
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 Oxidation

Methods

Chemical Anodic Thermal

Methods oxidation oxidation

Boil silicon in Electrolytic bath VLSI Technology

nitric acid (HNO3)

Quality is the best

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Thermal Oxidation Si
silicon sample

Oxide growth
put inside furnace
Left of the
Raise furnace temperature interface
Si

allow either oxygen or

water vapour to flow
oxidizing
species move in
silicon will react either with oxygen or
with water to form silicon dioxide.
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Cont..
Si + O2 = SiO2 Dry
Si + 2H2O = SiO2 + 2H2 Wet
Oxygen species or oxidant Either oxygen or water vapour

Note: during thermal

oxidation process

the oxidizing species

move inside

The interface will not be move through the oxide

affected by contamination layer and reacts with the
silicon at this interface.
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 Kinetics of oxidation

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Kinetics of oxidation: Deal & Grove
Model
C*= concentration of
oxidising species in oxide
Equilibrium with PG.

Three sequential steps are

needed for oxidation.

CG = concentration of oxidising species in gas

CS = concentration of oxidising species next to gas oxide interface
Co = concentration of oxidising species at outer oxide surface
Ci = concentration of oxidising species at the inner oxide surface
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 Cont..
F1 = Flux of the oxidising species in the bulk of the gas

From the bulk of the gas right next to the oxide gas interface

F1 α (CG – CS)
F1 = hG (CG –CS)

hG: Proportionality constant/ gas phase mass transfer coefficient

Gas law: PV = kT

ℎ𝐺
𝐹1 = (𝑃𝐺 − 𝑃𝑆 )
𝑘𝑇

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 Cont..

Henry’s Law: in equilibrium the concentration of a species within a solid

is proportional to the partial pressure of that species in the surrounding
gas.
C* = HPG H = Henry’s constant
Co = HPS
Rewrite equation (1)

h G ( C* −Co)
F1 =
HkT
h is very large. F1 = h (C − Co )
*
(5)
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Cont..

F2 is related to the movement of the oxidizing species through the

existing oxide layer.
𝜕𝐶 𝐶0 − 𝐶𝐼 (6)
𝐹2 = 𝐷 =𝐷
𝜕𝑥 𝑥
F3 is related to the reaction of silicon with the oxidizing species

availability of the oxidizing species at the

oxide silicon interface

F3 = KSCi (7)

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 Cont..

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 Cont..

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 Cont..

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 Cont..

[9]

[8]

What is physical significance of these equations?

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 Cont..

Case 1: D→∞ or x→0 x/D very small

The concentration of oxidizing species is
same from the outer surface to the inner
surface

reaction limited

Case 2: x→∞ CI→0

Not enough oxidizing species can reach to the
interface, diffusion coefficient tending to be
zero is same if x→∞

Diffusion limited
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 Growth Rate

Si + O2 = SiO2 Dry
Si + 2H2O = SiO2 + 2H2 Wet

• one molecule of silicon reacts with one molecule of oxygen to give

one molecule of silicon dioxide
• one molecule of silicon is going to react with two molecules of water
to give one molecule of silicon dioxide

N1 = no. of oxidant molecules per unit vol. of oxide

For O2 = 2.2 x 1022

For H2O = 2 x 2.2 x 1022

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 Cont..

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 Cont..

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 Cont..

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 Cont..

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 Cont..

Case II: t → ∞
x = Bt Parabolic growth

for any oxidation process → two rate constants associated with this.

Linear rate constant

Parabolic rate constant

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Extraction of Linear/Parabolic Rate
Constant Empirically
𝑥𝑜2 𝑥𝑜 𝑥𝑜 1 𝑡+𝜏 𝒕+𝝉
+ =𝑡+𝜏 + = 𝒙𝒐 = 𝑩 −𝑨
𝐵 𝐵 Τ𝐴 𝐵 𝐵Τ𝐴 𝑥𝑜 𝒙𝒐

𝑦 = 𝑚𝑥 + 𝐶

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 Oxidation Rate Constants

Temp (0C) Type A (μm) B (μm2/hr) B/A (μm/hr)

920 Wet 0.5 0.203 0.406
Dry 0.235 0.005 0.021
1200 Wet 0.05 0.72 14.4
Dry 0.04 0.045 1.12

𝟐𝑫𝑪∗ C* = 5.2 x 1016 (Dry) 𝒌𝒔 𝑪∗

𝑩= 𝑩ൗ =
𝑵𝟏 = 3.0 x 1019 (Wet) 𝑨 𝑵𝟏

N1 is larger for wet oxidation to grow one molecule of silicon dioxide, we

needed two molecules of water
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Fast Rate in Wet Oxidation?

Wet oxidation → faster growth rate

Why? 𝒌 𝑪∗
𝟐𝑫𝑪∗ N is larger for wet oxidation 𝑩ൗ = 𝒔
𝑩= 1 𝑨 𝑵𝟏
𝑵𝟏
to grow one molecule of silicon dioxide
we needed two molecules of water

N1 large → B small → still high oxidation rate for wet oxidation??

But the equilibrium concentration (C*) of the oxidizing species for wet
oxidation (5x1019) → three order higher than dry oxidation (5.2x1016)

B is much higher → wet oxidation

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 Cont..
Grow thicker oxide → grow it using steam ambient
B/A
B
9200 12000
9200 12000
0.406 14.4
0.203 0.72 KS
D
Reaction rate
Experimentally found: both B and B/A are well described by Arrhenius expressions
−𝐸1ൗ
𝐵= 𝐶1 𝑒 𝑘𝑇 𝐵ൗ = 𝐶 𝑒 −𝐸2ൗ𝑘𝑇
𝐴 2
Dry → 1.24 eV
E1 → Activation Energy Experimental Data
Wet → 0.7 eV
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Oxide Growth Graph: Calculated

Dry Oxidation Wet Oxidation

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 Cont..

• Both of them will exhibit the famous linear parabolic relationship.

• Wet oxidation → much thicker oxide
• Growth rate is higher for higher temperature.
• The experimental curve of dry oxidation is not passing through the origin
• Some xi at t=0
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Fallacy of Deal-Grove Model

• Only problem → when you grow thin oxide through dry oxide
Fails to predict.
• Explanations: Coupled diffusion of O2- with holes.

Initially, the oxide growth rate is much

faster than predicted by Deal & Grove
x

~270A0

time

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Substrate Orientation Effect

• (1 1 1) oriented crystal → higher rate of oxide growth than → the (1 0 0) oriented

crystal

• (1 1 1) oxidized faster → more number of atoms per unit area

• In the linear region → oxidation depends on reaction rate Widely

spaced
• In the parabolic region → oxidation depends on diffusion Closely
spaced

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Substrate Doping Effect

• Whether oxidation rate depends on doping?

• heavily doped with boron (p+) → oxidizes faster →
Diffusion of oxidizing species is faster

• heavily doped with phosphorous (n+) → Reaction rate of

oxidizing species is faster

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 Dopant Redistribution

• Silicon is doped either p-type or n-type, moderately or heavily →

carry out the oxidation → What happens to the impurity?

CSi: Equilibrium concentration of dopant in silicon 𝑪𝑺𝒊

CSiO2: Equilibrium concentration of the dopant in SiO2 𝑲=
𝑪𝑺𝒊𝑶𝟐
Either K<1 or >1

• Another factor → how fast the dopant can diffuse through oxide?

• Mask → SiO2 blocks the movement of dopants → Diffuse slowly through the
SiO2.

• Exception: Ga → diffuse very fast → not preferred as p-type doping

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Cont..
Two facts to consider while oxidising doped Si

Segregation coefficient Dopant diffuses fast or slow

(a) (b) (c) (d)

K<1 K<1 K>1 K>1
Slow Fast Slow Fast

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 Cont..

equilibrium concentration is more in

• Case I: K < 1 SiO2 than in Si
• Eg: ‘B’ → slow diffuser through SiO2 → preferably go into SiO2
1. Si side → B concentration is less than on the SiO2 side
2. Near Si-SiO2 interface → there is a depletion of B

1. B profile inside the SiO2 → concentration high

(K<1)
2. Stay constant → slow diffuser → then it falls

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 Cont..

• Case II: K < 1 & Fast diffuser

• A practical example → boron in a hydrogen ambient.
then boron can diffuse fast through silicon dioxide.
• normal boron diffusion is never done in hydrogen
ambient, but always in oxygen or nitrogen ambient

• Case III: K > 1 & Slow diffuser

• Eg → ‘P’ → reason for common n-type dopant

• Pile-up of phosphorous in Si side

• SiO2 side → same story as of Case I

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Cont..
• Case IV: K > 1 & Fast diffuser
• Eg → Ga
• Point→ instead of pile-up, it falling in Si side -interface

Ga is an extremely fast diffuser.

There is no chance for gallium to pile up

at the interface, it just diffuses out.

forced out through the oxide. just falls

drastically

draws the gallium out from

this interface region

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 Cont..

• Oxide thickness problems → heavily p-type and a heavily n-type silicon

• Eg.1: Si with heavily Phosphorous doped (n+)

Case III → pile-up

• thermal oxidation → inwards.
• heavily phosphorus piled up region → getting oxidized
• This affects the reaction rate.
• modifying the quality of this region.
• the oxidation process is governed by the reaction rate
• you can expect a thicker oxide growth.

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Cont..

• Eg.2: Si with heavily Boron doped (p+)

Case I

• Boron has preferentially come inside the oxide.

• increased presence of boron in SiO2 → affect the diffusion of the
oxidizing species through the oxide.
• aid in the diffusion of the oxidizing species → silicon dioxide, which
is heavily boron doped.
• silicon wafer → faster oxide growth rate

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Effect of PG

• To avoid contamination → the furnaces, the tubes → made of quartz

Two options

Pass pure oxygen Pass steam

Suppose requirement is to grow thick oxide.

increase the temperature increase the time of oxidation

Range 900-12000C Amorphous SiO2 → desired

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 Cont..
• High temperature → thermal stress → & → amorphous oxide can get
devitrified • > 1μm
• The process of crystallization

• Instead of amorphous → poor quality crystalline SiO2 → neither good for masking nor
useful for isolation

• Challenge: How to grow good quality thicker oxide?

𝐵ൗ = 𝐶∗ 2𝐷𝐶 ∗
𝐴
𝑁1 1ൗ𝑘 + 1ൗℎ
𝐵=
𝑠
𝑁1
Oxidation under higher oxygen pressure

𝑪∗ = 𝑯𝑷𝑮
Both rate constants increases

EEE F437 85 BITS Pilani, Pilani Campus

Cont..

• Three parameters to play: temperature, time, and pressure

• By increasing the P → afford to cut down either the T or the time

• Thermal stress, budget, cost, electricity

EEE F437 86 BITS Pilani, Pilani Campus

 Summary
• Thermal oxidation has been a key element of silicon technology since its inception.
• Thermally, chemically, mechanically and electrically stable SiO2 layers on silicon
distinguish silicon from other possible semiconductors.
• Si/SiO2 system contains 4 types of charges. They can severely affect the device
operation. They can be measured. They can be minimized by process innovations.
• Deal-Grove model: The basic growth kinetics of SiO2 on silicon are controlled by
oxidant diffusion and Si/SiO2 interface chemical reaction. Oxidation process has two
rate constants: linear and parabolic.
• Doping, orientation, thickness, etc. affect the oxidation process.
• Process simulators today include all these physical effects (and more) and are quite
powerful in predicting oxidation geometry and properties.
EEE F437
87 BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Thank You

BITS Pilani, Pilani Campus