Module 1 [8L] – Computer Organization
Detailed Notes
1. Introduction to CPU and Concepts of ALU [2L]
The Central Processing Unit (CPU) is the core component of a computer responsible for
interpreting and executing most commands from the computer's other hardware and
software. It contains three main parts:
- Control Unit (CU): Directs the flow of data and instructions.
- Arithmetic Logic Unit (ALU): Executes all arithmetic and logical operations.
- Registers: Temporary storage areas for instructions and data.
ALU performs operations like addition, subtraction, logical comparisons (AND, OR, NOT,
etc.).
2. Instruction Format and Instruction Cycle [1L]
Instruction Format:
Each instruction has:
- Opcode: The operation to perform.
- Operands: The data to process.
- Addressing Mode Bits: How to interpret operands.
Instruction Cycle:
1. Fetch: Get instruction from memory.
2. Decode: Interpret the instruction.
3. Execute: Carry out the command.
4. Store: Write result back to memory/registers.
3. Addressing Modes [1L]
Addressing Modes determine how operands are accessed.
- Immediate: Operand is part of instruction.
- Direct: Address of operand is specified.
- Indirect: Address points to another memory location.
- Register: Operand is in a register.
- Register Indirect: Register holds address of operand.
- Indexed: Base + index gives address (useful for arrays).
- Relative: PC + offset (used for branching).
4. Fixed-Point Multiplication – Booth's Algorithm [2L]
Booth’s algorithm is a technique for multiplying binary numbers in 2’s complement form.
Steps:
1. Append a 0 to multiplier.
2. Check bits:
- 10 → Subtract multiplicand.
- 01 → Add multiplicand.
- 00/11 → No operation.
3. Arithmetic right shift.
4. Repeat for each bit.
Advantages:
- Handles both positive and negative numbers.
- Efficient for long runs of 1s.
5. Fixed-Point Division – Restoring and Non-restoring Algorithms [1L]
Restoring Division:
1. Shift and subtract divisor.
2. If result negative, restore previous remainder.
3. Record quotient bit.
Non-Restoring Division:
1. Shift and subtract/add without restoring.
2. Final correction at the end.
3. Faster than restoring division.
6. Floating-Point Representation – IEEE 754 Format [1L]
IEEE 754 Single Precision (32-bit):
- Sign bit (1): 0 = positive, 1 = negative.
- Exponent (8): Stored with bias (127).
- Mantissa (23): Fractional binary part.
Value = (-1)^S × 1.M × 2^(E - Bias)
7. Floating-Point Arithmetic Operations [1L]
Addition/Subtraction:
- Align exponents, add/subtract mantissas, normalize.
Multiplication:
- Add exponents, multiply mantissas, normalize.
Division:
- Subtract exponents, divide mantissas, normalize.
Caveats:
- Rounding errors, Overflow/Underflow, Precision loss.