Module III
Cortex M processor Interfacing
KL25Z128VLK4 Pin-out
System Clock Gating Control Register 5
(SIM_SCGC5) is used to enable the clock
source for the I/O port circuitry among other
things
• Port Data Output Register (GPIOx_PDOR)
Direction Register in Freescale ARM
• Direction Register in Freescale ARM
• For example, by writing 0x03 (00000011 in binary) into the GPIOA_PDDR register, pins 0
and 1 of PORTA become outputs while the other pins become inputs
PORTx_PCRn (Portx
Pin Control) special
function register allows
us to program a pin to
be used for a given
alternate function
LED Interfacing
Toggling LEDs in Freescale FRDM
board in C
To toggle the green LEDs of the FRDM
board, the following steps must be
followed.
1) enable the clock to PORTB, since
access is denied to the port registers
until the clock is enabled,
2) configure PortB_PCR19 (Pin Control
Register) to select GPIO function for
PTB19,
3) set the Direction register bit 19 of
PTB as output,
4) write HIGH to PTB19 in data
register,
5) call a delay function,
6) write LOW to PTB19 in data register,
7) call a delay function,
8) Repeat steps 4 to 7
C program of LED interfacing
Register Address Definitions
Main function
Reading a switch in Freescale FRDM board
The contents of the PORTA_PCR1 register for PTA1 to use
PTA1 pin as input connected to SW. Use the pull-up resistor.
To read a switch on PTA1 and display it on the LED on PTB19, the following
steps must be taken.
1) enable the clock to PORTB,
2) configure PTB19 as GPIO in PORTB_PCR19 register,
3) make PTB19 output in PDDR register,
4) enable the clock to PORTA,
5) configure PTA1 as GPIO and enable the pull-up resistor in PORTA PCR1
register,
6) make PTA1 input in PDDR register,
7) read switch from PORTA,
8) if PTA1 is high, set PTB1
9) else clear PTB1
10) Repeat steps 7 to 9.
Seven-segment LED interfacing and
programming
For example, if we want to display number 25 on the 7-seg LED, the
following steps should be used:
1) enable the system clock to PORTD and PORTE,
2) Configure Port D as output port to drive the segments,
3) Configure Port E as output port to select the digits,
4) Write the pattern of numeral 2 from Table 2-7 to Port D,
5) Set the PTE1 pin to HIGH to activate the tens digit,
6) Delay for some time,
7) Write the pattern of numeral 5 from Table 2-7 to Port D,
8) Set the PTE0 pin to HIGH to activate the ones digit,
9) Delay for some time,
10) Repeat from step 4 to 9.
Program Description
Clock Enable for Ports
Port D GPIO Configuration
Port E GPIO Configuration
Infinite
Loop
Delay
LCD Interfacing
1. The LCD’s data pins are connected to PORTD of the microcontroller.
2. The LCD’s RS pin is connected to Pin 2 of PORTA of the microcontroller.
3. The LCD’s R/W pin is connected to Pin 4 of PORTA of the microcontroller.
4. The LCD’s E pin is connected to Pin 5 of PORTA of the microcontroller.
5. Both Ports D and A are configured as output ports.
Control Signal Definitions
Function Prototypes
Main Function
LCD Initialization
sequence
LCD Initialization
sequence
LCD command
function
LCD data function
Keyboard Interfacing
To detect the key pressed, the
microprocessor drives all rows low
then it reads the columns.
If the data read from the columns
is D7–D4 = 1111, no key has been
pressed and the process continues
until a key press is detected.
However, if one of the column bits
has a zero, this means that a key
was pressed.
For example, if D7–D4= 1101, this
means that a key in the D5 column
has been
pressed
ADC interfacing Programming
Absolute
Register Name Symbol Description
Address
ADC Status and Control Controls ADC operation
0x4003B000 ADC0_SC1A
Register 1A and status (A)
ADC Status and Control Controls ADC operation
0x4003B004 ADC0_SC1B
Register 1B and status (B)
ADC Configuration ADC configuration (clock,
0x4003B008 ADC0_CFG1
Register 1 mode, etc.)
ADC Configuration Additional ADC
0x4003B00C ADC0_CFG2
Register 2 configuration settings
ADC Data Result Register Conversion result (Channel
0x4003B010 ADC0_RA
A A)
ADC Data Result Register Conversion result (Channel
0x4003B014 ADC0_RB
B B)
• Enabling Clock to ADC
Bit D27 of SIM_SCGC6 register is used to enable the clock to ADC0
module.
• Start Conversion trigger options
There are two start-conversion (trigger) options. They are hardware trigger
and software trigger.
The selection of hardware or software trigger for conversion is done via the
bit D6 (ADTRG, ADC Trigger) of ADC0_SC2 (ADC0 Status Control
2) register.
The hardware trigger may be external pin, comparator, or timers
(TPMx, LPTMR0, PIT, or RTC). The selection of hardware trigger is done in
SIM_SOPT7 register.
Bit
Bit Name Description Bit Value = 0 Bit Value = 1
No.
Conversion not in Conversion in
7 ADACT Conversion Active
progress progress
6 ADTRG ADC Conversion Trigger Select Software trigger Hardware trigger
Compare function Compare function
5 ACFE Compare Function Enable
disabled enabled
Compare on less than Compare on
4 ACFGT Compare Function Greater Than Enable
value greater than value
Compare range
3 ACREN Compare Range Enable Compare range disabled
enabled
2 DMAEN DMA Enable DMA disabled DMA enabled
REFSEL Value Voltage Reference Used
VREFH and VREFL pins are used as VREF(+) and
00
VREF(−) respectively
1-0 REFSEL
VALTH and VALTL internal reference pair is
01
used
10 Reserved
11 Reserved
• Choosing Vin input channel
The channel selection is done through the ADC0_SC1A (ADC
Status and Control 1A) register. (There are more ADC0_SC1n
registers but onlyADC0_SC1A can be used for software trigger.
The other registers are for hardware trigger only and will not be
discussed here.)
The lowest 5 bits of ADC0_SC1A register are used to select one
of the 31 single-ended channels to be converted
Bit(s) Field Name Description Bit Value / Meaning
0 → Conversion not completed1 →
Conversion Conversion completedNote: COCO
7 COCO
Complete Flag is cleared when ADCx_SC1n is
written or ADCx_Rn is read
0 → ADC interrupt disabled1 →
6 AIEN Interrupt Enable ADC interrupt enabled (interrupt
occurs when COCO = 1)
Differential Mode 0 → Single-ended mode1 →
5 DIFF
Select Differential mode
Single-ended mode (DIFF =
0):Values 0–23 select ADC_SE0 to
ADC Input ADC_SE23Differential mode (DIFF
4–0 ADCH
Channel Select = 1):Values 0–3 select differential
channels11111 → ADC module
disabled
Name Description Pin
ADC_SE0 ADC input 0 PTE20
ADC_SE3 ADC input 3 PTE22
ADC_SE4 ADC input 4 PTE21, PTE29
ADC_SE5 ADC input 5 PTD1
ADC_SE6 ADC input 6 PTD5
ADC_SE7 ADC input 7 PTD6, PTE23
ADC_SE8 ADC input 8 PTB0
ADC_SE9 ADC input 9 PTB1
ADC_SE11 ADC input 11 PTC2
ADC_SE12 ADC input 12 PTB2
ADC_SE13 ADC input 13 PTB3
ADC_SE14 ADC input 14 PTC0
ADC_SE15 ADC input 15 PTC1
ADC_SE23 ADC input 23 / DAC0 output PTE30
ADC_SE26 Temperature sensor Internal
ADC_SE27 Bandgap reference Internal
ADC_SE29 VREFH VREFH pin
ADC_SE30 VREFL VREFL pin
ADC_SE31 Module disabled —
• ADC Data result
Upon the completion of conversion, the binary result is placed in the
ADC0_RA register.
There are many ADC0_Rn registers corresponding to the ADC0_SC1n
registers.
Because we can only use ADC0_SC1A for software trigger, the data
will be in ADC0_RA register. This is a 32-bit register but only the
lower 16 bits are used.
The conversion complete (COCO) flag bit in ADCx_SC1n register is
cleared automatically when the data from the respective ADCx_Rn
register is read
• Selection Bit Resolution