Memory System

Characteristics of Memory System

Memory Hierarchy

• Questions like:
• How Much? (Capacity related)

• How Fast? (Performance related)

• How Expensive? (Cost related)

• Need of trade off between these three characteristics
Memory Hierarchy

• If capacity is there, then it will be used by applications

anyhow

• For performance, memory must be able to keep up with

processor speed

• Cost of memory must be reasonable to other components

Memory Hierarchy: Implementation
relationship
• Faster Access Time, Grater Cost per bits

• Greater Capacity, Smaller Cost per bits

• Greater Capacity, Slower Access Time

For a designer, large- capacity memory is desirable because the

capacity is needed and because the cost per bit is low. However,
to meet performance requirements, the designer needs to use
expensive, relatively lower-capacity memories with short access
times.
Memory Hierarchy: Efficient
implementation
• Not to rely on single memory component or technology, instead employ memory
hierarchy
Memory Hierarchy: Efficient
implementation
• Smaller, more expensive, faster
memories are supplemented by
larger, cheaper, slower memories.

• The key to the success of this

organization is: decreasing
frequency of access.
 Memory Hierarchy: Efficient
implementation
• The total memory capacity thus can be
visualized as being a hierarchy of components.

• The memory hierarchy system consists of all

storage devices employed in a computer
system from the
• slow but high-capacity auxiliary memory to
• relatively faster main memory, to
• a smaller and faster cache memory accessible to the
high-speed processing logic.
Memory Hierarchy: Types of
Memories
• Main Memory
• The memory unit that communicates directly with the CPU
• Only programs and data currently needed by the processor reside in
main memory.

• Auxiliary Memory
• Devices that provide backup storage
• Most Commonly used: magnetic disks, tapes
• Used for storing system program, large data files, and other backup
Memory Hierarchy: Types of
Memories
• Cache memory
• Special very high-speed memory

• Used to increase the speed of processing by making current

program available to the CPU in a rapid rate

• Implemented in computer system to compensate for the speed

differential between main memory access time and processor
logic
Memory Hierarchy: Types of
Memories
• Virtual memory
• Not true physical memory, instead a part of secondary memory is
utilized to appear as if it is main memory of the system
• The CPU hardware and operating system collaborate in achieving the
swapping while the program is running, for smooth access of
secondary memory
• Swapping may be performed several time in computer systems with
virtual memory implementation
Memory Hierarchy: Types of
Memories
• Virtual memory
• Application programmer is not aware of the actual physical memory
size

• The access of secondary memory for required data is done by rising

special interrupt known as virtual memory interrupt or page fault

• Logical addressing for virtual memory (not physical) and the address
translation is done by memory management unit (MMU)
Memory Types: Main
Memory
3.1
Main Memory
• Central storage unit in a computer system

• Relatively large and fast memory used to store programs and data during
computer operation

• Earlier system included doughnut-shaped ferromagnetic loops referred to as

cores

• In present, use of semiconductor chips for main memory is almost universal

• Stores binary information on in groups of bits called a word. Most computer

system uses words whose number of bits are multiple of 8-bits (or a byte).
Main Memory: Organization
• Basic element of semiconductor
memory is cell which have following
properties
• They exhibit two stable (or semistable)
states, 1 and 0.
• They are capable of being written into (at
least once), to the state.
• They are capable of being read to sense the
state
Main Memory: RAM

• Random Access Memory or more appropriately Read-Write

Memory

• Volatile nature

• Can be used as temporary storage utilized during Run-time

• Two traditional form of RAM used in computers are: DRAM

and SRAM
Main Memory: DRAM
• Dynamic RAM is made with cells that store data as charge on
capacitors

• The presence or absence of charge in capacitor is interpreted as 1

or 0 logic.

• DRAM requires periodic charge refreshing to maintain data storage.

Even when power is still applied, DRAM has tendency to leak way
charge, and thus must maintain continuous refreshing.
 Main Memory: DRAM
• Once DRAM cell stores 1 bit (0 or 1)

• Address line is activated when bit value from this cell is

to be read or written

• Transistor acts as a switch that is closed if a voltage is

applied in address line otherwise open
• Write Operation
• voltage signal is applied to B line (bit line): High voltage =1
and Low voltage = 0.
• Signal is applied to address line which closes the transistor Individual cell of DRAM
and allows charge to be transferred to capacitor.
 Main Memory: DRAM
• Read Operation
• Signal is applied to address line which closes
the transistor (or current flow path)
• Now the charge stored in capacitor is fed to out
onto the bit line and to a sense amplifier.
• The sense amplifier compares logic 1 or 0
• The readout from cell discharges the capacitor,
Individual cell of DRAM
which must be restored to complete read
operation
Main Memory: SRAM

• Digital device that uses same logic elements used in

processor.

• Binary value are stored using traditional flip-flip logic-

gate configuration

• A SRAM will hold data as long as power is supplied to it.

 Main Memory: SRAM
• In logic state 1
• point C1 is high, and point C2 is low
• T1 and T4 are off and T2 and T3 are on

• In logic state 0
• point C2 is high and point C1 is low
• T2 and T3 are off and T1 and T4 are on

• As long as dc voltage is applied to cell,

both logic states are stable

• Unlike DRAM it doesn't need refresh to

retain data
Main Memory: SRAM vs DRAM
• Both are volatile
• A DRAM cell is simpler and smaller than SRAM cell which is
why DRAM are more dense and less expensive for same
capacity of storage.
• DRAM requires supporting refreshing circuits however SRAMs
are faster and bulky for same storage capacity.
• DRAM tends to be favored for larger memory requirements.
Main Memory: ROM
• Read Only Memory

• Contains permanent pattern of the data that cannot be changed

• Non-volatile i.e. power source is not required to maintain the bit

values in memory

• Advantage of ROM is that the data or program is permanently in

main memory and need never be loaded from a secondary storage
device
Main Memory: ROM
• Important application of ROM includes:
• Micro-programing
• Library subroutine for frequently wanted functions
• System programs
• Function tables

• In early ROM types, data were wired in chip while fabricating

ROM with help of Mask, however this created problems and
raised concept of programmable ROM (PROM)
Main Memory: ROM
• PROM can be written only once, through electrical process. Data
need not be inserted during fabrication.
• There are other ROMs which are mostly for Read-Only, however,
can provide flexibility of writing over old data.
• For applications which requires very less changes Read-Mostly
Memory can be utilized which are Erasable ROM memories.
• Read Mostly memories are EPROM (erasable programmable ROM),
EEPROM (electrically erasable programmable ROM)
Main Memory: ROM
• EPROM is erased with UV exposure, and all previous data are
erased, and rewritten

• EEPROM instead provides flexibility to erase bytes or words at

a time, and particular content can be modified

• Flash Memory is intermediate between EPROM and EEPROM

in both cost and functionality. Instead of bytes/words, a block
or section can be erased electrically in a flash.
Main Memory: Semiconductor
memory type
Cache Memory Principles

• Cache arrangement

Single cache arrangement

Three level cache arrangement
Cache Memory Principles

• Cache Memory
• Is an intermediate buffer between CPU and main memory

• Main objective is to reduce CPU waiting time during main

memory access

• Very small capacity

• Based on Locality of Reference phenomenon
Cache Memory Principles

• Locality of Reference phenomenon

• Reference to memory at any given interval of time tend to be
confined within a few localized area in memory

• It implies that future references will likely to come from this

block of memory

• Two sub-segment of this behaviors: Temporal Locality and

Spatial Locality
Cache Memory Principles
• Temporal Locality
• The current instruction which is being fetched may be needed again soon

• Spatial Locality
• The adjacent instruction to current instruction may be needed soon

• On basis of these two properties, while accessing the main memory

for an instruction, instead of fetching just one instruction from
main memory, several consecutive instructions are fetched together
and stored in cache memory.
Elements of Cache
Design
 Cache/Main memory Structure
Main memory consists of up to 2n
addressable words, with each word
having a unique n-bit address.

This main memory is considered to

consists of a number o fixed-length
block of K words each.

That is, there are M = 2n/K blocks

in main memory.
 Cache Size
The cache consists of m blocks,
called lines.

Line Size: Length of line not

including tag and control bits

Each line contains K words, plus a

tag of a few bits, and control bits to Tag: An identifier which identifies which
indicate whether a line has been particular block is currently being stored. It is
modified since being loaded into the usually portion of main memory address
cache.

Number of lines: m<<M, m = no. of

lines/blocks in cache,
M = no. of blocks in main memory
Cache Read Operation
 Cache Performance Metrices

Hit and Miss:

Cache Hit: If current memory address is already mapped onto cache, then the
situation is called Cache Hit.

Cache Miss: If the current memory address is not already mapped onto cache,
then it is called Cache Miss.

Miss Penalty: Every miss leads to accessing the main memory, and thus
increases time taken to access the item and supply it to processor. This is terms
as miss penalty.

Hit Ratio: Ratio of number of cache hits to the number of total accesses made.
Mapping Function/Process

• The Transformation of data from main memory to cache

memory is referred to as mapping process

• Three types of mapping procedures are of practical

interest:
• Direct Mapping
• Associative Mapping
• Set-associative Mapping
Direct Mapping

• Simplest technique, known as

direct mapping, maps each block

of main memory into only one possible cache line. The

mapping is expressed as:
Where,
i = cache line number
i = j modulo m j = main memory block number
m = number of lines in cache
Direct Mapping
- Address length = s+w bits

- No. of addressable units = 2s+w words

- Block size = line size = 2w words

- No. of blocks in main memory = 2s+w / 2w

= 2s

- No. of lines in cache = m = 2r

- Size of cache = 2r+w words = 2r * 2w words

= No. of lines * line size (block size)

- Size of tag = s-r bits

 Direct Mapping
• Main Advantage
• Simple and inexpensive implementation

• Main Disadvantage
• Thrashing: If a program happens to
reference words repeatedly from two different
blocks that maps into same line, then the
blocks will be continually swapped in the
cache, and the hit ratio will be low.
Associative Mapping
• Overcomes thrashing
• Any block can be mapped onto any line in cache
• The cache control logic interprets a memory address simply as
a Tag and a Word field.
• The Tag field uniquely identifies a block of main memory.
• The cache control logic must simultaneously examine every
line’s tag for a match.
Associative Mapping - Address length = s+w bits

- No. of addressable units = 2s+w

words

- Block Size = line size = 2w

words

- No. of blocks in main memory =

2s+w/2w = 2s

- No. of lines in cache =

undetermined

- Size of tag = s bits

Associative Mapping

• With associative mapping, there is flexibility as to which

block to replace when a new block is read into the cache.
Replacement algorithms are used to maximize hit ratio.

• Main Disadvantage
• Complex Circuitry : A complex set of circuitries is required to
examine the tags of all cache lines in parallel.
Set-Associative Mapping

• Compromise that exhibit the strength of both direct and

associative mapping

• In this procedures, cache consists of number of sets which

consists of a fix number of lines
•m=vxk
Where,
m = No. of lines in cache
v = No. of sets in cache
k = number of lines in each set of cache
Set-Associative Mapping

• Mapping can be expressed as:

• i = j modulo v j = Main memory block number
i = cache set number

• Also referred to as k-way set associative mapping

• This K-way set associative mapping can be viewed as

either v-associative map, or k-direct map cache.
 Set-Associative Mapping
Each sets of v contains k lines, where each Each direct- mapped cache is referred to as a
sets are associatively mapped. way, consisting of v lines.

Viewed as k-direct mapped cache

Viewed as v-associative mapped cache
Set-Associative Mapping

• For set- associative mapping, the cache control logic

interprets a memory address as three fields: Tag, Set, and
Word.

• The direct-mapped implementation is typically used for

small degrees of associativity (small values of k) while the
associative-mapped implementation is typically used for
higher degrees of associativity.
Set-Associative Mapping
- Block size = line size = 2w words

- No. of blocks in main memory = 2s+w/2w

= 2s

- Number of lines in set = k

- No. of lines in cache = m = kv = k x 2d

- Size of cache = k x 2d+w words

- Size of tag = s-d bits

Replacement Algorithms

• LRU (Lease Recently Used)

• FIFO (First In First Out)

• LFU (Least Frequently Used)

• Random
LRU

• Based on usage of data in cache line

• Replace the block in set that has been in the cache longest
with no reference to it

• For 2-way set associative, a use bit can be used. If one line
in a set is accessed, its use bit is set 1, while other is set 0

• At last, the one with use bit 0 is replaced

LRU

• In fully associative, cache mechanism maintains separate

indexes to all lines

• When a line is referenced, it moves to the front list, and

the one in the back of the list is replaced when needed

• Most popular algorithm

 FIFO

• Replace the block in set that has been in cache longest

• Easily implemented as round-robin or circular

buffer/queue technique
LFU

• Replacement of block which have very fewest hit or

references

• It can be implemented by associating counter with each

line

• The counter with lowest value is replaced

Random

• Replacement of random block in the set

• This algorithm do not analyze the usage of lines (hit or

miss values)
Write Policy

• When a block that is resident in the cache is to be replaced,

there are two cases to consider:
• If the old block in the cache has not been altered, then it may be over-
written with a new block without first writing out the old block.

• If at least one write operation has been performed on a word in that line
of the cache, then main memory must be updated by writing the line of
cache out to the block of memory before bringing in the new block.
Write Policy

• There are two problems to be dealt with in cache

implementation
• In case memory is directly being accessed by other devices than
processor

• Multiprocessors having multiple local cache

Write Policy: Techniques to deal the
problems
• Write Through
• Simplest and most commonly used procedure

• Each time cache and main memory block is updated

• Facilitates in DMA access by I/O

• But increases memory traffic and may create bottleneck
Write Policy: Techniques to deal the
problems
• Write Back
• Minimize memory write operation by only updating cache word
• Dirty bit or use bit is used to indicate if write operation has been
performed in a particular line of cache
• At the time of replacement the word is written back to memory only if
dirty bit is set
• But access of DMA should be made through cache which increases
circuit complexities
The CPU-Memory Interface
Memory Chip Logic

• Each chip contains an array of memory cells.

• One way of organization of array is into W words of B-bits each
(as perceived by the processor, logically)

• Another way is called 1-bit-per-chip organization, in which data

are read/written 1-bit at a time.
Memory Chip Logic

• For a typical 16-Mbit DRAM

• 4-bits are R/W at the same time in this chip (4M of 4-bit
Words!)

• Logically its memory array organization is 4 square arrays of

2048x2048 elements.

• Various physical arrangement are possible!

Each horizontal line connects to select terminal of
each cell in the row,

Each vertical line connects to the Data-In/Data sense

terminal of each cell in column

Address line supply of the word to be selected

total of
log2W lines are needed!
= 22 for the example

11 lines are fed into row decoder to select suitable

row for operation.
Total 2048 elements are selected in a row!

11 lines are fed into column detector to select

one of the 2048 element of the row.

Row and Column line values are accompanied by RAS’ and CAS’ signals to
distinguish for which the 11 address line serves as input address!
Logic external to the chip multiplexes the 22
lines into 11 lines to save the chip pins!

First 11 address passed to row with RAS’

Later 11 address passed to column with CAS’

One more addition to pin, quadruples the memory

size, that is increase the memory chip by factor of
4.

For larger word operation, need to add more

chip .

If chip logic included 1-bit per chip organization,

the numbers of chip required for W word
access is W chips!
A Memory Module
• A memory module presents a specific memory interface to the processor
or other unit that references memory.

• It usually contains buffer registers for the address and data, so that the
processor need not hold these values constant for the duration of the
memory cycle, or strobe the output data at a precise time in the case of a
read.

• A module operates independently by accepting address, read or write

commands, and perhaps data, storing the data on write or returning new
data on read.
A Memory Module
• The interface to a memory module is a bus that has signal wires
corresponding to:
• Read and Write-start signals for memory cycles
• Ready-memory is ready for next write or data is available from last read
• Address-must be sent to memory at time of Read or Write signal
• Data-sent with Write or available from memory when Ready becomes true
after Read
• Module select-needed when several modules share a bus
A Memory Module
Module Organization
If a RAM chip contains only one bit per
word, then clearly we will need at least a
number of chips equal to the number of
bits per word.

→ For 256K words, an 18-bit address is

needed
→ address is presented to 8 256K * 1@bit
chips

This organization works as long as the

size of memory equals the number of
bits per chip.

memory module consisting of 256K 8-bit words

Multiple Memory Module Organization

In the case in which larger memory is

required, an array of chips is needed.

→ four columns of chips, each column

containing 256K words arranged
→ For 1M word, 20 address lines are
needed.
→ The 18 least significant bits are routed to
all 32 modules.
→ The high-order 2 bits are input to a group
select logic module that sends a chip
enable signal to one of the four columns
of modules.

organization of a memory consisting of 1M

words by 8 bits per word.
Synchronous DRAM (SDRAM)

• Operation synchronized to an external clock signal

• Running at full speed of the processor/memory bus without
imposing wait states

• In typical DRAM, the processor presents address and control

levels to memory and wait for the data to be read/written (wait
states) (access time delay)

• During the Delay, DRAM needs to do various internal operations

Synchronous DRAM (SDRAM)
• In SDRAM, data in/out is done under control of the system
clock
• Processor instruct for an operation and provides address information
• SDRAM consumes specific time periods/clock cycle to ready the data
• Processor performs other internal operation while the SDRAM ready
the data
• SDRAM can then transfer the data in burst of several words (mode
register defines the burst)
256-Mb SDRAM
DDR Technology

• Double Data Rate DRAM (DDR DRAM)

• SDRAM with double data rate
• SDRAM still can limit I/O data rate that can be achieved

• Two words latched at same clock, rising and falling

• Double word in same clock, double data rate

• DDR uses higher clock on the bus to increase transfer rate

• Buffering is used (prefetched data)

DDR Technology

• Double Data Rate DRAM (DDR DRAM)

• First version of DDR- 2bit prefetch buffer
• Prefetch buffer = memory cache located on the SDRAM chip

• DDR I/O bus using same clock as memory chip, can handle two bit per
cycle
DDR Technology

• Double Data Rate DRAM (DDR DRAM)

• DDR3 and DDR4 have same prefetch buffer size, yet DDR4
doubles the data rate of DDR3
• Uses Bank Group Concept

• Bank group, separate entities such that they allow a column cycle to
complete within a bank group, but that column cycle does not impact
what is happening in another bank group.
DDR Generations
DDR Technology

• DIMM
• Dual In-line Memory Module

• Used for desktop, and servers to insert main memory

• Instead of soldering memories on board, memory modules

allows replacement
• Also defines standard form-factor of modules so there is
interchangeability
DDR Technology

• SODIMM
• Small Outline Dual In-line Memory Module

• Used for compact system like laptop

• Half the form factor of DIMM

• Pin numbers depends on DDR modules inside the DIMM/SODIMM (

• DIMM/SODIMM follows JEDEC standard for pin, signals, and form

factors
 DDR Technology
• KSM32ES8/16MF Memory Module • KVR32S22S8/16 Memory Module
• Kingston Server DIMM module (KSM: • KVR: Kingstone Value RAM
Kingstone Server Memory) • 32 = DDR4-3200, S = SO-DIMM, 22 =
• 32 = DDR4-3200, E = ECC, S8 = x8 CL22 Latency, S8 = x8 Organization
Organization Chips, /16 = 16 GB Module, chips, /16 = 16 GB Module
M = DIMM • No ECC
• 16 internal banks, 4 bank groups • 16 internal banks, 4 bank groups
• 72 bit (64 + 8) • 64 bit
• On board serial presence-detect (SPD) • On board serial presence-detect (SPD)
EEPROM EEPROM
DDR Technology

KSM32ES8/16MF
KVR32S22S8/16
133.35 mm length
31.25 mm height 69.60 mm length
9-chip, (1 chip for ECC) 30.000 mm height
8-chip, (no ECC)
External Memories
Internal and External Memory
• External Memories
• Magnetic Surface Recording technology
• Magnetic Disk
• Magnetic Tape

• Optical Memory
• SSD
• RAID
Internal and External Memory

• Magnetic Surface Recording Technology

magnetic states are
defined by the
direction or magnitude
of the cell's magnetic
flux in the cell.

magnetic medium such as ferric oxide.

 Internal and External Memory

• Magnetic Disk Memories

Disk = circular platter
constructed of nonmagnetic
material/substrate coated with
magnetisable material
Data are recorded on/retrieved
via a conducting coil called
head.

In many there can be two

a) Top view of magnetic disk drive unit b) side view of magnetic disk drive heads: a Read Head, and a
unit Write Head
 Internal and External Memory

• Magnetic Disk Memories

During operation of the
memory, the disks are rotated
at a constant speed by a disk
drive unit.
Each recording surface is
supplied with at least one read-
write head.
Heads are stationary.
MR = Magnetoresistive
Internal and External Memory

• Magnetic Disk Memories

Organization of data on the platter in a concentric sets of rings/tracks.

Each track has same width as head, and a platter can have thousands of
tracks. Adjacent tracks are separated by intertrack gaps.

Data transferred to/from disk in sectors. And there are hundreds of

sectors per tracks. (fixed or variable length). Adjacent sectors are
separated by inter-sector gaps.
Performance depends on :
seek time and rotational
latency
Internal and External Memory

• RAID
• Array of disks that operates independently in parallel

• Separate I/O request can be handled in parallel (if data are stored in
separate disks) or a single I/O request can be executed in parallel if
the block of data t be accessed is distributed across multiple disks.

• There are various way in which data can be organized and

redundancy can be added for improved reliability.
• Different RAID Levels
Internal and External Memory

• RAID
• RAID levels are simply different design architecture that share
common characteristics which are:
• RAID is a set of physical disk drives viewed by the OS as a single logical drive

• Data are distributed across the physical drives of an array in a scheme

known as stripping

• Redundant disk capacity is used to store parity information, which

guarantees data recoverability in case of a disk failure.
Internal and External Memory
• RADI 0
• Does not include redundancy
• The user and system data are distributed across all of the disks in the
array called stripping
• In n-disk array, the first n logical strips are physically stored as the
first strip on each of n-disks, forming first stripe,
• Second n logical strips are distributed as the second strips on each
disks, and so on.
Internal and External Memory

If single I/O request

consists of multiple
logically contiguous strips,
the up to n stripes of that
request can be handled in
parallel
Internal and External Memory

• RADI 1
• Redundancy is achieved by simply mirroring the disks

• No parity/ECC utilized

• Each logical strip is mapped to two separate physical disks.

Internal and External Memory

• RADI 1
• Characteristics:
• A read request can be serviced by either of the two disks that contains
the requested data, whichever involves the minimum seek time plus
rotational latency

• A write request requires that both corresponding strips must be updated,

but this can only be done in parallel. Thus, write performance is dictated
by the slower of the two writes
Internal and External Memory

• RADI 1
• Characteristics:
• Recovery from failure: data may still be accessed from the second drive.

• Principle disadvantages: cost

• If high I/O request are read, RAID 1 can achieve significant
performance, but if it is mostly write, there might be no
significant gain.
Internal and External Memory
• RADI 2
• RAID 2 make use of parallel access technique.
• All member disks participate in the execution of every I/O request
• Spindles of individual drives are synchronized so that each disk head is in
same position on each disk at any given time.

• Data striping in very small size: byte/word

• Error correcting code is calculated across corresponding bits on each
data disks, and bits of code are stored in corresponding bit position
on multiple parity disks. (Hamming code)
Internal and External Memory

• RADI 2
• Requires less disk than RAID1 but still costly
• Requires LogN times redundant disk
Internal and External Memory
• RADI 2
• Can handle one I/O request at a time
• In every read, all disks are simultaneously accessed and associated
error correcting code are delivered to controller
• In case of bit error controller can recognize and correct it instantly

• On single write, all data and parity disks must be accessed for write
operation
• An effective choice for environment in which may disk errors ocurr.
Internal and External Memory
• RADI 3
• Organized in similar way of RAID 2 and make use of parallel access
technique.
• But it requires only one redundant disk, no matter how large the disk
array
• Simple parity bit is computed for the set of individual bits in the same
position on the data disk
• In the event of failure the party drive is accessed and data is reconstructed
from the remaining devices
Internal and External Memory

• RADI 3
• Strips of very small data size (byte/word)) thus can achieve very
high data transfer rate

• Only one I/O request can be executed at a time

Internal and External Memory

• RADI 4
• Makes use of independent access technique
• Each member disk operates independently so that separate I/O request can
be satisfied in parallel

• This level is more suitable for applications that require high I/O
request rates and relatively less suited for applications that require
high data transfer rates

• Data strips are relatively large

Internal and External Memory

• RADI 4
• Bit-by-bit party strip is calculated across corresponding strips
on each data disk, and the parity bits are stored in the
corresponding strip on the parity disk
Internal and External Memory

• RADI 4
• Involves write penalty when an I/O request of small size is
performed
• Each time that write occurs the array management software must update
not only the user data but also the corresponding parity bits
Internal and External Memory

• RADI 5
• Organized in same way as RAID 4

• Difference is: distributed parity strips across all disks

• Typica allocation is a round-robin scheme
Level Advantages Disadvantages Applications
0 I/O performance is greatly improved by The failure of just one Video production and editing
spreading the I/O load across many drive will result in all Image editing
channels and drives data in array being lost. Pre-press applications
No parity calculation overhead involved Any applications requiring high
Very simple design bandwidth
Easy to implement
1 100% redundancy of data means no Highest disk overhead Accounting
rebuild is necessary in case of disk failure of all RAID types Payroll
Under certain circumstances RAID1 can (100% overhead) Financial
sustain multiple simultaneous drive failure Any application requiring very
Simple RAID storage subsystem design high availability
2 Extremely high data transfer rate possible Very high ratio of ECC No commercial implementation
The higher the data transfer rate required, disks to data disks for exist/not commercially viable
the better the ratio of data disks to ECC smaller word size
disks Entry level cost very
Relatively simple controller design in high (requires very high
comparison to level 3,2,4 transfer rate
requirement to justify)
Level Advantages Disadvantages Applications
3 Very high read data transfer rate Transaction rate equal to Video production and live streaming
Very high write data transfer rate that of single disk drive Image editing
Disk failure has an insignificant impact at best (if spindles are Video editing
on throughput synchronized) Prepress applications
Low ratio ECC (parity) disks to data Controller design is Any application requiring high
disk means high efficiency fairly complex throughput
4 Very high read data transaction rate Quite complex controller Noncommercial implementation
Low ratio of ECC (parity) disks to data design Commercially not viable
disks means high efficiency Worst write transaction
rate and Write aggregate
transfer rate
Difficult and inefficient
data rebuild in the event
of disk failure
5 Highest Read data transaction rate Most complex controller File and application servers
Low ratio of ECC (parity) disks to data design Data base servers
disks means high efficiency Difficult to rebuild in the Web, e-mail, and news servers
Good aggregate transfer rate event of a disk failure Intranet servers
(as compared to RAID1) Most versatile RAID level
Internal and External Memory
Magnetic tape memories
• Magnetic Tape Memories resemble domestic tape
recorders, which stores binary
information.
Tapes are flexible polyester
coated with magnetizable
material.
Tapes are hosed in cartridges.

Data on tape are structured as a

number of parallel tracks
running lengthwise.
Internal and External Memory
Earlier tape systems typically
• Magnetic Tape Memories used 9 tracks.
This made possible to store
data one byte at a time, and
with additional parity bit as the
ninth track.
Same structure followed by 18
or 36 tracks, corresponding to
a digital word or double word.

This form of recording is

Parallel recording.
Internal and External Memory
Most modern tape uses serial
• Magnetic Tape Memories recording.
Data are laid out as a sequence
of bit along each track, as done
in magnetic disks.
Data are read and written in
contiguous blocks, called
physical record and blocks on
the tape are separated by inter-
record gaps.
Internal and External Memory

• SSD (Solid State Drives)

• Solid State = electronic circuit built within semiconductor

• SSD made with solid state components that can be used as a

replacement to hard disk drive (HDD)

• SSD now on the market use NAND flash memory

Internal and External Memory

• SSD (Solid State Drives) Advantage over HDDs

• High performance I/O operations per seconds (IOPS)
• Significantly increases performance I/O subsystems

• Durability
• Less susceptible to physical shock and vibration

• Longer Lifespan
• SSDs are not susceptible to mechanical wear
Internal and External Memory

• SSD (Solid State Drives) Advantage over HDDs

• Lower power consumption
• SSDs use considerably less power than comparable-size HDDs

• Quieter and Cooler running capabilities

• Less space required, lower energy costs, and greener enterprise

• Lower access times and latency rate

• Over 10 times faster than spinning disks in an HDD
Components of SSD:

•Controller: Provides SSD device level interfacing

and firmware execution.

•Addressing: Logic that performs the selection

function across the flash memory components.

•Data buffer/cache: High speed RAM memory

components used for speed matching and to increased
data throughput.

•Error correction: Logic for error detection and

correction.

•Flash memory components: Individual NAND flash

chips.
Solid State Drive Architecture
Internal and External Memory

• SSD (Solid State Drives) Issues over HDDs

• Fist Issue: SSD performance has tendency to slow down as
device is used
• Files are stored on disk as a set of pages (typically 4KB in length)

• These pages are not necessarily stored as contiguous set of pages on the
disks

• Flash memory is accessed in blocks, with typical block size of 512KKB, so

that typical 128 pages per block
Internal and External Memory

• SSD (Solid State Drives) Issues over HDDs

• So to write a page onto a flash memory:
• The entire block must be read from the flash memory and placed in a
RAM buffer. Then the appropriate page in RAM buffer is updated

• Before the block can be written back to flash memory, the entire block of
flash memory must be erased-it is not possible to erase just one page of
the flash memory

• The entire block from the buffer is now written back to the flash memory
Internal and External Memory

• SSD (Solid State Drives) Issues over HDDs

• At the beginning when flash is relatively empty and a new file is
created, the pages of that file are written on the drive
contiguously, so that one or only few blocks are affected.

• However, overtime, because of the way virtual memory works,

files become fragmented, with pages scattered over multiple
blocks.
Internal and External Memory

• SSD (Solid State Drives) Issues over HDDs

• Second issue: flash memory becomes unusable after certain
number of writes
• Typical limit is 100,000 writes.
Internal and External Memory
Resembles magnetic disks in
• Optical Memory that they store binary
information in concentric
tracks

Information read or written

optically with help of laser