1

EX. NO.: 1
VERIFICATION OF LOGIC GATES
DATE:

AIM:

To construct the logic circuit using IC’s and to verify their truth tables.

MATERIALS REQUIRED:

Trainer kit, IC 7408 (AND), IC 7432 (OR), IC 7404 (NOT), IC 7400 (NAND),
IC 7402 (NOR), IC (7486) EX-OR, voltmeter, connecting wires, etc.

FORMULA:

AND Gate: Y = A.B

OR Gate: Y = A+B

NOT Gate: Y = A

NAND Gate: Y = A.B

NOR Gate: Y = A.B

EX-OR Gate: Y = A ⨁ B

Where,

A, B = Inputs, Y= Output

PROCEDURE:

 Place the IC on trainer kit connects Vcc and ground to respective pins of IC trainer kit.
 Connect the inputs to the input switched provided in the trainer kit.
 Connect the outputs to the switches provided in the o/p LEDs.
 Apply various combinations of inputs according the truth table and observe condition
of LEDs.
 Disconnect output from the LEDs and note down the corresponding multimeter
voltages for various combination of inputs
 2

AND GATE:- OR GATE:-

SYMBOL: SYMBOL:

PIN DIAGRAM: PIN DIAGRAM:

TRUTH TABLE: TRUTH TABLE:

INPUT OUTPUT (Y = A.B) INPUT OUTPUT (Y = A+B)

A B LOGIC VOLTAGE A B LOGIC VOLTAGE

0 0 0 0 0 0

0 1 0 0 1 1

1 0 0 1 0 1

1 1 1 1 1 1
 3

NOT GATE:- NAND GATE:-

SYMBOL: SYMBOL:

PIN DIAGRAM: PIN DIAGRAM:

TRUTH TABLE: TRUTH TABLE:

INPUT OUTPUT (Y = 𝑨.𝑩)

INPUT OUTPUT (Y = 𝑨)
A B LOGIC VOLTAGE
A LOGIC VOLTAGE 0 0 0

0 1 1
0 1
1 0 1
1 0
1 1 1
 4

NOR GATE:- EX - OR GATE:-

SYMBOL: SYMBOL:

PIN DIAGRAM: PIN DIAGRAM:

TRUTH TABLE: TRUTH TABLE:

INPUT OUTPUT (Y = A+ B ) INPUT OUTPUT (Y = A ⨁ B)

A B LOGIC VOLTAGE A B LOGIC VOLTAGE

0 0 1 0 0 0

0 1 0 0 1 1

1 0 0 1 0 1

1 1 0 1 1 0

RESULT:

The logic gates are constructed using IC’s and their truth tables are verified.

*******
 5

EX. NO.: 2
CONSTRUCTION OF HALF ADDER AND FULL ADDER
DATE:

AIM:

To construct the half adder and full adder logic circuits by using Ex-OR and basic
gates and to verify their truth tables.

MATERIALS REQUIRED:

Trainer kit,
IC 7486 (EX-OR),
IC 7408 (AND),
IC 7432 (OR),
Connecting wires.

PROCEDURE:

 Verify the gates.

 Make the connections as per the circuit diagram.
 Switch on Vcc and apply various combination of input according to the truth
table.
 Note down the output readings for half/full adder, sum /carry bit for different
combination of inputs.
 6
HALF ADDER:-

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

A B SUM CARRY
(A⨁ B) (A.B)
0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
 7
FULL ADDER:-

CIRCUIT DIAGRAM:
 8
TRUTH TABLE:

INPUT OUTPUT

S (SUM) Cout (CARRY)

A B Cin
(A⨁ B ⨁ C ¿ (A⨁ B ¿ C+ AB

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

RESULT:

The HALF adder and FULL adder logic circuits are constructed by using EX-OR and
basic gates and verified their truth tables.

*******
 9

EX. NO.: 3
K- MAP
DATE:

AIM:

To simplify the given Boolean expression by using k-map and to construct the circuit
for given Boolean expression and simplified Boolean expression and to verify outputs.

MATERIALS REQUIRED:

Trainer kit,

IC 7404 (NOT),

IC 7408 (AND),

IC 7432 (OR),

Connecting wires.

PROCEDURE:

 Simplify the given Boolean expression by k-map.

 Circuit diagram has been drawn for simplified Boolean expression & given
Boolean expressions.
 Connections are given through trainer kit for the simplified & given Boolean
expressions.
 10

BOOLEAN EXPRESSION:-

Y=AC+ A B + BC + AC
 11

SIMPLIFIED LOGIC CIRUIT:

K – MAP:-

SUM OF PRODUCT:

Y=AC+ A B + BC + AC

BC BC BC BC

A
1

A 1 1 1
1

Simplified Expression :

Y=A C+ A B + BC + AC

Y = A+ BC

Y = A+ BC
 12

TRUTH TABLE:

INPUT OUTPUT

GIVEN BOOLEAN SIMPLIFIED BOOLEAN

A B C EXPRESSION EXPRESSION
Y=AC+ A B + BC + AC Y = A+ BC

0 0 0 0 0

0 0 1 1 1

0 1 0 0 0

0 1 1 0 0

1 0 0 1 1

1 0 1 1 1

1 1 0 1 1

1 1 1 1 1

RESULT:

The given Boolean expression is simplified by using k-map and the circuit are
constructed and outputs are verified.

*******
 13

EX. NO.: 4
SHIFT REGISTER
DATE:

AIM:

To construct the shift register by using IC 7495 and verify the following modes

1) Serial In Parallel Out

2) Serial In Serial Out
3) Parallel In Serial Out
4) Parallel In Parallel Out

MATERIALS REQUIRED:

Trainer kit,

IC 7495,

Connecting wires.

PROCEDURE:

SERIAL IN PARALLEL OUT:

 Connections are made as per circuit diagram.

 Apply the data at serial I/P.
 Apply one clock pulse at clock observe this data at QA.
 Apply the next data at serial I/P.
 Apply one clock pulse at clock 2, observe that the data on QA will shift to QB
and the new data applied will appear at QA.
 Repeat steps 2 and 3 till all the 4 bits data reentered one by one in to the shift
register.
14
15
 16
SERIAL IN SERIAL OUT:

 Connections are made as per circuit diagram. Load the shift register with 5
bits data one by one serially.
 At the end of 4th clock pulse the first data ‘do’ appears at QD.
 Apply another clock pulse the second data d appears at QD.
 Apply another clock pulse the third data d2 appears at QD.
 Application of next clock pulse will enable the 4th data d3 to appear at QD,
thus the data applied serially input come out serially.

PARALLEL IN SERIAL OUT:

 Connections are made per circuit diagram.

 Apply the desired 4 bit data at A, B,C and D.
 Keeping the mode control m=1 apply one clock pulse the data applied at a, b,
c, and d will appear at QA, QB, QC, and QD respectively.
 Now mode control m=0 apply clock pulse one by one and observe the data
coming out at QD.

PARALLEL IN PARALLEL OUT:

 Connections are made as per circuit diagram.

 Apply the 4 bit data at A, B, C, and D. .
 Apply on clock pulse at clock 2.
 The 4 bit data at A, B, C and d appears at QA, QB, QC, and QD respectively.

PISO:-
 17

RESULT:

The shift register are constructed by using IC 7495 and verified the following modes

1) Serial In Parallel Out.

2) Serial In Serial Out.
3) Parallel In Serial Out.
4) Parallel In Parallel Out.

*******
 18

EX. NO.: 5
UP – DOWN COUNTER
DATE:

AIM:

To construct up-down counter by using IC 7490, IC 7404 and to verify its truth tables.

MATERIALS REQUIRED:

Trainer kit,

IC 7490,

IC 7404,

Connecting wires.

PROCEDURE:

 Connections are made as per circuit diagram. Load the shift register with 5
bits data one by one serially.
 Clock pulses are applied one by one at the clock inputs and outputs is
observed at QA, QB, QC and QD for IC 7490.
 Truth table is verified, now connect the output of the NOT gate to the load
input. Clock pulses are applied to “count” pins, the truth table is verified.
 19
UP COUNTER:-

CIRCUIT DIAGRAM:

TRUTH TABLE:

UP INPUT OUTPUT

COUNT CLK QC QB QA

0 1 0 0 0

1 1 0 0 1

2 1 0 1 0

3 1 0 1 1

4 1 1 0 0

5 1 1 0 1

6 1 0 1 0

7 1 1 1 1
 20
DOWN COUNTER:-

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
DOWN
COUNT
CLK QC QB QA

7 1 1 1 1

6 1 1 1 0

5 1 1 0 1

4 1 1 0 0

3 1 0 1 1

2 1 0 1 0

1 1 0 0 1

0 1 0 0 0

RESULT:

The Up-Down counter was constructed by using IC 7490, IC 7404 and verified its truth
tables.

*******
 21
FLOW CHART:

START

Load H-L pair with address of first operand’s memory location

Move the first operand from memory to accumulator

Increment H-L pair to point to next memory location

Move the second operand from memory to register B

Add register B with register A

NO If
Carry =
?

YES

Increment register C

Increment H-L pair

Move the result from accumulator to memory

Increment H-L pair

Move the carry from register C to memory

STOP
 22

EX. NO.: 6
EIGHT BIT ADDITION AND SUBTRACTION
DATE:

AIM:

To write and execute an assembly language program for addition and subtraction of two
eight bit numbers.

(i) ADDITION:-

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

Load H-L pair with address
8000 LXI H,8100h 21,00,81
8100.
Move the 1st operand from
8003 MOV A, M 7E
memory to reg. A.

8004 INX H 23 Increment H-L pair.

Move the 2nd operand from

8005 MOV B, M 46
memory to reg. B.

8006 MVI C, 00h 0E, 00 Initialize reg. C with 00.

8008 ADD B 80 Add reg. B with reg. A.

800D Jump to address 800D if

8009 JNC D2, 0D, 80
(AHEAD) there is no carry.

800C INR C 0C Increment reg. C.

800D
800D (AHEA INX H 23 Increment H-L pair.
D)
Move the result from reg. A
800E MOV M, A 77
to memory.

800F INX H 23 Increment H-L pair.

Move the carry from reg. C

8010 MOV M, C 71
to memory.

8011 HLT 76 Halt.

PROGRAM:
 23
TABULATION:

INPUT:

ADDRESS DATA

8100

8101

OUTPUT:

ADDRESS DATA

8102
(SUM)

8103
(CARRY)
 24
HAND CALCULATION:
 25
FLOW CHART:

START

Load H-L pair with address of first operand’s memory location

Move the first operand from memory to accumulator

Increment H-L pair to point to next memory location

Move the second operand from memory to register B

Subtract register B from register A

Increment H-L pair

Move the result from accumulator to memory

STOP

(ii) SUBTRACTION:
 26
PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

Load H-L pair with

8000 LXI H,8100h 21,00,81
address 8100.

Move the 1st operand

8003 MOV A, M 7E
from memory to reg. A.

8004 INX H 23 Increment H-L pair.

Move the 2nd operand

8005 MOV B, M 46
from memory to reg. B.

Subtract reg. B from

8006 SUB B 90
reg. A.

8007 INX H 23 Increment H-L pair.

Move the result from

8008 MOV M, A 77
reg. A to memory.

8009 HLT 76 Halt.

TABULATION:-
 27

INPUT:

ADDRESS DATA

8100

8101

OUTPUT:

ADDRESS DATA

8102

HAND CALCULATION:
 28

RESULT:

Thus an assembly language program for addition and subtraction of two 8-bit
numbers are written and executed.

*******

FLOW CHART:
START

Initialize reg. B = 00
 29

Initialize reg. A = 00

Load H-L pair with address of first operand’s memory location

Move the first operand from memory to register C

Increment H-L pair to point to next memory location

Add memory with register A

NO
If Carry =?

Increment register B

Decrement register C

NO
If Zero = ?
YES

Increment H-L pair

Move the result from accumulator to memory

Increment H-L pair

Move the carry from register C to memory

EX. NO.: 7
STOP
SUM OF SERIES
DATE:
 30
AIM:

To write and execute an assembly language program of sum of series.

OP-
ADDRESS LABEL MNEMONICS OPERAND COMMENTS
CODE
8000 MVI B, 00h 06, 00 Initialize reg. B with 00.

8002 MVI A, 00h 3E, 00 Initialize reg. A with 00.

Load H-L pair with

8004 LXI H, 8100h 21, 00, 81
address 8100.
Move the counter from
8007 MOV C, M 4E
memory to reg. C.
8008
8008 INX H 23 Increment H-L pair.
(LOOP2)

8009 ADD M 86 Add reg. A with memory.

800E Jump to address 800E if

800A JNC D2, 0E, 80
(LOOP 1) there is no carry.

800D INR B 04 Increment reg. B.

800E
800E DCR C 0D Decrement counter.
(LOOP1)
8008 Jump to address 8008 if
800F JNZ C2, 08, 80
(LOOP2) the counter is non zero.

8012 INX H 23 Increment H-L pair.

Move the result from reg.
8013 MOV M, A 77
A to memory.
8014 INX H 23 Increment H-L pair.
Move the carry from reg.
8015 MOV M, B 70
B to memory.
8016 HLT 76 Halt.
PROGRAM:

TABULATION:-

INPUT:
 31

ADDRESS DATA

8100 04
(No. of Count)

8101

8102

8103

8104

OUTPUT:

ADDRESS DATA

8105
(SUM)

8106
(CARRY)

HAND CALCULATION:
 32

RESULT:

Thus an assembly language program sum of series is written and executed.

*******

FLOW CHART:
 33
START

Load H-L pair with address of first operand’s memory location

Move the first operand from memory to register C

Increment H-L pair

Load D-E pair with address of memory location

Move the content from memory to accumulator

Store the result in accumulator to D-E pair

Increment H-L pair

Increment D-E pair

Decrement counter

NO
If
Zero =
?

YES

STOP

EX. NO.: 8
DATA TRANSFER
DATE:
 34
AIM:

To write and execute an assembly language program to move the given set of numbers
from one set of memory location to another set of memory location.

PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

Load H-L pair with

8000 LXI H, 8100h 21, 00, 81
address 8100.

Move the counter from

8003 MOV C, M 4E
memory to reg. C.

8004 INX H 23 Increment H-L pair.

Load D-E pair with

8005 LXI D, 8201h 11, 01, 82
address 8201.

8008 Move the content from

8008 MOV A, M 7E
(LOOP) memory to reg. A.
Store the address in
8009 STAX D 12 accumulator to
D-E pair.

800A INX H 23 Increment H-L pair.

800B INX D 13 Increment D-E pair.

800C DCR C OD Decrement counter.

8008 Jump to address 8008 if

800D JNZ C2, 08, 80
(LOOP) the counter is non zero.

8010 HLT 76 Halt.

TABULATION:-

INPUT:
 35

ADDRESS DATA

0A
8100
(No. of Count)

8101

8102

8103

8104

8105

8106

8107

8108

8109

810A

TABULATION:-

OUTPUT:
 36

ADDRESS DATA

8201

8202

8203

8204

8205

8206

8207

8208

8209

820A

RESULT:

Thus an assembly language program for data transferred from one set of memory
location to another set of memory location is written and executed.

*******

FLOW CHART:

START

Load H-L pair with address of first operand’s memory location

 37

Move the first operand from memory to register C

Increment H-L pair to point to next memory location

Move the content from memory to register A

Decrement register C

Increment H-L pair

Compare memory with accumulator

NO
If
Carry = ?
YES

Move the content from memory to register A

Decrement counter

NO
If
Zero = ?
YES

Store the result from accumulator to memory address

EX. NO.: 9 STOP

MAXIMUM OF “N” NUMBERS
DATE:

AIM:
 38
To write and execute an assembly language program to fine the result of maximum of
“N” numbers and the result store in one memory location.

PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

Load H-L pair with
8000 LXI H, 8100h 21, 00, 81
address 8100.
Move the counter from
8003 MOV C, M 4E
memory to reg. C.

8004 INX H 23 Increment H-L pair.

Move the content from

8005 MOV A, M 7E
memory to reg. A.

8006 DCR C 0D Decrement counter.

8007
8007 INX H 23 Increment H-L pair.
(LOOP)
Compare memory with
8008 CMP M 8E
accumulator.
800D Jump to address 800D
8009 JNC D2, 0D, 80
(AHEAD) if there is no carry.
Move the content to
800C MOV A, M 7E
reg. A.
800D
800D DCR C 0D Decrement counter.
(AHEAD)
8007 Jump to address 8007
800E JNZ C2, 07, 80
(LOOP) if there is non zero.
Store the result in
8011 STA 8200h 32, 00, 82
memory address.

8014 HLT 76 Halt.

TABULATION:-

INPUT:

ADDRESS DATA
 39
0C
8100
(No. of Count)

8101

8102

8103

8104

8105

8106

8107

8108

8109

810A

810B

810C

810D

OUTPUT:
 40

ADDRESS DATA

8200

RESULT:

Thus an assembly language program for data transferred from one set of memory
location to another set of memory location is written and executed.

*******

FLOW CHART:

START
 41
Load H-L pair with address of first operand’s memory location

Move the operand from memory to register A

Move the operand from register A to register B

AND operation 0F with accumulator

Move the content from reg. A to reg. C

Move the content from reg. B to reg. A

AND operation F0 with accumulator

Rotate accumulator right in 4 times

Move the content from reg. A to reg. D

EX. NO.:10 DECIMAL TO HEXADECIMAL

DATE:

AIM:

To write and execute an assembly language program for decimal to hexadecimal

conversion.

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

 42
8010 MVI A, 00h 3E, 00 Initialize reg. A with 00.
8012 MVI E, 0Ah 1E, 0A Initialize reg. E with 0A.
8014
8014 ADD E 83 Add reg. E with reg. A.
(DO)
8015 DCR D 15 Decrement reg. D.
8014 Jump to address 8014
8016 JNZ C2, 14, 80
(DO) if there is non zero.
8019 ADD C 81 Add reg. C with reg. A.
Store the result in accumulator
801A STA 8200h 32, 00, 82
to memory address 8200.
801D HLT 76 Halt.
PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND OP-CODE COMMENTS

Load H-L pair with address
8000 LXI H, 8100h 21, 00, 81
8100.
Move the content from memory
8003 MOV A, M 7E
to reg. A.
Move the content from reg. A to
8004 MOV B, A 47
reg. B.
AND operation 0F with
8005 ANI 0F E6, 0F
accumulator.
Move the content from reg. A to
8007 MOV C, A 4F
reg. C.
Move the content from reg. B to
8008 MOV A, B 78
reg. A.
AND operation F0 with
8009 ANI F0 E6, F0
accumulator.
800B RRC 0F Rotate accumulator right.
800C RRC 0F Rotate accumulator right.
800D RRC 0F Rotate accumulator right.
800E RRC 0F Rotate accumulator right.
Move the content from reg. A to
800F MOV D, A 57
reg. D.

FLOW CHART:
 43
Initialize 00 with register A

Initialize 00 with register A

Initialize 0A with register E

Add register E with accumulator

Decrement register D

NO If
Zero =
?

YES
Add register C with accumulator

Store the result in accumulator to memory address

STOP
TABULATION:-

INPUT:

ADDRESS DATA

8100
 44

OUTPUT:

ADDRESS DATA

8200

HAND CALCULATION:

RESULT:

Thus an assembly language program for conversion of decimal to hexadecimal is

written and executed.

*******