Semiconductor Material Procession

The semiconductor materials we study are single crystal. So first of all we consider how we grow
semiconductor crystals, specifically the silicon crystal because 95 % of the semiconductor material used
by the electronic industry is silicon. The basic process flow from starting materials to polished wafers is
shown in figure below:

Star'ng
materials

Dis'lla'on and reduc'on

Polycrystalline
Semiconductor

Crystal Growth
Single
Crystal
Grind, Saw, Polish

Wafer

The starting material for silicon is relatively pure form of sand (SiO2) called quartzite. This is placed in a
furnace with various forms of carbon (coal, coke and wood chips). Although a number of reactions takes
place in the furnace. The overall reaction is

SiC ( Solid ) + SiO 2 ( Solid ) ® Si ( Solid ) + SiO ( gas ) + CO(gas)

This reaction takes place in a reactor containing a resistance-heated silicon rod, which serves as the
nucleation point for the deposition of silicon. The ESG (Electronic-grade silicon), a polycrystalline
material of high purity, is the raw material used to prepare device-quality, single crystal silicon. Pure ESG
generally has impurity concentration in the parts-per-billion range.
The polycrystalline silicon is now ready for the crystal-growing process. The most common crystal
growth method is the CZOCHRALSKI Technique.
CZOCHRALSKI Technique
This technique uses an apparatus called a crystal puller shown in figure (1) below. A simplified version is
shown in figure (2). The puller has three main components:
a) A furnace, which includes a fused-silicon (SiO2) crucible, a graphite susceptor, a rotation
mechanism (Clockwise), a heating element and a power supply.
b) A crystal-pulling mechanism, which includes a seed holder and a rotation mechanism (Counter
Clockwise) and
c) An ambient control, which includes a gas source (Argon), a flow control and an exhaust system.
In addition, the puller has an overall microprocessor based control system to control
process parameters such as temperature, crystal diameter, pull rate and rotation speed as well as to
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 permit programmed process steps. Also various sensors and feedback loops allow the control
system to respond automatically.

Figure (1) Figure (2)

In the crystal growing process, polycrystalline silicon (ESG) is placed in the crucible and the
furnace is heated above the melting temperature (14120C) of silicon. A suitably oriented seed crystal
(<111>) is suspended over the crucible in a seed holder. The seed is inserted into the melt. Part of it melts,
but the tip of the remaining seed crystal still touches the liquid surface. It is then slowly withdrawn.
Progressive freezing at the solid-liquid interface yields a large single crystal. A typical pull rate is a few
millimeters per minute. For large-diameter silicon ingot, an external magnetic field is applied to basic
CZOCHRZLSKI puller to control the concentration of defects, impurities and oxygen contents.
In crystal growth, a known amount of dopant (Boron for P-type and Phosphorus for n-type) is added to the
melt to obtain the desired doping concentration in the grown crystal.
Float-Zone Process (Zone Refining Process)

This process can be used to grow silicon that has lower contaminations than that normally obtained from
CZOCHRALSKI technique. A schematic set up of the float zone process is shown in figure below. A high-
purity polycrystalline rod with a seed crystal at the bottom is held in a vertical position and rotated. The
rod is enclosed in a quartz envelope within which an inert atmosphere (Argon) is maintained. During the
operation, a small zone (few centimeters in length) of the crystal is kept molten by a radio-frequency
heater, which is moved from the seed upward so that this floating zone traverses the length of the rod. The
molten silicon is retained by surface tension between the melting and growing solid-silicon faces. As the
floating zone moves upward, single-crystal silicon freezes at the zones retreating end and grows an
extension of the seed crystal. Materials with higher resistivity can be obtained from the Float-Zone
Process, because it can be used to purify the crystal more easy. Furthermore, since no crucible is used in
the Float-Zone process, there is no contamination from the crucible. At the present time, float-zone
crystals are used mainly for high power, high voltage devices, where high resistivity materials are
required.
These two crystal growth techniques can also be used to remove impurities. A single pass in a float
zone process does not produce as much purification as a single Czochralski growth. However, multiple

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float-zone passes can be performed on a rod much more easily than a crystal can be grown, the end region
cropped off, and regrown from the melt.

Note that there is a substantial reduction of impurity concentration in the rod after each pass.
Therefore, the float-zone process is ideally suited for crystal purification. This process is also called the
Zone-Refining Process, which can provide a very high purity level of the raw material.
Wafer Shaping:
After a crystal is grown, the first shaping operation is to remove the seed and the other end of the
ingot, which is last to solidify. The next step is to grind the surface so that the diameter of the material is
defined. After that one or more flat regions are ground along the length of the ingot. These regions or flats
mark the specific crystal orientation of the ingot and the conductivity type of the material. The largest flat,
the primary flat, allows a mechanical locator in automatic processing equipment to position the wafer and
to orient the devices relative to the crystal. Other smaller flats called secondary flats are ground to identify
the orientation and conductivity type of the crystal as shown in figure below. For crystals with diameter
equal or larger than 200 mm, no flats are ground.
The ingot is ready to be sliced by diamond saw into wafers. Slicing determines four wafer parameters:
a) Surface orientation (For example <111> or <100>).
b) Thickness (For example 0.5- 0.7 mm depending on wafer diameter).
c) Taper (wafer thickness variation from one end to another).
d) Bow (surface curvature of the wafer).
After slicing, both sides of the wafer are lapped using a mixture of Al2O3 and glycerin to produce a
typical flatness uniformity within 2 micro meter. The lapping operation usually leaves the surface and
edges of the wafer damaged and contaminated. The damaged and contaminated regions can be removed
by chemical etching. The final step of wafer shaping is polishing. Its purpose is to provide a smooth,
specular surface where device features can be defined by Lithographic Processes.
Lithography: Lithography or photolithography is used to define the geometry of the P-N junction.
After the formation of SiO2, the wafer is coated with an ultraviolet light sensitive material called a
photoresist, which is spun on the wafer surface by a high speed spinner. After spinner, the wafer is baked
at about 80-1000C to drive the solvent out of the resist and to harden the resist for improved adhesion. The
next step is to expose the wafer through a patterned mask using an ultraviolet light source. The exposed
region of the photoresist-coated wafer undergoes a chemical reaction depending on the type of resist. The
area exposed to light become polymerized and difficult to remove in an etchant. The polymerized region
remains when the wafer is placed in a developer whereas the unexposed region dissolves and washes

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away. The wafer is again baked to 120 - 1800C for 20 minutes to enhance the adhesion and improve the
resistance to the subsequent etching process. Then an etch using buffered hydrofluoric acid (HF) removes
the unprotected SiO2 surface. Finally the resist is stripped away by a chemical solution or an oxygen
plasma system. The wafer is now ready for forming the P-N junction by a diffusion or ion implantation
process.
Impurity Doping: It is the introduction of controlled amounts of impurity dopants into semiconductors.
The impurity doping has been mainly to change the electrical properties of semiconductor. There are two
key methods of impurity doping:
a) Diffusion
b) Ion Implantation
Both diffusion and ion implantation are used for fabricating discrete devices and Integrated circuits
because these processes generally complement each other. For example: diffusion is used to form a deep
junction whereas ion implantation is used to form a shallow junction.
Diffusion: Diffusion of impurities is typically done by placing semiconductor wafers in a carefully
controlled high-temperature quartz tube furnace and passing a gas mixture that contains the desired dopant
through it. The temperature ranges between 8000C and 12000C for Silicon. The number of dopant atoms
that diffuses into the semiconductor is related to the partial pressure of the dopant impurity in the gas
mixture. For diffusion in silicon, Boron is most popular dopant for introducing a P-type impurity whereas
Arsenic and Phosphorus are used extensively as N-type dopants. These three elements are highly soluble
in silicon. These dopants can be introduced in several ways:
i) Solid sources (BN for Boron, As2O3 for Arsenic and P2O5 for Phosphorus)
ii) Liquid sources (BBr3,AsCl3 and POCl3) and
iii) Gaseous sources (B2H6, AsH3 and PH3)
However liquid sources are most commonly used. The schematic diagram of the furnace and gas flow
arrangement for a liquid source is shown in figure below:

An example of chemical reaction for phosphorus diffusion using a liquid source is

4POCl3 + 3O2 ® 2P2O5 + 6Cl2

The P2O5 forms a glass on silicon wafer and is then reduces to phosphorus by silicon

2P2O5 + 5Si ® 4P + 5SiO2

And the phosphorus is released and diffuses into the silicon and Cl2 is vented.

Ion Implantation:
Ion implantation is the introduction of energetic, charged particles into a substrate such as silicon.
Implantation energies are between 1 KeV and 1 MeV, resulting ion distributions with average depths
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ranging from 10 nanometer to 10 micrometer. The ion dose is expressed as the number of ions implanted
into 1 cm2 of the semiconductor surface area. The main advantages of ion implantations are:- its more
precise control and reproducibility of impurity doping and its lower processing temperature compared
with those of the diffusion process.
The figure shows a medium-energy ion implanter. The ion source has a heated filament to break up source
gas such as BF3 or AsH3 into charged ions (B+ or As+). An extraction voltage around 40 KV, causes the
charged ions to move out of the ion-source chamber into a mass analyzer. The magnetic field of the
analyzer is chosen such that only ions with the desired mass-to-charge ratio can travel through it without
being filtered. The selected ions then enter the acceleration tube, where they are accelerated to the
implantation energy as they move from high voltage to ground. Apertures ensure that the ion beam is well
collimated. The pressure in the implanter is kept below 10-4 Pascal to minimize ion scattering by gas
molecules. The ion beam is then scanned over the wafer surface using electrostatic deflection plates and is
implanted into the semiconductor substrate.
The energetic ions lose their energies through collision with electrons and nuclei in the substrate and
finally come to rest at some depth within the lattice. The average depth can be controlled by adjusting the
acceleration energy. The dopant dose can be controlled by monitoring the ion current during implantation.
The principle side effect is the disruption or damage of the semiconductor lattice due to ion collision.
Therefore, a subsequent annealing treatment is needed to remove these damages.
EPITAXIAL-GROWTH Techniques:
In an epitaxial process, the substrate wafer acts as the seed crystal. The epitaxial layer can be grown at a
temperature below (30 – 50 % below) the melting point. The common techniques for epitaxial growth are:
1) Chemical vapor deposition (CVD) or Vapour phase epitaxy (VPE)
2) Molecular-beam epitaxy (MBE)
Chemical vapor deposition: In this process, an epitaxial layer is formed by a chemical reaction between
gaseous compounds. CVD can be performed at atmospheric pressure (APCVD) or at low pressure
(LPCVD).
The figure shows three common susceptors for epitaxial growth. The geometric shape of the susceptor
provides the name for the reactor: Horizontal, Pancake and Barrel susceptors – all made from graphite
blocks.
The mechanism of CVD involves a number of steps:
a) The reactants such as the gases and dopants are transported to the substrate region.
b) They are transferred to the substrate surface where they are adsorbed.
c) A chemical reaction occurs, catalyzed at the surface, followed by growth of the epitaxial layer.
d) The gaseous products are desorbed into the main gas stream.
e) The reaction products are transported out of the reaction chamber.
Four silicon sources have been used for VPE growth. They are:
i) Silicon Tetrachloride (SiCl4).
ii) Dichlorosilane (SiH2Cl2).
iii) Trichlorosilane (SiHCl3).
iv) Silane (SiH4).

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 Silicon tetrachloride has been widely industrial use. The typical reaction temperature is 12000C. Other
silicon sources are used because of lower reaction temperature. The substitution os a hydrogen atom
for each chlorine atom from SiCl4 permits about a 500C reduction in the reaction temperature. The
overall reaction of SiCl4 that results in the growth of silicon layer is :

SiCl4 (gas) + 2H2 (gas) É Si (Solid) + 4HCl (gas)

An additional competing reaction is taking place along with the above equation.

SiCl4 (gas) + Si (Solid) É 2SiCl2 (gas)

As a result, if the silicon tetrachloride concentration is too high, etching rather than growth of silicon will
take place. Note that initially the growth rate increases linearly with an increasing concentration of SiCl4.
As the concentration of SiCl4 is increased, a maximum growth rate is reached. Beyond that growth rate
starts to decrease and eventually etching of the silicon will occur. Silicon is usually grown in the low
concentration region.
If the carrier gas entering the reactor contains hydrochloric acid, removal or etching will take place. This
etching operation is used for in-situ (appropriate position) cleaning of the silicon wafer prior to epitaxial
growth.
The dopant is introduced at the same time as the SiCl4 during epitaxial growth. Gaseous Diborane (B2H6)
is use as the P-type dopant whereas Phosphine (PH3) and Arsine (AsH3) are used as n-type dopant.
Molecular beam epitaxy (MBE): It is an epitaxial process involving the reaction of one or more thermal
beams of atoms or molecules with a crystalline surface under ultrahigh-vacuum conditions. MBE method
enables the precise fabrication of semiconductor hetero-structures having thin layers.
Planar process:
Today, planar technology is extensively used for integrated circuit (IC) fabrication. The major steps of a
planar process are shown in figure below:
These steps include oxidation, lithography, ion implantation and metallization.
Oxidation: The development of a high quality SiO2 has helped to establish the dominance of silicon in the
production of commercial IC’s. Generally, SiO2 functions as an insulator in a number of device structures

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or as a barrier to diffuse or implantation during device fabrications. In the fabrication of a p-n junction, the
SiO2 film is used to define the junction area.
There are two SiO2 growth method: dry oxidation and wet oxidation depending on whether dry oxygen or
water vapor is used. Dry oxidation is usually used to form thin oxides in a device structure because of its
good Si-SiO2 interface characteristics, whereas wet oxidation is used for thicker layer because of its higher
growth rate. After the oxidation process, a SiO2 layer is formed all over the wafer surface.

Metallization: This process is used to form ohmic contacts and interconnections. This process involves
the deposition of a metal (Al) over the entire surface of the silicon. The required interconnection pattern is
the selectively etched. The Al is deposited by heating it in vacuum until it vaporizes. The vapor’s then
contact the silicon surface and condense to form a solid – Al layer.