Dynamic Logic

Dynamic CMOS Design

• Static CMOS logic with a fan-in of N requires 2N devices.
• The pseudo-NMOS logic style requires only N + 1 transistors to
implement an N input logic gate, but unfortunately it has static power
dissipation.
• An alternate logic style called dynamic logic is presented that obtains
a similar result, while avoiding static power consumption.
• With the addition of a clock input, it uses a sequence of pre-charge
and conditional evaluation phases.
Dynamic Logic: Basic Principles
• The PDN (pull-down network) is constructed
exactly as in complementary CMOS.
• The operation of this circuit is divided into two
major phases: pre-charge and evaluation, with
the mode of operation determined by the clock
signal CLK.
Dynamic Logic: Basic Principles
• Pre-charge
• When CLK = 0, the output node Out is precharged
to VDD by the PMOS transistor Mp.
• During that time, the evaluate NMOS transistor Me
is off, so that the pull-down path is disabled.
• The evaluation FET eliminates any static power that
would be consumed during the pre-charge period
(this is, static current would flow between the
supplies if both the pull-down and the pre-charge
device were turned on simultaneously).
Dynamic Logic: Basic Principles
• Evaluation
• For CLK = 1, the precharge transistor Mp is off, and
the evaluation transistor Me is turned on.
• The output is conditionally discharged based on the
input values and the pull-down topology.
• If the inputs are such that the PDN conducts, then a
low resistance path exists between Out and GND
and the output is discharged to GND.
• If the PDN is turned off, the precharged value
remains stored on the output capacitance CL,
which is a combination of junction capacitances,
the wiring capacitance, and the input capacitance
of the fan-out gates.
Dynamic Logic: Basic Principles
• Evaluation
• During the evaluation phase, the only possible path
between the output node and a supply rail is to
GND.
• Consequently, once Out is discharged, it cannot be
charged again till then next precharge operation.
• The inputs to the gate can therefore make at most
one transition during evaluation.
Dynamic Logic: Basic Principles
• Evaluation
• Notice that the output can be in the high-
impedance state during the evaluation period if the
pull-down network is turned off.
• This behavior is fundamentally different from the
static counterpart that always has a low resistance
path between the output and one of the power
rails.
Dynamic Logic: Basic Principles
• Example
• During the precharge phase (CLK=0), the output is
precharged to VDD regardless of the input values
since the evaluation device is turned off.
• During evaluation (CLK=1), a conducting path is
created between Out and GND if (and only if) A·B+C
is TRUE.
• Otherwise, the output remains at the precharged
state of VDD.
• The following function is thus realized:
Important properties of Dynamic Logic
• The logic function is implemented by the NMOS pull-down network.
The construction of the PDN proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower
than in the static case: N + 2 versus 2N.
• It is non-ratioed.
• The sizing of the PMOS precharge device is not important for real-izing proper
functionality of the gate.
• The size of the precharge device can be made large to improve the low-to-high
transition time (of course, at a cost to the high-to-low transition time).
• There is however, a trade-off with power dissipation since a larger precharge
device directly increases clock-power dissipation.
Important properties of Dynamic Logic
• It only consumes dynamic power. Ideally, no static current path ever
exists between VDD and GND.
• The overall power dissipation, however, can be significantly higher compared to
a static logic gate.
• The logic gates have faster switching speeds.
• There are two main reasons for this.
• The first (obvious) reason is due to the reduced load capacitance attributed to
the lower number of transistors per gate and the single-transistor load per fan-
in.
• Second, the dynamic gate does not have short circuit current, and all the
current provided by the pull-down devices goes towards discharging the load
capacitance.
Important properties of Dynamic Logic
• Noise margins and switching thresholds have been defined as static
quantities that are not a function of time.
• To be functional, a dynamic gate requires a periodic sequence of
precharges and evaluations. Pure static analysis, therefore, does not
apply.
• During the evaluate period, the pull-down network of a dynamic
inverter starts to conduct when the input signal exceeds the threshold
voltage (VTn) of the NMOS pull-down transistor.
Design Consideration (PUN based design)
• It is also possible to implement dynamic logic using a complimentary
approach, where the output node is connected by a pre-discharge
NMOS transistor to GND, and the evaluation PUN network is
implemented in PMOS.
• The operation is similar: during precharge, the output node is
discharged to GND.
• During evaluation, the output is conditionally charged to VDD.
• This p-type dynamic gate has the disadvantage of being slower than the
n-type due to the lower current drive of the PMOS transistors.
Speed and Power Dissipation of Dynamic Logic
• After the pre-charge phase, the output is high. For a low input signal,
no additional switching occurs. As a result, tpLH = 0!
• The high-to-low transition, on the other hand, requires the discharging
of the output capacitance through the pull-down network.
• Therefore, tpHL is proportional to CL and the current-sinking capabilities of the
pull-down network

• The above analysis is somewhat unfair, because it ignores the influence

of the pre-charge time on the switching speed of the gate
Speed and Power Dissipation of Dynamic Logic
• The precharge time is determined by the time it takes to charge CL
through the PMOS precharge transistor.
• During this time, the logic in the gate cannot be utilized.
• However, very often, the overall digital system can be designed in such
a way that the precharge time coincides with other system functions.
• For instance, the precharge of the arithmetic unit in a microprocessor can
coincide with the instruction decode.
• The designer has to be aware of this “dead zone” in the use of dynamic logic,
and should carefully consider the pros and cons of its usage, taking the overall
system requirements into account.
A Four-Input Dynamic NAND Gate
• Due to the dynamic nature of the gate, the
derivation of the voltage-transfer characteristic
diverges from the traditional approach.
• We will assume that the switching threshold of the
gate equals the threshold of the NMOS pull-down
transistor.
• This results in asymmetrical noise margins, as
shown in Table.
A Four-Input Dynamic NAND Gate
• The dynamic behavior of the gate is
simulated with SPICE.
• It is assumed that all inputs are set high
as the clock transitions high.
• On the rising edge of the clock, the
output node is discharged.
• The resulting transient response is
plotted in Figure, and the propagation
delays are summarized in Table 6.9.
• The duration of the precharge cycle can
be adjusted by changing the size of the
PMOS precharge transistor.
Transient response of dynamic NAND gate.
• Making the PMOS too large should be
avoided, however, as it both slows
down the gate, and increases the
capacitive load on the clock line.
• For large designs, the latter factor
might become a major design concern
as the clock load can become
excessive and hard to drive.
Transient simulation of the output voltage
• Consider the four input NAND
gate with all inputs tied
together, and making a partial
low-to-high transition.
• Figure shows a transient
simulation of the output
voltage for three different
input transitions—to 0.45V,
0.5V and 0.55V, respectively.

• We have defined the switching

threshold of the dynamic gate
as the device threshold.
Transient simulation of the output voltage
• The amount by which the
output voltage drops is a
strong function of the input
voltage and the available
evaluation time.
• The noise voltage needed to
corrupt the signal has to be
larger if the evaluation time is
short.
• In other words, the switching
threshold is really a function of
the evaluation time.
Power dissipation of a dynamic gate
• Dynamic logic presents a significant advantage.
• There are three reasons for this.
• First, the physical capacitance is lower since dynamic logic uses fewer
transistors to implement a given function. Also, the load seen for each
fanout is one transistor instead of two.
• Second, dynamic logic gates by construction can at most have one
transition per clock cycle. Glitching (or dynamic hazards) does not occur
in dynamic logic.
• Finally, dynamic gates do not exhibit short circuit power since the pull-
up path is not turned on when the gate is evaluating.
Power dissipation of a dynamic gate
• They are offset by other considerations:
• The clock power of dynamic logic can be significant, particularly since
the clock node has a guaranteed transition on every single clock cycle;
• The number of transistors is higher than the minimal set required for
implementing the logic;
• Short-circuit power may exist when leakage-combatting devices are
added (as will be discussed further);
• Most importantly, dynamic logic generally displays a higher switching
activity due to the periodic pre-charge and discharge operations
Power dissipation of a dynamic gate
• Transition probability for a static gate was shown to be p0
• p1= p0(1-p0).
• For dynamic logic, the output transition probability does not depend on
the state (history) of the inputs, but rather on the signal probabilities
only.
• For an n-tree dynamic gate, the output makes a 0→1 transition during
the precharge phase only if the output was discharged during the
preceding evaluate phase.
• The 0→1 transition probability for an n-type dynamic gate hence equals

• where p0 is the probability that the output is zero. This number is

always larger or equal to p0.p1
Power dissipation of a dynamic gate
• For uniformly distributed inputs, the transition probability for an N-
input gate is:

• where N0 is the number of zero entries in the truth table of the logic
function
Activity estimation in dynamic logic
• For equi-probable inputs, there is then a
75% probability that the output node of
thedynamic gate will discharge
immediately after the precharge phase,
implying that the activityfor such a gate
equals 0.75 (i.e PNOR= 0.75
[Link]^[Link]).
• The corresponding activity is a lot smaller,
3/16, for a static implementation.
• For a dynamic NAND gate, the transition probability is 1/4 (since there is a
25% probability the output will be discharged) while it is 3/16 for a static
implementation.
• Though these example illustrate that the switching activity of dynamic logic
is generally higher, it should be noted that dynamic logic has lower physical
capacitance.
Issues in Dynamic Design
• Dynamic logic clearly can result in high performance solutions compared
to static circuits.
• However, there are several important considerations that must be taken
into account if one wants dynamic circuits to function properly.
• This include
• charge leakage,
• charge sharing,
• backgate (and in general capacitive) coupling, and
• clock feedthrough.
Charge Leakage
• If the pull-down network is off,
the output should ideally remain
at the pre-charged state of VDD
during the evaluation phase.
• However, this charge gradually
leaks away due to leakage
currents, eventually resulting in a
malfunctioning of the gate.
Charge Leakage
• Source 1 and 2 are the reverse-biased diode and
sub-threshold leakage of the NMOS pull-down
device M1, respectively.
• The charge stored on CL will slowly leak away due
these leakage sources, assuming that the input is
at zero during evaluation.
• Charge leakage causes a degradation in the high
level.
• Dynamic circuits therefore require a minimal
clock rate, which is typically on the order of a few
kHz.
• This makes the usage of dynamic techniques
unattractive for low performance products such
as watches, or processors that use conditional
clocks
Charge Leakage
• Note that the PMOS precharge device also
contributes some leakage current due to the
reverse bias diode (source 3) and the
subthreshold conduction (source 4).
• To some extent, the leakage current of the
PMOS counteracts the leakage of the pull-
down path.
• As a result the output voltage is going to be
set by the resistive divider composed of the
pull-down and pull-up paths.
Charge Leakage
• Consider the simple inverter with all
devices set at 0.5mm/0.25mm.
• Once the output drops below the
switching threshold of the fan-out logic
gate, the output is interpreted as a low
voltage.
• Notice that the output settles to an
intermediate voltage. This is due to the
leakage current provided by the PMOS
pull-up
Charge Leakage (Solution)
• Leakage is caused by the high impedance
state of the output node during the
evaluate mode, when the pull down path
is turned off.
• The leakage problem can be counteracted
by reducing the output impedance on the
output node during evaluation.
• This is often done by adding a bleeder
transistor as shown in Figure
Charge Leakage (Solution)
• The only function of the bleeder—a
pseudo-NMOS-like pull-up device—is to
compensate for the charge lost due to the
pull-down leakage paths.
• To avoid the ratio problems associated
with this style of circuit and the
associated static power consumption, the
bleeder resistance is made high, or, in
other words, the device is kept small.
Charge Leakage (Solution)
• Often, the bleeder is implemented in a
feedback configuration to eliminate the
static power dissipation
Charge Sharing
• During the precharge phase, the output
node is precharged to VDD.
• Assume that all inputs are set to 0 during
pre-charge, and that the capacitance Ca is
discharged.
• Assume further that input B remains at 0
during evaluation, while input A makes a
0-1 transition, turning transistor Ma on.
• The charge stored originally on capacitor
CL is redistributed over CL and Ca
• This causes a drop in the output voltage,
which cannot be recovered due to the
dynamic nature of the circuit.
Charge Sharing
• The influence on the output voltage is readily
calculated.
• Under the above assumptions, the following initial
conditions are valid: Vout(t = 0) = VDD and VX(t = 0) = 0.
• Two possible scenarios must be considered:
Charge Sharing
• Two possible scenarios must be considered:

• Which of the above scenarios is valid is determined by

the capacitance ratio.
• The boundary condition between the two cases can be
determined by setting ∆Vout equal to VTn in Eq.
yielding
Charge Sharing (Solution)
• Overall, it is desirable to keep the value of ∆Vout
below |VTp|.
• The output of the dynamic gate might be connected to
a static inverter, in which case the low level of Vout
would cause static power consumption.
• One major concern is circuit malfunction if the output
voltage is brought below the switching threshold of
the gate it drives.
 Charge Sharing (Example)
• The worst-case change in output
is obtained by exposing the
maximum amount of internal
capacitance to the output node
during the evaluation period.
• This happens for A’BC or AB’C.

• a worst-case change of 30/(30+50) * 2.5V = 0.94V.

• To ensure that the circuit functions correctly, the switching threshold
of the connecting inverter should be placed below 2.5- 0.94 = 1.56V.
Charge Sharing (Solution)
• The most common and effective
approach to deal with the charge
redistribution is to also precharge
critical internal nodes, as is shown in
Figure.
• Since the internal nodes are charged
to VDD during precharge, charge
sharing does not occur.
• This solution obviously comes at the
cost of increased area and
capacitance.
Capacitive Coupling
• The high impedance of
the output node makes
the circuit very sensitive
to crosstalk effects.
• A wire routed over a
dynamic node may
couple capacitively and
destroy the stateof the
floating node.
• Another equally
important form of
capacitive coupling is the
back-gate (or output-to-
input) coupling
Capacitive Coupling
• A transition in the input
In of the static gate may
cause the output of the
gate (Out2) to go low.
• This output transition
couples capacitively to
the other input of the
gate, the dynamic node
Out1, through the gate-
source and gate-drain
capacitances of transistor
M4.
Capacitive Coupling
• A simulation of this effect
is shown in Figure and
demonstrates that the
output of the dynamic
gate can drop
significantly.
• This further causes the
output of the static NAND
gate not to drop all the
way down to 0V, and a
small amount of static
power is dissipated.
Capacitive Coupling
• If the voltage drop is
large enough, the circuit
can evaluate incorrectly,
and the NAND output
may not go low.
• When designing and
laying out dynamic
circuits, special care is
needed to minimize
capacitive coupling.
Clock-Feedthrough
• A special case of capacitive coupling is
clock-feedthrough, an effect caused by
the capacitive coupling between the
clock input of the precharge device and
the dynamic output node.
• The coupling capacitance consists of the
gate-to-drain capacitance of the pre-
charge device, and includes both the
overlap and the channel capacitances.
• This capacitive coupling causes the
output of the dynamic node to rise above
VDD on the low-to-high transition of the
clock, assuming that the pull-down
network is turned off
Clock-Feedthrough
• The danger of clock feedthrough is that it
may cause the (normally reverse-biased)
junction diodes of the precharge
transistor to become forward-biased.
• This causes electron injection into the
substrate, which can be collected by a
nearby high impedance node in the 1
state, eventually resulting in faulty
operation.
• CMOS latchup might be another result of
this injection.
• For all purposes, high-speed dynamic
circuits should be carefully simulated to
ensure that clock-feedthrough effects
stay within bounds
 Cascading Dynamic Gates
• On the rising edge of the clock, output
Out1 starts to discharge.
• The second output should remain in the
precharged state of VDD as its expected
value is 1 (Out1 transitions to 0 during
evaluation).
• However, there is a finite propagation
delay for the input to discharge Out1 to
GND. Therefore, the second output also
starts to discharge.
• As long as Out1 exceeds the switching threshold of the second gate, which is
approximately equals VTn, a conducting path exists between Out2 and GND,
and precious charge is lost at Out2
 Cascading Dynamic Gates
• The conducting path is only disabled
once Out1 reaches VTn, and turns off
the NMOS pull-down transistor.
• This leaves Out2 at an intermediate
voltage level.

• The correct level will not be recovered, as dynamic gates rely on capacitive
storage in contrast to static gates, which have dc restoration.
• The charge loss leads to reduced noise margins and potential malfunctioning.
Cascading Dynamic Gates
• The cascading problem arises because the outputs of each gate—and
hence the inputs to the next stages—are precharged to 1.
• This may cause inadvertent discharge in the beginning of the
evaluation cycle. Setting all the inputs to 0 during precharge addresses
that concern
• In other words, correct operation is guaranteed as long as the inputs
can only make a single 0 to 1 transition during the evaluation period
• Transistors are only be turned on when needed, and at most once per
cycle.
• A number of design styles complying with this rule have been
conceived
Domino Logic • When doing so, all transistors in the
pull-down network are turned off
after precharge, and no inadvertent
discharging of the storage capacitors
can occur during evaluation.
• In other words, correct operation is
guaranteed as long as the inputs can
only make a single 0->1 transition
during the evaluation period
• Transistors are only be turned on
when needed, and at most once per
cycle.
Domino Logic • If one assumes that all the inputs of
a Domino gate are outputs of other
Domino gates, then it is ensured
that all inputs are set to 0 at the end
of the pre-charge phase, and that
the only transitions during
evaluation are 0->1 transitions.
• The formulated rule is hence
obeyed.
Domino Logic • The introduction of the static
inverter has the additional
advantage that the fan-out of the
gate is driven by a static inverter
with a low-impedance output, which
increases noise immunity.
• The buffer furthermore reduces the
capacitance of the dynamic output
node by separating internal and load
capacitances
Domino Logic • Consider now the operation of a
chain of Domino gates.
• During precharge, all inputs are set
to 0. During evaluation, the output
of the first Domino block either stays
at 0 or makes a 0->1 transition,
affecting the second gate.
• This effect might ripple through the
whole chain, one after the other,
similar to a line of falling
dominoes—hence the name.
Domino Logic • Domino CMOS has the following
properties:
• Since each dynamic gate has a static
inverter, only non-inverting logic can
be implemented. Although there are
ways to deal with this, as is discussed
in a subsequent section, this is major
limiting factor, and pure Domino design
has become rare
• Very high speeds can be achieved: only
a rising edge delay exists, while tpHL
equals zero. The inverter can be sized
to match the fan-out, which is already
much smaller than in the
complimentary static CMOS case, as
only a single gate capacitance has to be
accounted for per fan-out gate.
 Domino Logic
• Since the inputs to a Domino gate are low during pre-charge, it is tempting
to eliminate the evaluation transistor as this would reduce clock load and
increase pull-down drive.
• However, eliminating the evaluation device extends the pre-charge cycle:
the pre-charge now has to ripple through the logic network as well.
 Domino Logic
• If the primary input In1 is 1 during evaluation, the output of each dynamic gate
is 0 and the output of each static inverter is 1.
• On the falling edge of the clock, the precharge operation is started.
• Assume further that In1 makes a high-to-low transition.
• The input to the second gate is initially high, and it takes two gate delays before
In2
• is driven low. During that time, the second gate cannot precharge its output, as
the pull-down network is fighting the precharge device.
 Domino Logic
• Similarly, the third gate has to wait till the second gate precharges before it
can start precharging, etc.
• Therefore the time taken to precharge the logic circuit is equal to its critical
path.
• Another important negative is the extra power dissipation when both pull-
up and pull-down devices are on. It is therefore good practice to always
utilize evaluation devices.
 Dealing with the Non-inverting Property of Domino Logic.
• A major limitation in Domino logic is that only non-inverting logic can be
implemented.
• This requirement has limited the widespread use of pure Domino logic.
There are several ways to deal with the non-inverting logic requirement.
• Figure shows one approach to the problem—reorganizing the logic using
simple boolean transforms such as De Morgan’s Law
 Dual-rail Domino
• Dual-rail Domino is similar in
concept to the DCVSL structure,
but uses a pre-charged load
instead of a static cross-coupled
PMOS load.
• Figure shows the circuit
schematic of an AND/NAND
differential logic gate.

• Note that all inputs come from other differential Domino gates, and are
low during the pre-charge phase, while making a conditional 0->1
transition during evaluation.
Dual-rail Domino
• Using differential Domino, it is
possible to implement any
arbitrary function.
• This comes at the expense of an
increased power dissipation,
since a transition is guaranteed
every single clock cycle
regardless of the input values—
either O or O’ must make a 0->1
transition.
• The function of transistors Mf1 and Mf2 is to keep the circuit static when the
clock is high for extended periods of time (bleeder).

• Notice that this circuit is not ratioed, even in the presence of the PMOS pull-up
devices! Due to its high-performance, this differential approach is very popular,
and is used in several commercial microprocessors..
Optimization of Domino Logic Gates.
• Several optimizations can be performed on Domino logic gates.
• The most obvious performance optimization involves the sizing of the
transistors in the static inverter.
• With the inclusion of the evaluation devices in Domino circuits, all gates
precharge in parallel, and the precharge operation takes only two gate
delays—charging the output of the dynamic gate to VDD, and driving the
inverter output low.
Optimization of Domino Logic Gates.
• The critical path during evaluation goes through the pull-down path of
the dynamic gate, and the PMOS pull-up transistor of the static inverter.
Therefore, to speed up the circuit during evaluation, the beta ratio of
the static inverter should be made high so that its switching threshold is
close to VDD
• This can be accomplished by using a small (minimum) sized NMOS and a
large PMOS device.
• The minimum-sized NMOS only impacts the precharge time, which is
limited in general due to the parallel precharging of all gates.
• The only disadvantage of using a large beta ratio is a reduction in noise
margin.
• A designer should therefor simultaneously consider the reduced noise
margin and performance during the device sizing
Variations of Domino logic (Multiple Output Domino Logic)
• It exploits the fact that certain outputs are
subsets of other outputs to generate a
number of logical functions in a single gate.
• In this example, O3 = C+D is used in all
three outputs, and hence it is implemented
at the bottom of the pull-down network.
• Since O2 equals B ·O3, it can reuse the logic
for O3.
• Notice that the internal nodes have to be
precharged to VDD to produce the correct
results.
Variations of Domino logic (Multiple Output Domino Logic)
• Given that the internal nodes precharge to
VDD, the number of devices driving
precharge devices is not reduced.
•
• However, the number of evaluation
transistors is drastically reduced as they are
amortized over multiple outputs.
• Additionally, this approach results in a
reduction of the fan-out factor, once again
due to the reuse of transistors over multiple
functions.
Variations of Domino logic (Compound Domino)
• Instead of each dynamic gate
driving a static inverter, it is
possible to combine the outputs of
multiple dynamic gates with the aid
of a complex static CMOS gate.

• The outputs of three dynamic structures, implementing O1 = A B C, O2

= D E F and O3 = G H, are combined using a single complex CMOS static
gate that implements O = (o1+o2) o3.
• The total logic function realized this way equals O = A B C D E F + GH.
Variations of Domino logic (Compound Domino)
• Compound Domino is a useful tool for
constructing complex dynamic logic
gates.
• Large dynamic stacks are replaced
using parallel small fan-in structures
and complex CMOS gates.
• For example, a large fan-in Domino
AND can be implemented as parallel
dynamic NAND structures with lower
fan-in that are combined using a static
NOR gate.
• One important consideration in Compound Domino is the problem
associated with back gate coupling.
• Care must be taken to ensure that the dynamic nodes are not affected
by the coupling between the output of the static gates and the output
of dynamic nodes.
Variations of Domino logic (np-CMOS)
• The Domino logic presented in the
previous section has the
disadvantage that each dynamic
gate requires an extra static
inverter in the critical path to make
the circuit functional.

• np-CMOS, provides an alternate approach to cascading dynamic logic

by using two flavors (n-tree and p-tree) of dynamic logic
•
Variations of Domino logic (np-CMOS)
• In a p-tree logic gate, PMOS devices are
used to build a pull-up logic network,
including a PMOS evaluation transistor
• The NMOS predischarge transistor drives
the out-put low during precharge.
• The output conditionally makes a 0->1
transition during evaluation depending on
its inputs.