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Evolutionary Large Language Models for Hardware Security: A

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GLSVLSI '24: Great Lakes Symposium on
Comparative Survey VLSI 2024
June 12 - 14, 2024
MOHAMMAD AKYASH, University of Central Florida, Orlando, FL, United States FL, Clearwater, USA

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HADI M KAMALI, University of Central Florida, Orlando, FL, United States Conference Sponsors:
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GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024 (June 2024)
hps://[Link]/10.1145/3649476.3660390
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 Evolutionary Large Language Models for Hardware Security:
A Comparative Survey
Mohammad Akyash Hadi M Kamali
[Link]@[Link] [Link]@[Link]
ECE Department, University of Central Florida ECE Department, University of Central Florida
Orlando, Florida, USA Orlando, Florida, USA
ABSTRACT Given the pivotal role of SoCs, while substantial efforts have been
Automating hardware (HW) security vulnerability detection and invested in software (SW) testing and debugging, SoC (HW-based)
mitigation during the design phase is imperative for two reasons: (i) testing, validation, and verification remain less mature [30]. The
It must be before chip fabrication, as post-fabrication fixes can be problem worsens while bugs are detected at lower levels of abstrac-
costly or even impractical; (ii) The size and complexity of modern tion, which makes respins extremely difficult (and even impossible,
HW raise concerns about unknown vulnerabilities compromising e.g., post-silicon) [34]. Moreover, existing solutions, from simula-
CIA triad. While Large Language Models (LLMs) can revolutionize tion to formal verification, usually require expertise. Such solutions
both HW design and testing processes, within the semiconductor also suffer from scalability issues, unable to cope with the grow-
context, LLMs can be harnessed to automatically rectify security- ing size and complexity of SoCs [2]. Furthermore, these solutions
relevant vulnerabilities inherent in HW designs. This study ex- cannot address the majority of SoCs’ vulnerabilities due to rapidly
plores the seeds of LLM integration in register transfer level (RTL) evolving threats, such as zero-day attacks.
designs, focusing on their capacity for autonomously resolving With the rapid evolution of LLMs, their capabilities have ex-
security-related vulnerabilities. The analysis involves comparing panded into the domain of SW code generation with remarkable
methodologies, assessing scalability, interpretability, and identi- success, e.g., OpenAI’s Codex [36]. Moreover, the scope of LLMs
fying future research directions. Potential areas for exploration extends to SW code testing and verification while outperforming
include developing specialized LLM architectures for HW secu- techniques like fuzzing [32]. While significant progress has been
rity tasks and enhancing model performance with domain-specific achieved in SW through LLMs, studies at the HW/SoC level, par-
knowledge, leading to reliable automated security measurement ticularly at RTL, have been dispersed. Many studies have initiated
and risk mitigation associated with HW vulnerabilities. the LLMs’ applicability at the HW/SoC level by raising questions
like whether "LLM can generate HDL" or "LLM can validate HW
CCS CONCEPTS designs". Just like in SW, LLMs have the potential to be utilized for
both HW design, testing and validation (see Fig. 1). These studies
• Security and privacy → Security in hardware; • Hardware
show harnessing LLMs’ capability to analyze, comprehend, and
→ Hardware validation; HL and RTL synthesis.
generate/validate complex code structures, might make them a
right target vs. existing formal tools to identify potential security
KEYWORDS
vulnerabilities within RTL codes [3, 37]. However, ensuring the
Large Language Models, Hardware Security, RTL Debugging integrity and security of HW designs, coupled with the potential
ACM Reference Format: for unknown vulnerabilities, presents broader challenges.
Mohammad Akyash and Hadi M Kamali. 2024. Evolutionary Large Lan- This survey aims to offer a useful and comprehensive snapshot
guage Models for Hardware Security: A Comparative Survey. In Great Lakes of rapidly growing use of LLMs in HW/SoC designs, particularly
Symposium on VLSI 2024 (GLSVLSI ’24), June 12–14, 2024, Clearwater, FL, USA. for security. We explore advancements, analyzing the pros and cons
ACM, New York, NY, USA, 6 pages. [Link]
of each method. By examining current approaches, this work high-
lights the innovative application of LLMs to automate the detection
1 INTRODUCTION and resolution of security vulnerabilities in HW designs. Also, we
In today’s semiconductor technology landscape, As system-on-chip investigate future research directions, emphasizing the need for
(SoC) designs integrate more and more intellectual property (IP) specialized LLM architectures and domain-specific knowledge in-
cores, each with unique functionality and security challenges, each tegration. Our goal is to outline a roadmap for harnessing the full
from various vendors, each with ever-increasing complexity, we potential of LLMs in addressing HW security challenges, setting
witness a growing challenge in detecting and fixing vulnerabilities. the stage for more robust and secure HW systems.
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed 2 LLMS FOR SW: ENGINEERING AND TESTING
for profit or commercial advantage and that copies bear this notice and the full citation
on the first page. Copyrights for components of this work owned by others than the
Since the 1950s, many research efforts have been undertaken to de-
author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or velop highly efficient automated code generation tools [38]. These
republish, to post on servers or to redistribute to lists, requires prior specific permission efforts have spanned from traditional program synthesizers [38]1 ,
and/or a fee. Request permissions from permissions@[Link].
GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA 1 Synthesizers aim to automatically generate programs (SW codes), based on a space
© 2024 Copyright held by the owner/author(s). Publication rights licensed to ACM. search over a variety of constraints relevant to domains known as Domain Specific
ACM ISBN 979-8-4007-0605-9/24/06 Languages (DSLs). These techniques are mostly limited to pre-defined DSLs and thus
[Link] suffer scalability, being general-purpose, and adaptability issues [1].

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GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA Mohammad Akyash and Hadi M Kamali

Fine Tuning HDL codebase4 , (iii) expedite time-to-market (TTM) in the com-

Repair (Mitigation)
HDL Code
RTL Modules Prompting Database petitive chip design process, and (iv) enable a more efficient and
for HDL

Suggestions
(+Instruction/Explain)
Generation
reliable system (by reducing human-induced faults) [40].
with & without
Vulnerabilities The current LLM-based methodologies in HW can be classified
into two primary categories: (1) Development of automated AI
Prompt agents aimed at streamlining EDA workflows (e.g., ASIC flow); (2)
Policy/Property Engineering Derivation of SW code generation for RTL implementation. Re-
Assertion HDL Database garding the former category, LLMs assist in various tasks such as
Generation script generation, architecture specification, and interpretation of

Repair (Mitigation)
For HDL Modules Prompting for
Vulnerability compilation reports, thereby minimizing the workload of the design

Suggestions
Description team. Within the latter category, solutions predominantly utilize
Vulnerabilities LLMs in two manners: (i) refinement of design prompts, which en-
Database Fine Tuning tails the creation (engineering) of more precise prompts to guide
Figure 1: The Usage of LLMs for HDL (RTL) Generation/Validation. LLMs towards RTL generation with increased effectiveness, and (ii)
RTL-based tuning, which involves directly tuning LLMs through
either deductive or inductive, to current neural-based models, no-
training on RTL code examples. A comparison of all existing LLM-
tably codebase-reliant generative models [31].
based approaches in these two categories is shown in Table 1.
With recent outrageous advancements in LLMs, massive research
has focused on applying LLMs for independent SW code generation, 3.1 LLM Agent for EDA Automation
leading to widely-used platforms like Codex and CodeGen [4]. The
foundation of these models lies in autonomously predicting the Several studies have explored the potential of LLM in automating
subsequent token by considering the preceding context, typically the ASIC design/implementation process [8, 14, 27, 29]. ChatEDA
comprising function signatures and docstrings that describe the and ChipNeMo are two examples of task planning and execution
intended functionality of the program, translating human-written agents that interpret natural language commands from the de-
instructions into precise code snippets or entire programs [4]. sign team. ChipNeMo [29] implements a series of domain-specific
While this code generation relies on natural language processing training strategies for chip design tasks. It involves the deploy-
(NLP), unlike natural language that is typically parsed as a sequen- ment of bespoke tokenizers, domain-adaptive continued pretrain-
tial array of words or tokens, code generation is scrutinized based ing, and supervised fine-tuning guided by domain-specific instruc-
on its syntactic and semantic structure, often depicted using tree tions. ChatEDA [27] aims to facilitate optimal interaction with the
structures, e.g., abstract syntax trees (AST) [39]. Also, programming EDA tools by comprehending instructions in natural language for
languages have a limited set of keywords, symbols, and rules, unlike generating and delivering executable programs.
the broad and nuanced vocabulary of natural languages. Using such techniques, LLM agents can offer automated ASIC
Given such differences, the primary concern for LLM-generated flow, from RTL generation to GDSII creation, by invoking neces-
code is (i) correctness (testing and verification process), and (ii) sary SW tools and utilizing required scripts/files. However, while
codebase data hungriness [39]. In terms of correctness, testing and promising, these techniques necessitate thorough analysis to truly
validation from the viewpoint of LLMs require well-defined met- enhance automation in EDA tools for the following reasons:
rics, where traditional metrics, e.g., BLEU that widely used in NLP (1) Expert-Oriented Training and Fine-Tuning: Constructing such
assessments [39], fail due to their focus on linguistic similarity. For frameworks heavily relies on expert efforts for training or fine-
example, CodeBLEU that evaluates the quality of code produced tuning them to accommodate specific ASIC flows. Given the vari-
by LLMs, or Pass@k that quantitatively measures the functional ety of technologies with their respective documentation, syntaxes,
accuracy of code generation models, are example of such new met- flows, and scripting methods, the pre-trained LLM may not offer a
rics [36]. Regarding codebase data for code generation, substantial universally applicable model for all environments.
codebase data2 is required for enhanced training and/or fine-tuning (2) Failure in Handling Unforeseen Incidents: Despite extensive fine-
to improve the efficacy of LLMs for code ganeration [4, 36]. tuning, the LLM-based agent may inaccurately extract information
from reports/specs or generate incorrect scripts/configs when con-
fronted with new incidents in the flows. Technology advancements,
3 LLMS FOR HW: DESIGN AND TESTING
EDA tools updates, etc., may worsen this issue, as the LLM agent
Similar to SW engineering and testing, leveraging LLMs can signif- may fail to provide the desired output under evolving conditions.
icantly optimize and enhance circuit design processes, particularly (3) Dependence on Technology: To clarify this, we raise a question!
within Electronic Design Automation (EDA) frameworks. LLMs can How similar is the EDA flow (i) from one design to another design,
be used at high level abstraction, e.g., RTLs, to (i) reduce manual (ii) from one technology to another technology, (iii) from one ven-
efforts for implementation3 , (ii) address the challenge of lacking dor to another vendor? Now, the question becomes how deep is
LLM fine-tuned based on these designs, technologies, and vendors?
While chatbots may offer basic assistance, the prospect of achieving
2 The data must be not only vast but also diverse, relevant, and of high integrity as the comprehensive automation seems to remain elusive.
superioir quality codebase data enhances model performance significantly [32].
3 It can potentially serve as an alternative to high level synthesis (HLS), thereby enabling 4 Lackof HDL codebase is always a substantial barrier for AI-driven HW solutions,
designers with limited HDL expertise to swiftly generate HW designs [40]. consequently enhancing the efficiency of the training phase [33].

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Evolutionary LLMs for Hardware Security: A Comparative Survey GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA

Table 1: A Top Comparison of LLM-based HW RTL Generation and EDA Tools.

Study Target LLM Engine Input Output Comment (—Shortcomings—)
Chang et al. [10] RTL Generation + Refinement GPT-3.5 Design Specification Prompts RTL Module - Static PPA analysis is post-LLM with no LLM-based improve-
+ Human Feedback for Corrections ment.
- Human feedback is needed for manual correction per design.
Thakur et al. [20] RTL Generation GPT-4, Llama2, GPT-3.5T, Design prompt + Com- Compiled and Tested RTL Design - Feedback addresses compilation/simulation errors but may
w/ guaranteed Compilation Claude 2 pile/Synthesis Report alter function priority, leading to unintended functions.
- No Feedback for PPA Efficiency Matter
He et al. [27] Automatic EDA Flow Script- Llama2-70B Natural Language Instructions + EDA Tool Commands & Reports + Scripts - It is either design- or technology-Dependent.
ing and Execution Calls RTL Design + Synthesized Design + Layout (GDSII) - Cannot be easily design/tool-agnostic.
Li et al. [14] Architecture Specifications GPT-4 Architecture specifications + RTL Hierarchical Reviewed Architecture Spec- - Specifications are limited to the existing technologies.
Generation + Review Design ifications - It is mostly processor-based instructions. Not for generic
HW.
Lu et al. [25] RTL Generation GPT-3.5, GPT-4, VeriGen, Star- Natural language instructions RTL Design - WIth no feedback, success rate is low for functional correct-
Coder ness.
- The reference designs are very limited and relatively small.
Liu et al. [18] RTL Generation RTLCoder Natural language instructions RTL Design - Diversity rate is low in the training dataset.
- The functional correctness of training dataset is not ensured,
leading to lower functional coverage in the generated outputs.
Thakur et al. [41] Completing Partial RTL De- MegatronLM-355M, CodeGen, Partial RTL Design + Custom prob- RTL Design - Lack of Organized Dataset.
sign code-davinci-002, and J1-Large- lem set with testbenches - RTLLM shows the performance does not surpass existing
7B commercial models.
- Completion necessarily does not provide correct functionali-
ties.
Cheng et al. [11] RTL Generation + Repair + Llama2-7B, Llama2-13B Natural language descriptions + Corrected Verilog code + Verilog code - For refinement, it is for syntactic errors (compilation issues).
EDA Script Generation Verilog files + EDA scripts from descriptions + EDA scripts
DeLo et al. [12] RTL Generation VeriGen-2B Natural language instruction + Compiled, Tested, and PPA Improved - Tested on Small Toy Circuits, e.g., adders and MAC units.
RTL modules description RTL Design - Stochastic behavior of MCTS. Less Improvement in More
Iterations.
Li et al. [42] RTL Synthesis (Mapping) Circuit Transformer Gate-Level Design (AIG) Design Model (Truth Table) + Synthe- - Low Accuracy for Larger Circuits.
sized AIG - Low Performance with no MCTS (Low Scalability).

3.2 LLM for RTL Generation and Refinement by the limited availability of trained models for test bench gen-
The main LLM-based RTL-oriented research focuses on the gen- eration and functional simulation [13]. The complexity of circuit
eration and refinement of RTL, primarily transitioning from spec- designs, which involve both functional and structural attributes,
ification to RTL design (+optimization). Initial efforts emphasize worsens the challenge, as even small changes to the structure (a
prompt engineering, crucial to successful RTL generation while code line) can have significant effects on functionality, underscoring
relying on the existing LLMs [8, 10, 25]. Other methods, e.g., Veri- the complexity of testbench generation and simulation of circuits.
gen and VerilogEval, adapt open-source LLMs like CodeGen [4], (3) Scalability Issues: Scalability is crucial for RTL-based LLMs in
followed by fine tuning on RTL, to produce more optimized HDL addressing complex circuit designs [25]. Efforts to enhance compu-
modules [13, 41]. Additionally, studies such as ChipGPT and Au- tational efficiency and model architecture sophistication are essen-
toChip explore use of feedback mechanisms to enhance HDL quality, tial to accommodate larger designs and meet evolving electronic
addressing aspects like compilation errors and design optimization device demands. Further research is necessary to overcome scala-
(PPA optimization) [10, 20]. While these methods often rely on bility challenges and maximize LLM potential in RTL generation.
static analysis, DeLorenzo et al. Introduce optimization techniques
like Monte Carlo tree search (MCTS) to fine-tune LLM tokens even 4 LLM FOR HW: SECURITY (VERIFICATION)
further for more tuned optimization at the backend of LLMs [12]. Given the paramount significance of security of HW designs in
More recent advancements have shifted the focus from fine tun- modern SoCs, and in light of the earlier discussion emphasizing
ing and prompt engineering in existing LLMs to the development the importance of verification over LLMs, several studies have
of dedicated circuit transformers, e.g., Li et al. Introduce "Circuit commenced employing LLM for SoC verification (moving towards
Transformer" with 88M parameters and integrated MCTS for opti- bug-free designs, either functional or security-oriented). Similar
mization, leading to a fully open-source independent LLMs for RTL to LLM-based RTL design, these approaches fall into two main
[42]. Similarly, RTLCoder proposes an automated data generation categories: (i) refinement of design prompts, where designers guide
flow utilizing a model with 7B parameters, producing a sizable la- LLMs toward generating secure code (i.e. prompt engineering), and
beled dataset for RTL generation [18]. These endeavors have led (ii) RTL-based tuning, which is about altering the LLM’s framework
to the emergence of large circuit models (LCM), enhancing the itself to generate output bug-free code. In advancing HW security,
expression of circuit data’s semantics and structures, thus creating researchers have leveraged LLMs using either pure natural language
more robust, efficient, and innovative design approaches. prompts (i.e. description of the code) or a blend of natural language
Despite its promise, more research is needed as follows: (i.e. comments designed by human experts) and code. The following
(1) Universality Issues: LLM-based RTL generation faces limitations describes these two categories in detail and how each category can
due to scarce codebase knowledge available for model fine-tuning enhance verification and security for HW designs.
and training per application [18]. As an example, developing se-
curity enclaves or fully-debugged Verilog modules is incredibly 4.1 Prompt Engineering
challenging as there are not many training datasets available for it.
Prompt engineering is the practice of designing inputs for LLMs,
(2) Verification (Functional) Issues: Existing studies highlight the
to obtain specific, desirable outputs. This technique optimizes the
complex nature of (functional) verification tasks, further magnified interaction with LLMs to improve its performance on various tasks,
leveraging strategies like few-shot [21], and chain-of-thought [9]

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GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA Mohammad Akyash and Hadi M Kamali

Prompt Prompt
prompting to guide the model’s responses effectively. A few recent Write a hardware
Based on the provided instruction, correct the security bug in this Verilog
studies in HW explore the applications of prompt engineering for module. compares bits of

enhancing vulnerability detection and repair, as well as design ver- BUG: Access Control Check Implemented After Asset is Accessed.
Response
Ensure that access is granted before data is accessed.
ification. For example, [3] employs a range of detailed instruction module key_compar
module user_grant_access(data_out, usr_id, data_in, clk, rst_n); input [7:0] k
prompts for various LLMs, aiming to evaluate the efficacy of each output reg [7:0] data_out; input [7:0] k
input wire [2:0] usr_id;
model in correcting HW vulnerabilities5 . Fig. 2 shows an exam- input wire [7:0] data_in;
output reg mat
output [7:0] d
input wire clk, rst_n; );
ple of how prompting GPT-4 with a bug description and repair reg grant_access;
wire [7:0] compar
instructions alongside the Verilog code enables GPT-4 to address always @(posedge clk or negedge rst_n) begin assign compare_re
if (!rst_n)
the vulnerability. Here are two important lessons to be learned: data_out = 0; always @(compare_
else begin if (compare_r
(1) The example shows that being super specific is crucial in en- grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0; 8'b00000000)
data_out = (grant_access) ? data_in : data_out; match = 1
gineering the prompt to ensure the generated code is devoid of end else
end match = 0
vulnerabilities. Thus, it is vital to have careful crafting by human endmodule end
experts to generate such prompts. This requirement for human Response assign diff = com
input could become a tedious process, posing challenges in scaling module user_grant_access(data_out, usr_id, data_in, clk, rst_n); endmodule
output reg [7:0] data_out;
and automating the approach for broader applications. input wire [2:0] usr_id;
input wire [7:0] data_in;
(2) The performance and efficacy of LLMs depends on the infras- input wire clk, rst_n;
reg grant_access;
tructure of LLM used. While commercial LLMs like GPT-4 tend to
always @(posedge clk or negedge rst_n) begin
outperform models trained on coding datasets, including Codegen if (!rst_n) begin
data_out <= 0;
and VeriGen, in terms of repair accuracy and efficacy, this advantage end else begin
grant_access = (usr_id == 3'h4) ? 1'b1 : 1'b0;
comes at the cost of increased number of parameters. if (grant_access) begin
data_out <= data_in;
The importance of precision in prompt generation is also shown end
end
in [15], relying on ChatGPT, revealing the fact that the success rate end

can be degraded significantly while the model is more limited6 . This

endmodule

Figure 2: An Examplary Case in GPT-4 for Security Debugging.

study also demonstrates models misguiding the designers while the
Verilog code of various CWE scenarios as part of instruction can promising results and achieved high coverage rates in simple sce-
lead to new form of vulnerabilities from prompts (may not fully narios. However, this approach focuses more on coverage-related
represent the capture of potential vulnerabilities in SoC designs). metrics, overlooking security-oriented vulnerabilities.
To enhance verification capability, some studies focus on the use Similar to these formal-based mechanisms, [37] proposes de-
of LLMs for verification assertion generation (e.g., SystemVerilog signing an evaluation framework that includes generating natural
Design Bug Detector
Assertions (SVAs)). For instance, [16] uses GPT-4 in an iterative language prompts that mimic code comments in assertion files, us- Design
mechanism to refine prompts for GPT-4, enabling it to generate ing these prompts to generate SVAs with LLMs, and then assessing
more accurate and complete SVA properties from RTL code. This the correctness of these assertions against a benchmark suite of
approach coupled with AutoSVA2, which automatically generates real-world HW designs and corresponding golden reference asser-
formal verification testbenches, enables LLM-guided formal verifi- tions. The results demonstrate that LLMs, with varying levels of
Bug
cation towards more automation. However, the major obstacle to detail in the prompts, can generate valid HW security assertions.
this automation is the reliance of this approach on iterative refine- More recent use of LLMs Designer
for RTL debugging aimed to enhance
ment by an expert, which requires a deep understanding of both automation in the domain. For instance, RTLFixer [26] automati-
HW verification and prompt engineering. cally rectifies syntax errors in Verilog code by leveraging Retrieval-
Similarly, AssertLLM [23] uses a customized GPT-4 Turbo to BugAugmented
free Generation
LLM (RAG) and the ReAct prompting strategy. Bug free
generate SVAs (functional verification assertions) from natural lan- design
RTLFixer employs a retrieval database filled with expert knowl- design
guage design specifications (translating design documents). Al- edge of syntax errors. ReAct also introduces an iterative approach
though results show high success rate, this model is also heavily involving reasoning, action, and observation, mimicking experts’
dependent to the quality and completeness of the design documents. debugging techniques. This combination builds a more effective
This is while richness of documentation is always a critical issue in system for automating the debugging. However, it still heavily
HW design, thus AssertLLM might struggle to generate assertions relies on the comprehensiveness and currentness of the external
that fully capture the intended design behavior. knowledge database, which is collected by human experts.
LLM4DV [28] uses LLMs with prompt templates to automate Some LLM-based studies focus on the use of such models at the
the generation of test stimuli for verification. LLM4DV integrates SoC level. DIVAS [19] uses LLMs to analyze SoC specifications and
LLMs with a systematic method that includes a stimulus genera- crafts precise queries that encapsulate potential security vulnera-
tion agent, prompt templates, and four LLM-based improvements, bilities related to the SoC. These queries are submitted to LLMs,
e.g., summarizing prompts, resetting, etc. Evaluated using three e.g., ChatGPT and Google’s BARD, and the LLMs map these queries
custom-designed large-scale DUTs, this framework demonstrated to relevant CWE vulnerabilities that could compromise the SoC.
Once CWEs have been identified, DIVAS utilizes LLMs to construct
SVAs for each. These SVAs are designed to act as security verifica-
5 These prompts must provide a thorough description of the bug, strategies for debug- tion mechanisms, ensuring the SoC’s design complies with security
ging, and illustrative examples that contrast insecure code with its secure counterpart. standards and is safeguarded against identified vulnerabilities.
6 The number of parameters was restricted to a range of millions instead of billions.

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Evolutionary LLMs for Hardware Security: A Comparative Survey GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA

Table 2: A Top Comparison of LLM-based HW Security Validation Solutions

Study Target LLM Engine # of Bugs Success Rate Source of Bench- Expert Knowledge Needed? Reference (for Eval) Comment
marks
Nair et al. Prompt gen- ChatGPT 10 100%∗1 CWE (Descrip- For the Whole Process Manual expert interven- - Cannot be automated.
[15] eration for tions) tion per debugging - Limited evaluation on CWEs
Debugging RTL
Kande et al. Detection (Gener- OpenAI Codex 10 ∼25% Hack@DAC21, For manually building detailed secu- Golden Assertion - High success rate only when bug and security
[37] ate Assertion) (code-davinci- OpenTitan rity constraints policy is known. Otherwise, it is below 10%.
002) - Only for single endmodule, No Hierarchical and
Recursive SVA.
Ahmad et Repair OpenAI Codex 15 ∼31% CWE (Bench- - For training (dataset generation for Repaired Code (Prompt - Only applicable on pre-observed cases with high
al. [3] (pre-detected (code-davinci-001, mark), assisting repairs) Reference) similarity (to be detected by CWEAT)
bugs) code-davinci-002, OpenTitan, - For CWEAT static analyze verifica-
code-cushman- Hack@DAC21 tion
001), CodeGen
Saha et al. Detection (Gener- GPT 3.5, N/R∗2 N/R∗2 CWE, Trust-Hub For prompt engineering and evalua- Manual expert interven- - Limited evaluation on CWEs and smart toy cir-
[5] ate Assertion), se- GPT 4 tion tion per debugging cuits.
curity vulnerabil-
ity insertion
Fu et al. Detection and/or StableLM, Falcon, 1 (different ∼35% Open-Source SoCs For fine-tuning (Open-source code Repaired Code (Pre- and - Detailed enhancement for training is needed. Per
[22] Repair LLama2 models) and Microproces- classifications) Post-correction of Git design, a new training might be required.
sors (CVA6, Opentitan, . . . )) - Raw dataset is limited and not design-agnostic).
Meng et al. Detection (Gener- HS-BERT 8 326 Bugs from RISC-V, Open- For classifying security rules in doc- Manual expert labling for - Limited by the quality of the input HW documen-
[24] ate Assertion) 1723 sentences RISC, MIPS, uments security property valida- tation.
OpenSPARC, tion - Limited to the design/verification team knowledge.
OpenTitan (docu-
mentation)
Fang et al. Detection (Gener- GPT4 Turbo N/A 89% Open-source For extracting verification-required Golden RTL Implementa- - Limited by the quality of the input HW documen-
[23] ate Assertion) CPUs, SoCs, information from documents tion tation.
Xbars, arithmetic. - Mostly syntactic and basic functional verification.
Paria et al. Detection (Gener- ChatGPT, N/A N/A CEP SoC (MIT-LL) For assumptions (CWE-based secu- N/R∗2 - Expert review for Spec Generation is needed per
[19] ate Assertion) BART rity rules) design.
Vera et al. Detection (Gener- GPT-4 N/R∗2 N/R∗2 RISC-V CVA6 For building rules related to asser- Previously developed for- - The success rate heavily depends on expert’s input
[16] ate Assertion) tions mal tools (AutoSVA) for prompt engineering.
Zhang et al. Test Stimuli Gen- GPT-3.5-turbo N/A small: ∼98%, Self-designed RTL For prompts generation Coverage Monitoring - Not for security purposes. Coverage-based testing.
[28] eration large: ∼65% Designs
Tsai et al. Syntax Errors Re- GPT-3.5, 212 98.5% VerilogEval bench- For retrieval database (debugging ref- VerilogEval, - Not for security purposes. Only for Syntax errors.
[26] pair GPT-4 marks, erence) RTLLM
RTLLM bench-
marks
∗1 : It is 100% as all the debugging is done manually. Bug is known, the debugging instruction (flow) is known, and GPT is used for generation. N/R∗2 : Not Reported.

Similarly, [5] explores how GPTs are utilized in SoC level for extracting commits, issues, and pull requests (PRs) related to HW
security vulnerability insertion, detection, assessment, and mitiga- designs. This approach provides a rich source of domain-specific
tion. This study, focusing on smaller models, e.g., ChatGPT-3.5, and data for training models, specifically tailored to identifying and
relying on a sub-set of CWEs, evaluates the modification possibil- fixing bugs in HW designs. Although innovative and promising, the
ity over RTL using one- and few-shot learning. By comprehensive quality of this data is dependent on the filtering process accuracy.
exploration, the study suggests specific prompt guidelines for ef- The effectiveness of LLMs in debugging HW designs is thus directly
fectively using LLMs in SoC security-related tasks. tied to how precisely the data is curated and processed.
LLMs possess a dual-use nature; While advancing HW security The NSPG framework [24] is another example of LLM solution
initiatives, LLM can also present new threats simultaneously. [7] for HW verification that offers a novel methodology for automat-
delves into the potential of general-purpose models like ChatGPT in ing the generation of HW security properties utilizing fine-tuned
the offensive HW security domain This study involves employing LLMs. This approach is anchored by the development of a special-
prompt engineering techniques to guide LLMs in filtering com- ized language model for HW security, HS-BERT, which is trained
plex HW design databases, correlating system-level concepts with on domain-specific data. Through deep evaluation on previously
specific HW modules, identifying security-critical design modules, unseen design documents from OpenTitan, NSPG has proven its
and modifying them to introduce HW Trojans. This study initiates capability by extracting and validating security properties, showing
the possibility of using LLMs for building more stealthy and unde- security vulnerabilities within the OpenTitan design. However, a
tectable HW Trojans, reshaping the characteristics of HW Trojan notable limitation of not only NSPG, but also all HW-oriented fine-
implementation, detection, and mitigation. tuned model for now lies in its dependency on the quality and scope
of the HW documentation provided as input (which is almost super
4.2 Fine-Tuning limited). As in the realm of HW/SoC design, this documentation
As mentioned previously, some of these LLM-based HW verifi- often remains incomplete, inconsistent, or lack necessary detail, the
cation solutions rely on fine-tuning, which involves adjusting a precision and efficacy of the solution could be adversely affected.
pre-trained language model by training it on Verilog/SVA data.
However, LLMs require extensive datasets for effective training, 5 TAKEAWAYS AND FUTURE DIRECTIONS
posing a significant challenge in specialized domains, particularly in In all facets of using LLMs for HW security, it becomes apparent that
HW security due to the scarcity of targeted data. LLM4SecHW [22] a significant hurdle, whether in HW design or in testing/verification,
is one example, which leverages a dataset compiled from defects whether stemming from prompt engineering or fine-tuning, lies in
and remediation steps in open-source HW designs, using version the procurement and effective utilization of quality data [17]. Also,
control data from GitHub. This dataset was created by selecting as depicted in Table 2, creating specialized LLMs (e.g., LCMs) or
significant HW projects such as CVA6, CVA5, OpenTitan, etc., and employing pre-existing ones necessitates a deep expert knowledge

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GLSVLSI ’24, June 12–14, 2024, Clearwater, FL, USA Mohammad Akyash and Hadi M Kamali

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