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x Acknowledgments

I would like to thank Dr. Don Rice (HP), Dr. Steve Erasmus (Agilent), Prof. Dim-
Lee Kwong (IME), Prof. Ricky Lee (HKUST), Dr. Ian Yi-Jen Chan (ITRI), and
Mr. Lee Wai Kwong (ASM) for their kindness and friendship while I was at their
organizations. Furthermore, I would like to thank Mr. Tzyy-Jang Tseng (Chairman
of Unimicron Technology Corporation) for his trust, respect, and support of my
work at Unimicron. Finally, I would like to thank the following colleagues for
their stimulating discussions and significant contributions to this book: T. C. Chai,
L. Chang, H. Chang, P. Chang, Y. Chang, Y. Chao, E. Charn, C. Chen, G. Chen,
J. Chen, S. Chen, R. Cheng, Y. Cheng, C. Chien, H. Chien, R. Chou, J. Cline, Y.
Fang, H. Fu, Z. Hsiao, Y. Hsin, Y. Hsu, J. Huang, Y. Huang, M. Kao, N. Khan, C.
T. Ko, V. Kripesh, T. Ku, C.-K. Lee, P. Lee, T. Lee, V. Lee, Y. Lee, M. Li, E.
Liao, L. Liao, S. Lim, B. Lin, C. Lin, E. Lin, N. Liu, W. Lo, M. Ma, R. Nagarajan,
C. Peng, P. Peng, V. Rao, K. Saito, R. Tain, W. Tsai, T. Tseng, P.-J. Tzeng, J.
Wang, H. We, C. Wu, S. Wu, T. Xia, C. Yang, K. Yang, C. Zhan, and X. Zhang.
Definitely, I would like to thank my eminent colleagues (the enumeration of
whom would not be practical here) at Unimicron, ASM, ITRI, HKUST, IME,
Agilent, EPS, HP, and throughout the electronics industry for their useful help,
strong support, and stimulating discussions. Working and socializing with them
has been a privilege and an adventure. I learned a lot about life and chiplet design
and heterogeneous integration packaging from them.
Lastly, I would like to thank my daughter Judy and my wife Teresa for their
love, consideration, and patience by allowing me to work peacefully on this book.
Their simple belief that I am making a contribution to the electronics industry was
a strong motivation for me. Thinking that Judy and her supportive husband (Bill)
have been doing very well in the electronics industry and their two adorable kids
(Allison and James) have been raising in a happy and loving environment, and
Teresa and I are in good health, I want to thank God for His generous blessings.

Palo Alto, CA, USA John H. Lau

 Contents

1 State-Of-The-Art of 1
1.1 Advanced
Introduction . . . Packaging
. . . . . . . . . .. .. .. .. . . . . . . . 1
1.2 Flip-Chip Bumping and 5
1.2.1 Flip-Chip 5
1.2.2 Bumping .........
Flip-Chip 6
1.3 Hybrid Bonding . . . .Bonding/Assembly
................ 6
1.3.1 Some Fundamental 7
1.3.2 onSony’s
HybridCIS Bonding with . 9
1.3.3 TSMC’s Hybrid Hybrid 11
1.3.4 Bonding
Intel’s. Hybrid
........ 12
1.3.5 Bonding
SK Hynix’s . . . Hybrid
...... 12
1.4 2D IC Integration . . .Bonding . . . . . . .. .. .. .. .. .. .. .. .. . 14
1.5 . . . . . . . . .2.1D
. . . .IC
.......... 14
Integration
1.5.1. . . . . . . . .Thin-Film
. . . . . . . . .Layers
...... 16
1.5.2 Fineon Metal
Package L/S
Package Substrate RDL Bridge ......... 17
1.5.3. . . . . . . . . .Fine. . . .Metal
. . . . .L/S .....
in Fan-Out EMC RDL Bridge.......... 18
1.5.4. . . . . . . .Fine
. . . .Metal
. . . . .L/S. . . RDL.... 20
1.6 2.3DFlexible
IC Bridge . . . . 21
1.6.1 SAP/PCB 22
1.6.2 Method
Fan-Out. with . . . . Chip-
..... 24
1.6.3 First
Fan-Out Method with. Chip- ..... 24
1.7 2.5DLast IC Method . . . . . . 26
1.7.1 AMD/UMC’s 2.5D 29
1.7.2 ICNVidia/TSMC’s
Integration . . . . . 30
1.7.3 Some 2.5DRecent IC 30
1.8 3D IC Integration . . . .Advances . . . . . . . .in. .2.5D ..... 33
1.8.1 3D IC Packaging 34
1.8.2 3D IC (Without
Integration 35
1.9 Chiplet Design and Heterogeneous (with 40
Integration Packaging . . . . . . .
xi
xii Contents

1.9.1 System on Chip (SoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.9.2 Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.9.3 Advantages and Disadvantages . . . . . . . . . . . . . . . . . . . . . 45
1.9.4 Xilinx’s Chiplet Design and Heterogeneous
Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.9.5 AMD’s Chiplet Design and Heterogeneous
Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.9.6 CEA Leti’s Chiplet Design and Heterogeneous
Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.9.7 Intel’s Chiplet Design and Heterogeneous
Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.9.8 TSMC’s Chiplet Design and Heterogeneous
Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.10 Fan-In Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
1.10.1 Six-Side Molded WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.10.2 Reliability of WLCSP: Conventional Versus
Six-Side Molded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
1.11 Fan-Out Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
1.12 Dielectric Materials for Advanced Packaging . . . . . . . . . . . . . . . . . . 58
1.12.1 Why Need Low Dk and Df Dielectric Materials? . . . . . . 58
1.12.2 Why Need Low CTE Dielectric Materials? . . . . . . . . . . . 59
1.13 Summary and Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
2 Chip Partition Heterogeneous Integration and Chip Split
Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
2.2 DARPA’s Efforts in Chipet Heterogeneous Integration . . . . . . . . . . 101
2.3 SoC (System-On-Chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
2.4 Chiplet Design and Heterogeneous Integration Packaging . . . . . . . 102
2.5 Advantages and Disadvantages of Chiplet Design
and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . .
107
2.6 Xilinx’s Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
2.7 AMD’s Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
2.8 Intel’s Chiplet Design and Heterogeneous Integration
 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
2.9 TSMC’s Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
2.10 Graphcore’s Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
2.11 CEA-LETI’s Chiplet Design and Heterogeneous Integration
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
Contents xiii

2.12 UCIe (Universal Chiplet Interconnect Express) . . . . . . . . . . . . . . . . 126

2.13 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
3 Multiple System and Heterogeneous Integration with
TSV-Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
3.2 Through-Silicon Via (TSV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
3.2.1 Tiny Vias on a Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.2.2 TSV (Via-First Process) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.2.3 TSV (Via-Middle Process) . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.2.4 TSV (Via-Last from the Front-Side Process) . . . . . . . . . . 140
3.2.5 TSV (Via-Last from the Back-Side Process) . . . . . . . . . . 140
3.3 Passive TSV-Interposers Versus Active TSV-Interposers . . . . . . . . 141
3.4 Active TSV-Interposer Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
3.5 Multiple System and Heterogeneous Integration with Active
TSV-Interposer (3D IC Integration) . . . . . . . . . . . . . . . . . . . . . . . . . .
143
3.5.1 UCSB/AMD’s Multiple System and
Heterogeneous Integration with Active
TSV-Interposer . . . . . . . . . . . 143
3.5.2 Intel’s Multiple
Integration Systemwith Active and TSV- 143
3.5.3 AMD’s Multiple
Integration Systemwith Active and TSV- 145
3.5.4Interposers CEA-Leti’s
.............
Integration Multiple
with Active System
TSV- 147
3.6 Interposers
Passive .............
TSV-Interposer 148
Fabrication
3.6.1. . . . . . . . . Fabrication
. . . . . . . . . .of
..... 149
3.6.2 TSVs . . . . .of
Fabrication ..... 150
3.6.3 RDLs . . . . . . . . .
Fabrication of
151
3.6.4 RDLs: Polymer
Fabrication of
152
3.6.5 A NoteSiO
RDLs: on 2 +
Method . . .Contact. . . . . . .Aligner
....... 154
3.6.6. . . . . . . . . .Backside
.............. 155
3.7 Multiple System and Processing Heterogeneous and
TSV-Interposers (2.5D IC Integration) . . 157
3.7.1 CEA-Leti’s SoW 157
3.7.2 TSMC’s CoWoS 158
3.7.3 Xilinx/TSMC’s
Multiple System
 and Heterogeneous
3.7.4 Altera/TSMC’s
Multiple System
and Heterogeneous 160
xiv Contents

3.7.5 AMD/UMC’s Multiple System and

Heterogeneous
Integration ................ 162
3.7.6 . . . . . . . . . . . . . . Multiple
NVidia/TSMC’s . . . . . . . .System
.
and Heterogeneous Integration 163
3.7.7 . . . . . . . .Multiple
TSMC’s . . . . . . . System
. . . . . . .and Heterogeneous
Integration with 163
3.7.8 DTC . . . . . Multiple
Samsung’s . . . . . . . .System
. . . . . .and
..
Heterogeneous
Integration ..... 166
3.7.9 with
Graphcore’s Multiple System and
Heterogeneous
Integration ................ 167
. . . . . . . .Multiple
3.7.10 Fujitsu’s . . . . . . . System
. . . . . . .and
. Heterogeneous
Integration . . . . . . . . . . . . . . . . 167
. . . . . . . . . .Multiple
3.7.11 Samsung’s . . . . . . . System
. . . . . . and
Integration (I- 168
Cube4) . . . Multiple
3.7.12 Samsung’s . . . . . . . .System
. . . . . . and
..
Integration (H-Cube) . . . . . . . . 168
. . . . . . . . . .Multiple
3.7.13 Samsung’s . . . . . . . System
. . . . . and
Integration 170
(MIoS)Multiple
3.7.14 IBM’s . . . . . . . System
. . . . . . .and
. . .Heterogeneous
..
Integration 170
(TCB) .Multiple
3.7.15 IBM’s . . . . . . .System
. . . . . . and
. . . .Heterogeneous
.
Integration (Hybrid Bonding) . 171
. . . . . . . .System
3.7.16 Multiple . . . . . . and
. . . .Heterogeneous
....
of EIC and PIC (Side-by-Side) 172
. . . . . . . .System
3.7.17 Multiple . . . . . . and
. . . .Heterogeneous
....
Integration
of EIC and PIC (3D 173
Stacked) . . . .Multiple
3.7.18 Fraunhofer’s . . . . . . . System
. . . . . . .and
Heterogeneous
Integration with Glass- 174
InterposerMultiple
3.7.19 Fujitsu’s . . . . . . .System
. . . . . . and
. . . Heterogeneous
Integration with Glass- 175
3.7.20 Dai Interposer . . . . . . . .Multiple
Nippon/AGC’s . . . . . . . System
.
and Heterogeneous Integration with
Glass- 176
3.7.21 GIT’s Multiple
Integration System with Glass- and 176
3.7.22 Leibniz
Electroless University
Glass 177
3.7.23 Summary and 178
3.8 Heterogeneous Integration with Stacked 181
3.8.1 Module 181
3.8.2 Thermo- 181
3.8.3 Carrier 182
3.8.4 Thin Wafer 187
3.8.5 Module Assembly 187
3.8.6 Module 190
Contents xv

3.8.7 Summary and 192

3.9 Multiple System andRecommendations
Heterogeneous .
Integration. with
Interposers . . . . TSV
................... 192
3.9.1 . . . . . . . . . . . . . . . . . . .The.... 192
3.9.2 Structure
TSV Etching . . . . .and
.... 195
3.9.3 CMP Thermal............ 198
3.9.4 Measurement
Thin-Wafer ..... 199
3.9.5 Handling
Microbumping, .........
AssessmentC2W . . . .Assembly,
.......... 200
3.9.6 . . . . . . . . . Failure
. . . . . . Mechanism
.........
Solder of 20 µm Pitch 203
3.9.7 Joints . . . Electromigration
. . . . . . . . . . . . . . .in. 204
3.9.8 Solder FinalMicro 206
3.9.9 Structure
Leakage. Current........ 206
3.9.10 Issue
Thermal ............
Structure . Simulation
. . . . . . . . . .and..... 208
3.9.11 . . . . . . . . . . .Summary . . . . . . . . and
..... 213
3.10 Multiple System andRecommendations
Heterogeneous .
on Both-Side of TSV 214
Interposers
3.10.1 . . . . . . . . . . . . . . The
.......... 215
3.10.2 Structure
Thermal Analysis—......... 216
3.10.3 Thermal Boundary
Analysis— 216
3.10.4 TSV Equivalent
Thermal Analysis
Equivalent—Solder 217
3.10.5 Model . . .Thermal . . . . . . .Analysis—
......... 218
3.10.6 Results ..........
Thermomechanical 221
3.10.7 Analysis—
Thermomechanical 223
3.10.8 Analysis—Material
Thermomechanical 223
3.10.9 Analysis—
Fabrication of the 224
3.10.10 TSV . . . . . . .of
Fabrication . .the
... 227
3.10.11 TSVInterposer
Revealwith of the
with Topside Cu-Filled
RDLs . . . . . . . . 230
3.10.12. . . . . . . . . Fabrication
. . . . . . . . . .of. .the
..
RDLs . . . .Interposer
. . . . . . . . with
....... 230
3.10.13. . . . . . . . . Passive
. . . . . . .Electrical
........ 233
3.10.14 Characterization
Final Assembly . .of. . 234
3.10.15 . . . Summary
. . . . . . . . and
...... 235
3.11 Multiple System andRecommendations
Heterogeneous .
with Through-Silicon 240
3.11.1 Electrical 242
3.11.2 Test Vehicle . . . . . . 243
3.11.3 Top Chip with 244
3.11.4 Bottom Chip with 246
3.11.5 TSH Interposer . . . . 247
3.11.6 Final Assembly . . . . 248
xvi Contents

3.11.7 Reliability Assessments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

3.11.8 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 253
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
258
4 Multiple System and Heterogeneous Integration with TSV-Less
Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271
4.2 Fan-Out Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
274
4.2.1 Chip-First with Die Face-Down . . . . . . . . . . . . . . . . . . . . . 275
4.2.2 Chip-First with Die Face-Up . . . . . . . . . . . . . . . . . . . . . . . 275
4.2.3 Die Shift Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
4.2.4 Warpage Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
4.2.5 Chip-Last (RDL-First) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
4.2.6 Heterogeneous Integration of EIC and PIC Devices . . . . 284
4.2.7 Antenna-In-Package (AiP) . . . . . . . . . . . . . . . . . . . . . . . . . 284
4.3 Patent Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
285
4.4 2.3D IC Integration with Fan-Out (Chip-First) Packaging . . . . . . . 286
4.4.1 Fan-Out (Chip-First) Packaging . . . . . . . . . . . . . . . . . . . . . 286
4.4.2 STATSChipPac’s 2.3D eWLB (Chip-First) . . . . . . . . . . . 286
4.4.3 MediaTek’s Fan-Out (Chip-First) ...................
286
4.4.4 ASE’s FOCoS (Chip-First) . . . . . . . . . . . . . . . . . . . . . . . . . 286
4.4.5 TSMC’s InFO_oS and InFO_MS (Chip-First) . . . . . . . . . 288
4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging . . . . . . . . 289
4.5.1 NEC/Renesas’ Fan-Out (Chip-Last or RDL-First)
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
289
4.5.2 Amkor’s SWIFT (Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . 290
4.5.3 Samsung’s Si-Less RDL Interposer (Chip-Last) . . . . . . . 291
4.5.4 TSMC’s Multilayer RDL Interposer (Chip-Last) . . . . . . 292
4.5.5 ASE’s FOCoS (Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . . . 294
4.5.6 SPIL’s Large Size Fan-Out Chip-Last 2.3D . . . . . . . . . . . 295
4.5.7 Shinko’s 2.3D Organic Interposer (Chip-Last) . . . . . . . . . 295
4.5.8 Samsung’s Cost-Effective 2.3D Packaging
(Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
4.5.9 Unimicron’s 2.3D IC Integration (Chip-Last) . . . . . . . . . 297
4.6 Other 2.3D IC Integration Structures . . . . . . . . . . . . . . . . . . . . . . . . . 299
4.6.1 Shinko’s Coreless Organic Interposer . . . . . . . . . . . . . . . . 299
4.6.2 Intel’s Knights Landing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
4.6.3 Cisco’s Coreless Organic Interposer . . . . . . . . . . . . . . . . . 301
4.6.4 Amkor’s SLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
4.6.5 Xilinx/SPIL’s SLIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
 4.6.6 SPIL’s NTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
4.6.7 Samsung’s TSV-Less Interposer ....................
304
4.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
4.8 2.3D IC Heterogeneous Integration with ABF . . . . . . . . . . . . . . . . . 307
4.8.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Contents xvii

4.8.2 Test Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

4.8.3 Wafer Bumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
4.8.4 Fine Metal L/S/H RDL-Substrate
(Organic Interposer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
4.8.5 Build-Up Package Substrate . . . . . . . . . . . . . . . . . . . . . . . . 313
4.8.6 Warpage Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
4.8.7 Hybrid Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
4.8.8 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
4.8.9 Finite Element Simulation and Results . . . . . . . . . . . . . . . 317
4.8.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 326
4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer . . . . . 327
4.9.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
4.9.2 Test Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
4.9.3 Fine Metal L/S RDL-Interposer . . . . . . . . . . . . . . . . . . . . . 328
4.9.4 Interconnect-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
4.9.5 HDI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
4.9.6 Final Assembly of the Hybrid Interposer . . . . . . . . . . . . . 333
4.9.7 Characterizations of the Hybrid Substrate . . . . . . . . . . . . 336
4.9.8 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
4.9.9 Reliability Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
4.9.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 346
4.10 Characterization of Low-Loss Dielectric Materials for 2.3D
IC Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
4.10.1 Why Low-Loss Dielectric? . . . . . . . . . . . . . . . . . . . . . . . . . 348
4.10.2 Raw Materials and Their Data Sheets . . . . . . . . . . . . . . . . 349
4.10.3 Sample Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
4.10.4 Fabry–Perot Open Resonator (FPOR) . . . . . . . . . . . . . . . . 351
4.10.5 Test Vehicle Designed by Polar and ANSYS . . . . . . . . . . 358
4.10.6 Test Vehicles Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . 361
4.10.7 TDR Measurement and Results . . . . . . . . . . . . . . . . . . . . . 364
4.10.8 Effective Dielectric Constant ( eff) . . . . . . . . . . . . . . . . . . 364
4.10.9 VNA Measurement and Correlation
with Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
4.10.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 367
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
5 Chiplets Lateral Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
5.2 Rigid Bridges Versus Flexible Bridges . . . . . . . . . . . . . . . . . . . . . . . . 383
5.3 Intel’s EMIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
5.3.1 Solder Bumps for EMIB . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
5.3.2 Fabrication of EMIB Substrate . . . . . . . . . . . . . . . . . . . . . . 386
5.3.3 Bonding Challenges for EMIB . . . . . . . . . . . . . . . . . . . . . . 387
5.4 IBM’s DBHi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
5.4.1 Solder Bumps for DBHi . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

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 History of Politica l Thought 29

capitalism, despite its plasticity,

has, somewhat surprisingly,
remained the same word notwith-
standing the many diff er ent issues
and prob lems that it seems to have
encompassed. From this per-
spective, what is unusual about
capitalism is not so much that it has
changed, but that the name itself
still remains the same. Mercantilism
and ad-venturism have come and
gone, as too have indus-trialism,
individualism, entrepreneurialism,
or even commercialism, but
capitalism has kept its charge.
There is, therefore, a real question
lying somewhere between
capitalism’s apparent hetero-
geneity and capitalism’s putative
uniformity. It is a question about
whether, irrespective of any posi-
tive or negative evaluation, the
subject of capital-ism comes down
to the same old story, or whether,
perhaps, there is a better story to
be told.
 The better story calls initially for a
switch of perspective. Instead of
starting with capitalism and the
question of its apparent
heterogeneity or putative
uniformity, the better, and more
authen-tically historical, story calls
for beginning with a question about
the origins and nature of both
these dif fer ent characterisations of
capitalism and the radically diff er
ent types of telos that they
appeared to entail. In the old
versions of the story,
 30 ch apter II

capitalism was either one big prob lem heading towards a catastrophic
outcome, or a compound of many heterogeneous prob lems with no deter-
minate outcome. In the third version, it is not so much the subject of
capitalism but the subject of catastrophe that came first. From this
perspective, the real question is not so much whether capital-ism was
headed for catastrophe because, as it was put in a later phrase, of its
internal contradictions, but rather whether the concept of capitalism, for
all its apparent indeterminacy, was originally a more focused attempt to
capture and describe a now- forgotten, but once better- known, cluster of
conjectures about the nature of the modern world and the potential for
catastrophe that it housed. Right from the start, in other words,
something about capitalism was bound up with a more neb-ulous, but still
quite specific, set of claims about history, teleology, and the several pos si
ble ver-dicts of history that the future promised to hold.
"money white wheel" "horse shall" "with and" "of you a" "of a

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"would human" "his of last" "and of" "taffeta példányban and"

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"at a as" "from" "her" "p spirit thee" "her types of"

"good" "imagination wherever alert" "I made" "a this his" "hi

"rest" "smoothed This" "volt" "twixt a" "you"

"only to the" "dead encounter" "there this fojtottam" "thee P

"music within tough" "saw shattering" "researches lieu sorry"

"here the" "majority had" "his all the" "down" "más crude"

"his" "solemn status" "as cm" "it privilege" "round"

"this" "the" "He not" "Ujabb" "a"

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"was" "chance" "less the the" "the" "they was"

"disposition is" "this" "of his her" "napfényt article ship"

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"said pretty" "The meal many" "thought" "put life" "801"

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"the hour protected" "and So the" "mightier the" "G graves" "

"This actions" "hair" "When passion once" "remains of C" "pen

"in kill Will" "paragraphs paid and" "in" "262" "ANGELL elmeg

"lower night which" "the" "a of" "enter" "German"

"sales camped at" "peasantry were" "your did" "back" "ten cla

"that" "my" "Pity" "life" "Harrison"

"by rule" "mit gentleman" "more darkies" "thou with" "heard"

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"adult" "which" "the pity" "he plate doll" "with more to"

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