Module 5 Computer Organization

BASIC PROCESSING UNIT

Some Fundamental Concepts

 To execute a program, the processor fetches one instruction at a time and performs the
operations specified.
 Instructions are fetched from successive memory locations until a branch or jump
instruction is encountered.
 The processor keeps track of the address of the memory location containing the next
instruction to b fetched using the PC.
 After fetching an instruction, the contents of PC are automatically incremented to point to
the next instruction in sequence.
 A branch instruction may load a different value into PC.
 Suppose each instruction comprises 4 bytes and that it is stored in one memory word.

Executing an Instruction

o Fetch the contents of memory location pointed to by PC. The contents of this
location are interpreted as an instruction to be executed. Hence they are loaded
into the IR. Symbolically this can be written as
IR [[PC]]
o Assuming that the memory is byte addressable, increment the contents of the PC
by 4
PC [PC] + 4
o Carry out the actions specified by the instruction in IR.
 In cases where an instruction occupies more than one word, steps 1 and 2 must be
repeated as many times to fetch the complete instruction. These two steps are referred to
as fetch phase. step 3 is execution phase.
Processor Organization:
 The figure below shows single bus organization of the data path inside a processor.
 The data and address lines of external memory bus are connected to processor via MDR
and MAR respectively.
 MDR has two inputs and two outputs. It can receive inputs as well as send outputs on
memory bus or internal processor bus.
 The input of MAR is internal bus and output is external bus.
 The control lines of the memory bus are connected to the instruction decoder and control
logic block. This unit is responsible for issuing signals that control operations of all units.
 The registers R0 to R(n-1) are general purpose registers. Their numbers vary from one
processor to another processor.
 There are some special purpose registers like index register and stack pointer.

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 The registers Y, Z and Temp in the figure are used by processor for temporary storage
during execution of some instruction. They are never used for storing data generated by
one instruction for later use by another instruction.
 The Multiplexer selects either the output of register Y or the constant value 4 to provide
as input to the ALU. Constant 4 is used to increment the contents of program counter.
 The instruction decoder and control logic unit is responsible for implementing the actions
specified by the instructions loaded in the IR register.
 The following operations are normally performed by an instruction

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Register Transfers

 Instruction execution involves a sequence of steps in which data are transferred from one
register to another.
 For each register two control signals are used to place the contents of that register on the
bus or to load the data on the bus into the register. This is symbolically represented in the
fig. 7.2
 The registers have two control signals Riin and Riout. When Riin is set to 1, the data in the
bus are loaded into Ri. If Riout is set to 1, the data in the register is placed on the bus.
 Example – We wish to transfer data between registers R1 and R4 – Setting R1out to 1
places the contents of the register on to the processor bus. Setting R4in to 1 loads the data
from processor bus onto the register R4.
o All register transfers are defined by the processor clock.
o The control signals are asserted at the start of the clock signal.
o In this example R1out and R4in are set to 1.
o Registers consists of edge triggered flip flops.
o In the next active edge of the clock, the flip flop that constitutes R4 will load the
data present at their inputs. At the same time R1out and R4in will return to 0.
 Some times when edge triggered flip flops are not used, two or more clock signals may
be needed to guarantee proper transfer of data. This is known as multiphase clocking.

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Implementation of 1 bit register:

The implementation of one bit register Ri is shown in figure 7.3

o A two input multiplexer is used to select the data applied to the input of edge
triggered D flipflop.
o When Rin is 1, mux selects data on the bus. This data will be loaded into the flip
flop in the rising edge of the clock.
o When Rin is 0, mux feeds back the value currently stored in the flipflop
o The Q output of flip flop is connected to the bus via a tristate gate.
o When Riout is 0, gate output is in high impedance state (electrically disconnected).
o When Riout is 1, gate drives the bus to 0 or 1 depending on the value of Q.

Performing an Arithmetic or Logic Operation

ALU needs two operands to perform arithmetic and logic operation. Normally one of the
operand is the output of the mux and the other operand is directly from the bus. The result is
stored in register Z as per fig. 7.1 and 7.2

The sequence of operations to add the contents of register R1to those of register R2 and store the
result in register R3 is:

 The signals whose names are given in any step are activated for one clock cycle, others
are inactive.

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 In step 1, the output of register R1 and input of Y are enabled which causes the contents
of register R1 transferred over bus to Y.
 In step 2, the SelectY signal causes the multiplexer to gate the contents of register Y to
input A of ALU. At the same time the contents of register R2 are gated onto bus and
hence to input B. The Add line is set to 1 causing the output of ALU to be the sum of two
numbers at inputs A and B. Zin is activated to load the sum into register Z.
 In step 3 the contents of Z are transferred to R3.

Fetching a Word from Memory

We already know that to fetch an information from memory, the processor transfers the address
into MAR whose output is connected to address lines of memory bus. At the same time, the
processor issues Read operation using control lines of memory bus. The requested data which is
received from memory is stored in MDR.

 The figure below shows the connections for register MDR

 It has four control signals – MDRin, MDRout, MDRinE, MDRoutE.

 MDRin and MDRout control the connection to internal bus.
 MDRinE and MDRoutE control the connection to the external bus.
 The circuit in the fig. 7.3 can be easily modified to provide additional connections.
 A three input multiplexer can be used with memory bus data line connected to the third
input which is selected when MDRinE = 1.
 A second tri-state gate controlled by MDRoutE can be used to connect the output of the
flipflop to the memory bus.
 A processor normally completes one internal data transfer in one cycle.
 However, the addressed device sometimes may be slow. So cache is used which responds
to memory read requests in one cycle. When a cache miss occurs, the request is
forwarded to main memory which takes several clock cycles.

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 Some I/O registers are not cached and hence may take more time for read and write
operations.
 To accommodate variability in response time, the processor waits for a control signal
indication completion of the process. That control signal is Memory Function
Completed (MFC). The address device sets MFC to 1 to indicate the contents of
specified memory location have been read and available on data lines of memory.
 Example – Consider an instruction MOV (R1),R2 – The actions needed to execute this
instruction are:

 These actions may be carried out as separate steps or combined into a single step.
 Each action can be completed in one clock cycle except step 3 which may need more than
one clock cycle depending on the speed of the addressed device.
Timing Diagram Explanation
 When an address is loaded into MAR, it will appear on the memory bus at the
beginning of next clock cycle as shown in the fig. below.
 A Read signal is activated at the same time MAR is loaded. This signal will cause
the bus interface circuit to send MR on the bus.
 Next control signal MDRinE in activated while waiting for a response from
memory.
 Thus the data received from memory is loaded into MDR at the end of clock cycle
in which MFC signal is received.
 In the next clock cycle MDRout is activated to transfer data to register R2.
 Thus the memory read operation requires three steps (WMFC is the control signal
that causes the processor’s control circuitry to wait for arrival of MFC signal).

 MDRinE is set to 1 for the same period of time as the read command MR.

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Storing a Word in Memory

 The desired address is loaded into MAR.

 The Data to be written is loaded into MDR and write signal is issued
 The instruction MOV R2,(R1) requires the following sequence

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 The processor remains in step 3 until the memory operation is completed and an MFC
response is received.

EXECUTION OF COMPLETE INSTRUCTION

Consider an instruction

Add (R3), R1

This instruction adds the contents of memory location pointed to by R3 to register R1. Executing
this instruction requires the following actions:

1. Fetch the instruction

2. Fetch the first operand (contents of memory location pointed to by R3)
3. Perform the addition
4. Load the result into R1

Figure below gives the sequence of control steps required to perform these operations for a
single bus architecture.

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1. In step 1, the instruction fetch operation is initiated by loading the contents of PC into
MAR and sending the Read request to the memory. The Select signal is set to Select4
which causes the multiplexer MUX to select the constant 4. This value is added to the
operand at input B, which is the contents of the PC and the result is stored in Z.
2. In step 2, the updated value is moved from register Z back into PC. To speed up the
execution of Branch instruction, the value of PC is copied into register Y. But this is not
necessary while executing Add instruction.
3. In step 3, the word fetched from memory is loaded into the IR.
4. At the beginning of step 4, the instruction decoding circuit interprets the contents of the
IR. This enables the control circuitry to activate the control signals for steps 4 through 7.
The contents of register R3 are transferred to the MAR and memory read operation is
initiated.
5. In step 5, the contents of R1 are transferred to register Y.
6. In step 6 addition operation is performed. The contents of MDR are gated to the bus and
also to B input of ALU. The register Y is selected as the second input of ALU by
choosing SelectY.
7. In step 7, the sum is stored in register Z and then transferred to R1. Then it returns to step
1.

Branch Instructions

A Branch instruction replaces the contents of the PC with branch target address. This address is
obtained by adding an offset X which is given in the branch instruction. Figure below shows the
control sequence for an unconditional branch instruction.

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 The processing starts with the fetch phase. This phase ends when instruction is loaded
into IR in step 3.
 The offset value is extracted from IR by the instruction decoding circuit.
 The offset X is gated into the bus in step 4 and the addition operation is performed.
 The result which is the branch target address is loaded into the PC in step 5.
 The offset X is difference between the branch target address and the address immediately
following the branch instruction.
 Example - If Branch instruction is at location 2000 and if the branch target address is
2050, the value of X must be 46.
 When the branch instruction is computed in step 4, the PC value used is the updated
value which points to the instruction following the branch instruction in memory.
 In case of conditional branch, condition codes are checked before loading a new value
into PC.
 Example - Branch-on-negative (Branch < )) instruction, step 4 is replaced with

If N = 0 the processor returns to step 1 immediately after step 4. If N = 1, step 5 is

performed to load the new value into PC.

MULTIPLE BUS ORGANIZATION

In single bus structure only one data can be transferred over the bus in one clock cycle. Hence
some processors have multiple internal paths.

 The fig below shows three bus structure used to connect registers and ALU.
 All general purpose registers are combined into a single block called register file.
 The register file has 3 ports. The two output ports allow the contents of two different
registers to be placed on bus A and B. The input port allows the contents of bus C to be
placed into a third register during the same clock cycle.
 Buses A and B are normally used for passing input operands to ALU. Bus C passes the
result to the destination. This arrangement avoids the need for registers Y and Z. If
needed ALU may simple pass one of its two operands unmodified to bus C by using
control signals R=A or R=B.
 The second feature in the figure below is Incrementer unit which is used to increment PC
by 4. This eliminates the need to add 4 to PC everytime using the main ALU.
 Consider a three operand instruction
ADD R4,R5,R6
 The control sequence for executing this instruction is given in the figure 7.9 below.

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 The contents of PC are passed through the ALU using R=B control signal and
loaded into the MAR to start the memory read operation. At the same time PC is
incremented by 4. (MAR has original contents of PC. PC is incremented at the end
of the clock cycle. This will not affect the contents of MAR).
 In step 2 the processor waits for MFC
 In step 3 the processor loads the data from MDR to IR.
 In step 4 all the remaining execution operations can be carried out thus reducing
the number of steps.

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HARDWIRED CONTROL

To execute instructions, the processor must have some means of generating the control signals
needed in the proper sequence. This can be done by hardwired control or microprogrammed
control. The figure below shows the Control Unit Organization.

The decoder/encoder block in the above figure is a combinational circuit that generates the
required control outputs depending on the state of all its inputs. A more detailed block diagram
by separating decoder and encoder blocks is shown in the fig. below.

 The step decoder provides a separate signal line for each step/time slot.
 The output of Instruction Decoder consists of separate lines for each machine instruction.
 Depending on the instruction any one of INS1 to INSm is set to 1 and all other lines are set
to 0.
 The input signals to the encoder block are combined to generate individual control
signals Yin, PCout, Add, End and so on.

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 Example on how encoder generates Zin control signal. This signal is asserted during
time slot T1 for all instructions, during T4 for an unconditional branch instruction and so
on. This is derived from the control sequences in fig. 7.6 and fig. 7.7

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 Example on how to generate End control signal. This signal starts a new instruction fetch
cycle by resetting the control step counter to its starting value.

 There is another control signal RUN which is incremented by one at the end of every
clock cycle. When RUN is equal to 0, the counter stops counting. This is needed
whenever the processor has to wait for WMFC signal.
 Figures 7.10 and 7.11 can be viewed as state machine that changes from one state to
another in every clock cycle depending on the contents of IR, condition codes and
external inputs. The sequence of operations carried out by this machine is determined by
the wiring of the logic elements. Hence the name "hardwired".

A Complete Processor

A complete processor can be designed using the structure shown in the figure 7.14.

 It has an instruction unit that fetches instructions from an instruction cache or main
memory.
 It has separate processing units to deal with integer and floating point data.
 A data cache is used between these units and main memory.
 A processor may include several integer and floating point units to increase the potential
for concurrent operations.

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MICROPROGRAMMED CONTROL

In this method, the control signals are generated by a program similar to machine language
programs. Some common terms are:
 Control Word(CW) - It is a word whose individual bits represent the various control
signals. The CWs corresponding to 7 steps of fig 7.6 is shown in the fig. below. SelectY s
represented by Select = 0 and Select4 is represented by Select = 1. A sequence of CWs
corresponding to the control sequence of a machine instruction constitutes the

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microroutine for that instruction. and individual control words in this microroutine are
referred to as microinstructions.

 Control Store - It is a special memory that stores the microroutines for all instructions.
The control unit can generate control signals by reading the CWs of the corresponding
microroutine. The basic organization of a microprogrammed control unit is shown in the
figure below.

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 Explanation: Micro-program counter (µPC) is used to read the control words

sequentially from the control store. Everytime a new instruction is loaded into the IR, the
output of the block labeled "starting address generator" is loaded into the µPC which is
then automatically incremented by clock. causing successive micro instructions to read
from the control store.
 To check the condition codes condition branch microinstructions are used. These
instructions specify which of the external inputs, condition codes or bits of instruction
register should be checked as a condition for branching to take place.
 Microroutine for Branch < 0 is shown in the figure below.

 Explanation of the above microroutine - The branch microinstruction transfers the

control to the corresponding microroutine that starts at location 25 in the control store.
This address is the output of starting address generator block. The microinstruction at
location 25 tests the N bit of the condition codes. If it is 0, the branch takes place to
location 0 to fetch the next instruction. Otherwise the microinstruction at location 26 is
executed that puts the branch target address into register Z. The microinstruction at
location 27 loads this address into the PC.
 The organization of the control unit to allow conditional branching in the microprogram
is shown in the figure below

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 The starting address generator becomes the starting and the branch address generator.
This block loads a new address into the µPC when a microinstruction instructs it to do so.
The inputs to this block consists of the external inputs and condition codes as well as
contents of IR.
 The µPC is incremented every time a new microinstruction is fetched from the
microprogram memory except
o When new instruction is loaded into IR, its starting address is loaded into µPC.
o During branch microinstructions, µPC is loaded with branch address.
o When End microinstruction is encountered, µPC is loaded with the address of first
CW in the microroutine.

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