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Digital Circuits
Assignment- Week 4
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

The boolean expression 𝐴̅ 𝐵 + 𝐴𝐵̅ + 𝐴𝐵 is equivalent to?

a) 𝐴+𝐵
b) 𝐴̅ . 𝐵
c) ̅̅̅̅̅̅̅̅
𝐴+𝐵
d) 𝐴.𝐵

Correct Answer: A

Detailed Solution:

𝐹 = 𝐴̅ 𝐵 + 𝐴 𝐵̅ + 𝐴𝐵

= 𝐵 (𝐴 + 𝐴̅ ) + 𝐴 𝐵̅ = 𝐴 ( 𝐵 + 𝐵̅ ) + 𝐴̅ 𝐵

= 𝐵 + 𝐴 𝐵̅ = 𝐴 + 𝐴̅ 𝐵

= (𝐵 + 𝐵̅ )(𝐴 + 𝐵) = (𝐴 + 𝐴̅ )(𝐴 + 𝐵)
= (𝐴 + 𝐵) = (𝐴 + 𝐵)

Question 2:

The input to a logic gate is A = 1100 and B = 1010. What will be the output, if the logic gate
is NAND gate?
a) 1101
b) 0111
c) 0110
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d) 1011

Correct Answer: b

Detailed Solution:

We are given inputs:

 A=1100
 B=1010
 The logic gate is a NAND gate.

Question 3

The combinational circuit implementation of the following boolean function

F(A,B,C) = Σ(1,2,4,7)
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(a)

(b) A

B
C

A
(c)
B

(d)

Correct Answer: (a) A BC

Detailed Solution:
F(A,B,C) = Σ(1,2,4,7)
=(ABC+ABC+ ABC+ABC)
=(AB+AB)C+ (AB+AB)C
=(AB+AB)C+ (AB+AB)C= (AB+AB)  C=A B C

Question 4:

For following logic diagram which expression is true?

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̅̅̅̅̅̅̅̅̅̅̅̅
A) ̅̅̅̅
𝐴𝐵 + 𝐴𝐵
B) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ 𝐵̅ . 𝐴. 𝐵
𝐴.
C) ̅̅̅̅̅
𝐴𝐵. 𝐴𝐵
D) (A.B) (𝐴.̅̅̅̅̅̅̅
𝐵)

Correct Answer: B

Detailed Solution:

QUESTION 5:
The output of the logic gate in the figure below is :

(A) 0
(B) 1
(C) A
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(D) A̅

Corrected Answer: d

Detailed Solution:

1) If B is always LOW, the OUTPUT is the inverted value of the INPUT A, i.e A’
2) The OUTPUT is LOW when both the inputs are different.
3) The OUTPUT is HIGH when both the inputs are the SAME.

QUESTION 6:
The number of inputs and outputs in a half adder circuit are?
a) 2 and 1
b) 4 and 2
c) 1 and 1
d) 2 and 2

Correct Answer: d

Detailed Solution:

A half adder is a combinational circuit that performs the addition of two single-bit binary
numbers.

 2 inputs:
o A (first bit)
o B (second bit)

 2 outputs:
o Sum (S): XOR of A and B

S=A⊕B

o Carry (C): AND of A and B

C=A⋅B

 Number of inputs: 2
 Number of outputs: 2
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QUESTION 7:

The output Y in the circuit below is always ‘1’ when

a) Two or more of the inputs P, Q, R are ‘0’

b) Two or more of the inputs P, Q, R are ‘1’
c) Any odd number of the inputs P,Q, R is ‘0’
d) Any odd number of the inputs P,Q, R is ‘1’

Correct Answer: b

Detailed Solution:
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If any two or more inputs are ‘1’ , then output will be 1.

QUESTION 8:
In the circuit shown in the figure, if C = 0, the expression for Y is

a) Y = AB’ + A’B
b) Y=A+B
c) Y = A’ + B’
d) Y = AB

Correct Answer: a

Detailed Solution:
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QUESTION 9:
In the figure shown, the output Y is required to be Y = 𝐴 . 𝐵 + 𝐶̅ 𝐷
̅ . The gates G1 and G2
must be respectively?

A) NOR, OR
B) OR, NAND
C) NAND, OR
D) AND, NAND

Correct Answer: A

Detailed Solution:

QUESTION 10:
What is the primary cause of glitches in digital circuits?
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A) Manufacturing defects in the integrated circuits.

B) Variations in gate delays due to process variations.

C) Incorrect connections in the circuit layout.

D) Inadequate power supply voltage.

Correct Answer: B

Detailed Solution:

Glitches in digital circuits are primarily caused by variations in gate delays due to process
variations in integrated circuits. These variations can lead to differences in signal arrival
times, causing temporary and unwanted changes in the output signal. Glitches are transient
errors that occur due to the non-ideal behavior of the digital components, such as gates and
flip-flops, in the presence of varying delays.

QUESTION 11:
The output Y of the logic circuit given below is:

(A) 1
(B) 0
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(C) X
(D) X̅

Corrected Answer: A

Detailed Solution:

QUESTION 12:

Identify the logical operations performed by the given circuits?

a) a) AND gate , b) OR gate
b) a)NAND gate , b) OR gate
c) a) OR gate , b) AND gate
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d) a) NAND gate , b) NOR gate

Correct Answer: A

Detailed Solution:

𝐴 . 𝐵 ; 𝑌 = 𝑋̅ = ̅̅̅̅̅̅
𝑋 = ̅̅̅̅̅̅ 𝐴.𝐵 = 𝐴.𝐵 ( AND gate)

𝑃 = 𝐴̅ ; 𝑄 = 𝐵̅ ; 𝑃 . 𝑄 = ̅̅̅̅̅̅̅
𝑌 = ̅̅̅̅̅̅ ̅̅̅
𝐴 . 𝐵̅ = A + B (OR gate)

QUESTION 13:
The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The
minimum number of gates required is:

a) 2

b) 3

c) 4

d) 5

Correct Answer: b

Detailed Solution:

QUESTION 14:
Which of the following Boolean Expressions correctly represents the relation between P, Q,
R and Y ?
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A) Y = ( P OR Q) XOR R
B) Y = ( P AND Q) XOR R
C) Y = ( P NOR Q) XOR R
D) Y = ( P XOR Q) XOR R

Correct Answer: (D)

Detailed Solution:

QUESTION 15:

Which of the following terms refers to the maximum amount of unwanted voltage (noise)
that can be present at the input of a digital logic gate without causing a change in its output
logic level?

A) Noise Margin
B) Noise Immunity
C) White Noise
D) Signal-to-Noise Ratio
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Correct Answer: A

Detailed Solution

Noise Margin is the measure of how much noise voltage a digital logic circuit can tolerate at
its input without changing the intended output. It defines the safety buffer for logical high
and low levels.

************END*******
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Digital Circuits
Assignment 5- Week 5
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

Question 1:
Find the number of 2 x 1 MUX (multiplexers) required to implement 16 x 1 MUX

a) 15
b) 20
c) 5
d) 9

Answer: (A)

Detailed Solution:

Step 1: Understanding

A 16×1 multiplexer has:

 16 inputs

 1 output

 4 select lines (because 2^4 = 16)

A 2×1 MUX selects between 2 inputs using 1 select line.

Step 2: Breaking down

We can think of this as building in levels:

1. Level 1: Combine 16 inputs into 8 outputs

o Each 2×1 MUX takes 2 inputs → 1 output

o For 16 inputs, we need 16/2=8 MUXes.

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2. Level 2: Combine 8 outputs into 4 outputs

o Need 8/2=4 MUXes.

3. Level 3: Combine 4 outputs into 2 outputs

o Need 4/2=2 MUXes.

4. Level 4: Combine 2 outputs into 1 output

o Need 2/2=1 MUX.

Step 3: Total
Total number of 2×1 MUXes:
8+4+2+1=15

QUESTION 2:
Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C
and D, the values for A0, A 1, A 2 and A3 are ___________.
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a) A₀ = 1, A₁ = 0, A₂ = 1, A₃ = 1
b) A₀ = 1, A₁ = 0, A₂ = 1, A₃ = 0
c) A₀ = 0, A₁ = 1, A₂ = 1, A₃ = 0
d) A₀ = 1, A₁ = 1, A₂ = 0, A₃ = 0

Answer: (C)

Detailed Solution:

QUESTION 3:

The logical function realized by the circuit shown below is:

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A) Y = P Q

B) Y = P + Q

C) Y =

D) Y = +

Correct Answer: (A)

Detailed Solution:

QUESTION 4:
The number of select lines for 32 to 1 multiplexer is
a) 4
b) 5
c) 16
d) 6

Correct Answer: b

Detailed Solution:

The number of select lines for 32 (25) to select one input among them, total (log232) or 5
select lines are required.
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QUESTION 5:
Identify the following circuit

a) 2 to 4 Decoder
b) 1:4 De-multiplexer
c) 4-2 Encoder
d) None

Correct Answer: (b)

Detailed Solution:
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QUESTION 6:

Octal to Binary Encoders are made by three _____________ gates?

a) NOT gate
b) OR gate
c) AND gate
d) NAND gate

Correct Answer: (b)

Detailed Solution:

Encoders are made by Three OR gates. Octal to Binary Encoder has eight inputs, A7 to A0
and three outputs B2, B1 and B0.
The Truth table of octal to the binary encoder is shown below:

Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 +D5 + D6 + D7
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QUESTION 7:
In binary coded decimal (BCD) system, the decimal number 81 is represented as

a) 10000001
b) 10100010
c) 01010001
d) 00011000

Correct Answer: (a)

Detailed Solution:

________
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QUESTION 8:

The excess-3 code of decimal 7 is represented by

a) 1001

b) 1100

c) 1011

d) 1010

Correct Answer: ( d)

Detailed Solution:

Write 7 in 4-bit binary (BCD):

7=(0111)2
Add 3 (0011):

0111 (7)

+ 0011 (3)
-------

1010 (result)

Do the binary addition bit by bit (LSB → MSB):

 LSB: 1+1=0 carry 1

 Next bit: 1+1+carry 1=3=1 carry 1

 Next bit: 1+0+carry 1=2=0 carry 1

 MSB: 0+0+carry 1=1 carry 0

So the final 4-bit XS-3 code is 1010.

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QUESTION 9:

The logic function implemented by the circuit below is (ground implies a logic "0"

a) F = AND (P, Q)
b) F = OR (P, Q)
c) F = XNOR (P, Q)
d) F = XOR (P, Q)

Answer: (D)

Detailed Solution:
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QUESTION 10:

The number (762)10 would be represented in 8421 code or BCD code as

a) (0010 0110 0111)

b) (1111 1101 0101)
c) (0111 0110 0010)
d) (1000 0100 0010)
Correct Answer: c

Detailed Solution:

In 8421 or Binary Coded Decimal (BCD), each decimal digit is represented with a group of
4-binary bits group.

(7 6 2 )10
(0111 0110 0010)
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QUESTION 11:

The Boolean expression for the output of the multiplexer shown below is:

A)

B)

C) P+Q+R

D)

Correct Answer: (B)

Detailed Solution:
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QUESTION 12:

The equivalent Gray Code of the binary number (1011)2 is

a) (1101)
b) (1011)
c) (1110)
d) (1100)

Correct Answer: (c)

Detailed Solution:

Step 1: The most significant bit (MSB) of the Gray code is the same as the MSB of the binary
number.

 MSB = 1 → Gray MSB = 1

Step 2: For the remaining bits, perform XOR between the current binary bit and the
previous binary bit.

Binary: 1 0 1 1

 1⊕0=1

 0⊕1=1

 1⊕1=0
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Step 3: Combine results:

Gray code = 1 1 1 0

QUESTION 13:
The number of (2 to 4) Decoders required to implement (4 to 16) Decoder is
a) 6
b) 4
c) 5
d) 7

Correct Answer: c
Detailed Solution:

Step 1 – Understanding the structure

 A 4-to-16 decoder has 4 input lines and 16 output lines.

 We can split the inputs into two groups:

o Upper 2 bits → Used for enabling one of four decoders.

o Lower 2 bits → Used as actual inputs to the final decoding stage.

Step 2 – Implementation

1. First stage: Use one 2-to-4 decoder to decode the upper 2 bits into 4 enable signals.

2. Second stage: Use four 2-to-4 decoders, each enabled by one of the outputs from the
first stage, to decode the lower 2 bits.

Step 3 – Total decoders needed

 First stage: 1 decoder

 Second stage: 4 decoders

 Total = 1 + 4 = 5 decoders
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QUESTION 14:

Perform the addition of (30)10 and (15)10 using the BCD scheme. The correct BCD result is,

A) 0100 0101
B) 0101 0100
C) 0011 0100
D) 1000 0101

Correct Answer: ( A)
Detailed Solution:
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QUESTION 15:

The Boolean function f implemented as shown in the figure using two input multiplexer is:

Correct Answer: (A)

Detailed Solution:

The output of the 1st MUX will be ,

The final output will be:

************END*******
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Digital Circuits
Assignment 6- Week 6
TYPE OF QUESTION: MCQ
Number of questions: 16 Total mark: 16 X 1 = 16

QUESTION 1:

The minimum number of N flip-flops required to construct any counter with a given modulus must
satisfy which of the following condition?

A) 2N− 1 ≤ modulus ≤ 2N−1

B)
2N−1 + 1 ≤ modulus ≤ 2N
C) 2N + 1 ≤ modulus < 2N+1
D) 2N+1 + 1 ≤ modulus ≤ 2N

Correct Answer: B

Detailed Solution:
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QUESTION 2:
The present output of an edge triggered J-K Flip-Flop is logic 0. If J=1, then

a) Cannot be determined
b) Will be logic 1
c) Will be logic 0
d) Will race around

Correct Answer: b

Detailed Solution:

QUESTION 3:

The J input of a J-K flipflop is connected to logical 1. The K input is connected

to of the same flipflop. Assume that the flipflop is initially

cleared and then 6 clock pulses are applied. What is the output sequence at Q?

a) 0 1 0 0 1 0

b) 0 1 1 0 0 1

c) 0 1 1 1 1 1

d) 0 1 0 1 0 1
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Correct Answer: C

Detailed Solution:
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QUESTION 4:

The output of the circuit is shown will be of frequency_____________

a) 125 Hz

b) 250 Hz

c) 375 Hz

d) 500 Hz

Correct Answer: a

Detailed Solution:
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Another Solution:

QUESTION 5:

Two D flip-flops are connected as synchronous counter that goes through the following (QBQA)
sequence 00, 11, 01, 10 , 00.. The combination of the inputs DA and DB are?

A)

B)

C)

D)

Correct Answer: D

Detailed Solution:
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D FlipFlops are connected as a synchronous counter output sequences:

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QUESTION 6:

What is the functionality of the following digital circuit?

A is input data, CLK is system clock and Y is output.

A) Falling edge detection of input A

B) Clock division by 2
C) Rising edge detection of input A
D) Clock division by 4

Correct Answer: A

Detailed Solution:

D Flip-Flops are used as a apart of memory storage elements and data processor as well. Due to
their versatility, they are available as IC packages.

The major application of D Flip Flops are to introduce delay in timing circuit, as a buffer,
sampling data at specific intervals.

The truth table is presented below:

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D Q(n+1)
0 0
1 1

The characteristic equation is : Q(n+1) = D

The excitation table is shown below:

Q(n) Q(n+1) D
0 0 0
0 1 1
1 0 0
1 1 1

From the given sequential circuit the output equation can be written as:

To make the output 1 = Q1 Q0 = 01.

The below table shows the variation of the flip-flop for respective inputs:

QUESTION 7:

The flip-flop behaves as a:

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a) JK flip-flop

b) RS flip-flop

c) D flip-flop

d) T flip-flop

Correct Answer: D

Detailed Solution:

Therefore, the flip-flop behaves as a T (Toggle) flip-flop (frequency divider by 2).

QUESTION 8:

Toggle condition is present in which of the following?

a) D flip-flop

b) Clocked SR flip-flop

c) SR latch
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d) JK flip-flop

Correct Answer: D

Detailed Explanation:

Truth table of JK flip-flop:

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1

So the output will toggle when both the inputs are 1, i.e J = K = 1.

QUESTION 9:

The expression of X output of the following PLA circuit is

A) X=ABC+ABC+ABC+ABC

B) X=A BC +ABC+ABC+ABC

C) X=ABC+ABC+ABC+ABC

D) X=ABC+ABC+ABC+ABC
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Correct Answer: B

Detailed Solution:

ABC
ABC

ABC

ABC

X=A BC +ABC+ABC+ABC

QUESTION 10:

In a D flip-flop, if D=1, then the output of the flip-flop becomes _____; but if D=0, then the output of the

flip-flop goes to _____ on the next clock edge.

a) 0 ; 0

b) 1 ; 0

c) 1 ; 1

d) 0 ; 1

Correct Answer: b

Detailed Solution:
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QUESTION 11:
A 1 MHz clock is applied to a J - K =1. What is the frequency of the flip-flop O/P signal?

a) 2 MHz
b) 500 kHz
c) 250 kHz
d) 500MHz

Correct Answer: b
Detailed Solution:
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QUESTION 12:
How to implement D Flip-Flop using J-K Flip-Flop?

Correct Answer: D

Detailed Solution:
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QUESTION 13:
In a J-k Flip-Flop, when Jn = 0, and Kn = 1, the output Qn+1 will have a value of?

a) Qn

b) Q̅n

c) 1

d) 0
Correct Answer: d
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Detailed Solution:

QUESTION 14:
The minimum number of flip-flops needed to construct a BCD decade counter is:

a) 3

b) 4

c) 6

d) 10

Correct Answer: b
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Detailed Solution:

QUESTION 15:

How many flip flops circuits are needed to divide by 16?

a) 2

b) 4

c) 8

d) 16

Correct Answer: b

Detailed Solution:
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QUESTION 16:

When a sequential circuit changes its state only on the occurrence of clock pulses at fixed time
intervals, the machine is called:

A) Combinational Logic Circuit

B) Synchronous Sequential Machine
C) Asynchronous Sequential Machine
D) None of the above

Correct Answer: B

Detailed Solution:

Synchronous sequential circuit transits from one state to the next state at discrete instants of time
controlled by a clock.

************END*******
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Digital Circuits
Assignment- Week 7
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
______________________________________________________________________________

QUESTION 1:

For the logic circuit given below, the decimal count sequence and the modulus of the
circuit corresponding to A B C D are?

A) 8 4 2 1 9 5 (MOD 6)

B) 8 4 2 9 5 3 (MOD 6)

C) 2 5 9 1 3 (MOD 6)

D) 8 5 1 3 7 (MOD 5)

Correct Answer: B

Detailed Solution:

The J-K flip-flop with J=k+1 is implementing negative edge triggered T- flip flop.
The output D will change whenever C changes from 1 0.
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The 3 – bit ring counter will count through 3 stages initialization is important to
start ring counter hence let any 1 bit will be 1 say (C = 1)

A B C D
0 0 1 0 2
1 0 0 1 Toggle 9
0 1 0 1 5
0 0 1 1 3
1 0 0 0 Toggle 8
0 1 0 0 4
0 0 1 0 2

The output sequence is

2 9 5

4 8 3
The counter counts 6 stages. Hence it is mod- 6 counter.

QUESTION 2:
The contents of the following registers (Q4Q3Q2Q1Q0) after two clock transitions are.
(Assume initial values of all flip-flops are logic 1).

A) 1 1 1 1 0
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B) 1 1 0 0 1

C) 1 1 0 1 0

D) 1 1 1 0 0

Correct Answer: D

Detailed Solution:
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QUESTION 3:
The minimum number of flip-flops required to design a mod-150 counter?

A) 8
B) 7
C) 6
D) 15

Correct Answer: A

Detailed Solution:
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QUESTION 4:
An eight – bit binary ripple UP counter with a modulus of 256 is holding the count
01111111. What will be the count after 135 clock pulses?

a) 0000 0101

b) 1111 1001

c) 0000 0110

d) 0000 0111

Correct Answer: C

Detailed Solution:

01111111 127

After 135 clock cycles, we will get 127 + 135 = 262.

The total number of clock pulses will be 262.

As the modulus is 256, after 256 clock pulses, the sequence will repeat.

262 = 256 + 6

257 00 00 00 01

258 00 00 00 10

259 00 00 00 11

260 00 00 01 00

261 00 00 01 01

262 00 00 01 10
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____________________________________________________________________________

QUESTION 5:
In a Johnson counter circuit using negative edge-triggered J-K flip-flops, all flip-flops
are initially reset, resulting in outputs Q₃Q₂Q₁Q₀ = 0000. What are the outputs of the
flip-flops after the fifth negative going pulse?

(A) Q₃Q₂Q₁Q₀ = 0101

(B) Q₃Q₂Q₁Q₀ = 1000
(C) Q₃Q₂Q₁Q₀ = 0010
(D) Q₃Q₂Q₁Q₀ = 1110
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Correct Answer: D

Detailed Solution:
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Sequence Summary

Thus, the first part of the Johnson counter sequence is:

0000 → 0001 → 0011 → 0111 → 1111 → 1110 ⋯0000

QUESTION 6:
The state transition diagram for the logic circuit shown is
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A)

B)

C)

D)

Correct Answer: D

Detailed Solution:

Output expression Y for 2 x 1 MUX is given as

---------------(1)
The next state of D flip-flop is :
--------------------(2)
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From the given circuit :

We know that :
From the given data :
From the equation (2)
A Present State (Q) Next State
0 0 Q=1
0 1 Q=0
1 0 Q=0
1 1 Q=1

QUESTION 7:

If a counter having 10 FFS is initially at 0, what count will it hold after 2060 pulses?

a) 000 000 1100

b) 000 001 1100

c) 000 001 1000

d) 000 000 1110

Correct Answer: A

Detailed Solution:
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QUESTION 8:
For the circuit shown, the counter state (Q 1 Q0) follows the sequence
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a) 00, 01, 10, 11, 00 ….

b) 00, 01, 10, 00, 01 ….

c) 00, 01, 11, 00, 01 ….

d) 00, 10, 11, 00, 10 ….

Correct Answer: B

Detailed Solution:

D-flipflop is a flipflop that produces a delay of exactly one cycle to the CLK.
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QUESTION 9:
A 4-bit shift register is initially loaded with the bit pattern 1010. The register is
clocked repeatedly, and with each clock pulse, the entire pattern shifts one position
to the right; the serial input (leftmost bit) receives the XOR of certain register
outputs (as shown in the feedback loop). After how many clock pulses will the
register content once again become 1010?
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a) 5

b) 7

c) 9

d) 11

Correct Answer: (b)

Detailed Solution:
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Total no. of clock 7.

QUESTION 10:

The following state diagram represents which of the input equation. ( Given D A : [A,
x, y ] ) Where DA denotes a DFF with output A. The x and y are the inputs to the
circuit.
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a)

b)

c)

d)

Correct Answer: C

Detailed Solution:
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QUESTION 11:
The diagram is shown is of a / an _____________
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a) Asynchronous Counter
b) Ring Counter
c) Synchronous Counter
d) Combinational Circuit

Correct Answer: a

Detailed Solution: Follow the lecture material.

QUESTION 12:
Assume initial contents of all D flip-flops are reset to logic 0. The serial input is tied
to logic 1. What are the contents of the registers after three clock cycles?

a) 1100
b) 1110
c) 1011
d) 0011

Correct Answer: b

Detailed Solution:
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This is a 4-bit serial-in, serial-out shift register built from D flip-flops. All flip-
flops are initially reset to 0. The serial input (SI) is tied to logic 1. On every clock
edge, each flip-flop captures the value from the left.
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QUESTION 13:
A three bit shift register is shown below. To have content 000 again, the number of
clock pulses required would be:

a) 2
b) 3
c) 6
d) 7

Correct Answer: C

Detailed Solution:

D - flipflos Truth Table and circuit diagram are shown below :

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When CP =1 then Q = 0 for D = 0

Q1+ = D1 = Q3

Q2+ = D2 = Q1

Q3+ = D3 = Q2
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From the above table, it is clear that the content 0 0 0 will repeat after 6 th clock
pulse.

QUESTION 14:
A counter is constructed with three D flip-flops. The input-output pairs are named
(D0, Q0), (D1, Q1), (D2, Q2), where the subscripts 0 denotes the least significant bit.
The output sequence is desired to be the grey code sequence 000, 001, 011, 010,
110, 111, 101, and 100 repeating periodically. Note that the bits are listed in the
Q2Q1Q0 format. The combinational logic expression for D 1 is,

a)
b)
c)
d) +

Correct Answer: D

Detailed Solution:

Given

000 → 001 → 011 → 010 → 110 →111 → 101 → 100 → 000 → ……….

Table for given condition

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Present State Next state

Q2 Q1 Q0 Q2+ Q1+ Q0+ D2 D1 D0

0 0 0 0 0 1 0 0 1

0 0 1 0 1 1 0 1 1

0 1 1 0 1 0 0 1 0

0 1 0 1 1 0 1 1 0

1 1 0 1 1 1 1 1 1

1 1 1 1 0 1 1 0 1

1 0 1 1 0 0 1 0 0

1 0 0 0 0 0 0 0 0

D1 will have high logic at (1, 3 , 2 , 6) → D1 = 𝛴 m(1, 3, 2, 6)

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QUESTION 15:

The group of bits 01100 is serially shifted (right-most bit first) into 1 5 bits parallel
output shift register with an initial state of 01011. What is the value contained in the
register after 2 clock pulses?

A) 00001

B) 00010

C) 10001

D) 10011

Correct Answer: B

Detailed Solution:

The register consists of four flip-flop stages labelled A, B, C, D. Data in is loaded

serially into stage A with each clock pulse. The output of each stage (QA, QB, QC, QD)
represents the parallel data outputs available at any time.

After the necessary number of clock pulses, the data word can be read in parallel at
these output pins. Key Points from the Image Serial Input: Data is introduced
gradually, one bit per clock pulse, into the first flip-flop.

Parallel Output: Once data filling is complete, all bits can be accessed simultaneously
from the outputs of the flip-flops. Stage Connection: The first flip-flop receives the
serial data, while subsequent flip-flops receive data from the output of the preceding
stage.
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************END*******
 Digital Circuits
Assignment 8- Week 8
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

An 8-bit Digital-to-Analog converter (DAC) using two identical 4-bit DACs with
equal reference voltage is shown in Figure. If b 0 represents LSB, b7 MSB and the op-
amp is ideal, to obtain correct analog values corresponding to an 8-bit DAC at the
output VO, what should be the value of resistor R?

a) 8 k𝛺
b) 0.25 k𝛺
c) 1 k𝛺
d) 0.5 k𝛺

Correct Answer: c
Detailed Solution:
QUESTION 2:

An 8-bit DAC produces an out voltage of 1V for a digital input of 00110010.

Determine the largest value of the output voltage from the DAC?

a) 12.75 kV
b) 5.1 V
c) 255 V
d) 20 mV

Correct Answer: b
Detailed Solution:
QUESTION 3:

For a 4-bit DAC shown below, the output voltage V 0 is ______________ V?

A) 9 V
B) 10 V
C) 11 V
D) 12 V
Correct Answer: A
Detailed Solution:
QUESTION 4:

A 5-bit ladder has a digital input of 11010. Assuming that 0 corresponds to ) V and 1
corresponds to +10 V, it’s output voltage will be:

a) + 6.5 V
b) – 6.5 V
c) -8.125 V
d) + 8.125 V

Correct Answer: d
Detailed Solution:

QUESTION 5:

An 8-bit weighted resistor digital-to analog converter (DAC) has the smallest
resistance of 500 𝛺. The largest resistance has a value of ___________ k𝛺.

a) 64 k𝛺
b) 64 𝛺
c) 6.4 k𝛺
d) 6.4 𝛺

Correct Answer: a
Detailed Solution:
QUESTION 6:

If the resolution of a digital-to-analog converter is approximately 0.4% of it’s full

scale range, then it is a/an ____________ ?

a) 16 - bit converter
b) 10 – bit converter
c) 8 – bit converter
d) 12 - bit converter

Correct Answer: c
Detailed Solution:
QUESTION 7:

An analog-to-digital converter with resolution 0.01V converts analog signals

between 0 V to +10 V to an unsigned binary output. The minimum number of bits
(in integer) in the output is ___________ ?
a) 10
b) 20
c) 30
d) 40
Correct Answer: A
Detailed Solution:
For an ADC,
𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 =
22

10 − 0
0.01 =
2𝑛
2𝑛 = 1000

QUESTION 8:

An 8-bit DAC produces an out voltage of 1 V for a digital input of 00110010.

Determine the largest value of the output voltage from the DAC?

a) 12.75 kV
b) 5.1 V
c) 255V
d) 20 mV

Correct Answer: b
Detailed Solution:
QUESTION 9:

How many comparators are used ina 4 – bit flash Analog-to-Digital Converter
(ADC)?

a) 15
b) 4
c) 5
d) 16
Correct Answer: a
Detailed Solution:

For an n-bit flash ADC, the number of comparators required is:

N=2n−1

Substitute n=4

N=24−1=16

QUESTION 10:

For a 10-bit digital ramp ADC using 500kHz clock, the maximum conversion time is?

a) 2084 µs
b) 2064 µs
c) 2046 µs
d) 2084 µs

Correct Answer: c
Detailed Solution:
QUESTION 11:
Size of the priority encoder required for 4-bit flash ADC?
A) 16 : 4
B) 4 : 2
C) 8 : 3
D) 32 : 5

Correct Answer: a

Detailed Solution:

QUESTION 12:

A 4-bit weighted-resistor DAC with inputs b3, b2, b1, and b0, and (MSB to LSB) is
designed using an ideal opamp, as shown below. The switches are closed when the
corresponding input bits are logic ' 1 ' and open otherwise.
When the input b3, b2, b1,b0 changes from 1110 to 1101, the magnitude of the change
in the output voltage V0 (in mV , rounded off to the nearest integer) is ____________.

a) 245 mV
b) 250 mV
c) 255 mV
d) 260 mV

Correct Answer: b

Detailed Solution:
QUESTION 13:
The advantage of using a dual slope ADC in a digital voltmeter is that

a) Its conversion time is small

b) Its accuracy is high
c) It gives output in BCD format
d) It does not require a comparator.

Correct Answer: b

Detailed Solution:

The key feature of a dual-slope ADC (commonly used in digital voltmeters) is that it
integrates the input voltage over a fixed period, then de-integrates using a reference.
This process cancels out errors due to noise, offset, and component drift, making the
method highly accurate even if it is slower.

QUESTION 14:
For a sequence detector detecting ‘1 0 1 1 0’ (Mealy Type), how many states and
transitions are there in a state diagram?

a) 6, 10
b) 6, 12
c) 5, 10
d) 5, 12

Correct Answer: c

Detailed Solution:
QUESTION 15:

In a 5-bit successive approximation ADC with reference voltage of 1V, if an input

voltage of 0.9V is applied, after 5 clock cycles the content of SAR is
A) 10100
B) 01100
C) 10011
D) 11100

Correct Answer: D

Detailed Solution:
 Vin = 0.9 V
1st iteration: VDAC = ½ = 0.5
Vin>VDAC SAR content = 10000

2nd iteration: VDAC = 0.5 + 0.25 = 0.75

Vin>VDAC SAR content = 11000

3rd iteration: VDAC = 0.5 + 0.25 + 0.125 = 0.875

Vin>VDAC SAR content = 11100

4th iteration: VDAC = 0.5 + 0.25 + 0.125 + 0.0625 = 0.9375

Vin<VDAC SAR content = 11100

5th iteration: VDAC = 0.5 + 0.25 + 0.125 + 0.03125 = 0.90625

Vin<VDAC SAR content = 11100

After 5 clock cycles SAR content = 11100

Another Solution:
 Digital Circuits
Assignment 9- Week 9
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

A memory chip has a capacity of 4 kB. How many address lines are required?

a) 10

b) 12

c) 16

d) 14

Correct Answer: B

Detailed Solution:

QUESTION 2:

An SRAM has address lines from A0 to A15 and data width from D) to D7. What is the total
capacity of the SRAM will be?

a) 64 MB

b) 32 KB
 c) 64 KB

d) 16 MB

Correct Answer: C

Detailed Solution:

QUESTION 3:

Consider the following statements comparing static RAM with dynamic RAM:

1. In static RAM typical cell requires more number of transistors than the dynamic RAM.

2. Power consumption per bit of static RAM is less than that of dynamic RAM.

3. Dynamic RAM is less expensive than the static RAM.

Which of the above statement are correct?

a) 1,2 and 3 only

b) 1 and 2 only

c) 2 and 3 only

d) 1 and 3 only

Correct Answer: d
Detailed Solution: Follow the lecture material.

QUESTION 4:

What is the hamming distance between the codes ‘11001011’ and ‘10000111’

a) 2

b) 3

c) 4

d) 5

Correct Answer: b

Detailed Solution:
Step 1: Compare bit by bit:
Code 1: 1 1 0 0 1 0 1 1
Code 2: 1 0 0 0 0 1 1 1

 Bit 1: 1 vs 1 → same
 Bit 2: 1 vs 0 → different (1)
 Bit 3: 0 vs 0 → same
 Bit 4: 0 vs 0 → same
 Bit 5: 1 vs 0 → different (2)
 Bit 6: 0 vs 1 → different (3)
 Bit 7: 1 vs 1 → same
 Bit 8: 1 vs 1 → same

Step 2: Count differences

Total differences = 3

QUESTION 5:

The final code after encoding data bits 1101 into 7 – bit even parity Hamming Code is?

a) 1110101

b) 1011101

c) 1010101
 d) 0110101

Correct Answer: c

Detailed Solution:

Step 1: Positions of parity & data bits

For a 7-bit Hamming code:

 Positions that are powers of 2 are parity bits: 1, 2, 4

 Remaining positions are data bits: 3, 5, 6, 7

So:

Bit positions: 1 2 3 4 5 6 7
P1 P2 D1 P4 D2 D3 D4
Data = 1101 → assign to D1, D2, D3, D4
D1 = 1 (pos 3)
D2 = 1 (pos 5)
D3 = 0 (pos 6)
D4 = 1 (pos 7)

Now layout before parity fill:

Pos: 1 2 3 4 5 6 7
Val: P1 P2 1 P4 1 0 1

Step 2: Calculate parity bits (even parity)

P1 (pos 1): covers bits 1,3,5,7


→ positions 1,3,5,7 = P1,1,1,1 → (1+1+1 = 3 ones, odd) → need P1=1 to make even.
 P2 (pos 2): covers bits 2,3,6,7
→ positions 2,3,6,7 = P2,1,0,1 → (1+0+1 = 2 ones, already even) → P2=0.
 P4 (pos 4): covers bits 4,5,6,7
→ positions 4,5,6,7 = P4,1,0,1 → (1+0+1=2 ones, even) → P4=0.

Step 3: Final Code

Pos: 1 2 3 4 5 6 7
Val: 1 0 1 0 1 0 1
QUESTION 6:
What is the ROM size when it has 16-bit address lines as input and 8-bit data lines as
output?

A) 216 x 8 bits
B) 28 x 16 bits
C) 162 x 8 bits
D) 215 x 8 bits

Correct Answer: A

Detailed Solution:

Step 1: Address lines : 2^16 = 65,536 locations

Step 2: Data width : Each location stores 8 bits (1 byte).

So total ROM size = 2^16 X 8 bits

QUESTION 7:

A programmable logic array (PLA) is shown in the figure.

A) 𝑃 𝑄 𝑅 + 𝑃̅ 𝑄̅ 𝑅 + 𝑃 𝑄 𝑅̅
 B) (𝑃̅ + 𝑄̅ + 𝑅)(𝑃 + 𝑄 + 𝑅)(𝑃 + 𝑄̅ + 𝑅̅ )

C) 𝑃̅ 𝑄̅ 𝑅 + 𝑃̅ 𝑄 𝑅 + 𝑃 𝑄̅ 𝑅

D) (𝑃 + 𝑄 + 𝑅̅ )(𝑃 + 𝑄̅ + 𝑅)(𝑃̅ + 𝑄 + 𝑅̅ )

Correct Answer: C

Detailed Solution:

̅𝑸
A=𝑷 ̅ 𝑹; 𝑩 = 𝑷
̅ 𝑸 𝑹 ;𝑪 = 𝑷 𝑸
̅ 𝑹;

̅𝑸
F=A+B+C=𝑷 ̅ 𝑹+ 𝑷
̅ 𝑸𝑹+ 𝑷𝑸
̅𝑹

QUESTION 8:

The minimum number of AND and OR Gate required for the implementation of boolean
function,
f (A, B, C) = 𝛴m (0, 1, 3, 6, 7)
f (A, B, C) = 𝛴m(3, 5, 6, 7)

using PLA is :
a) 3 AND and 2 OR
b) 4 AND and 2 OR
c) 3 AND and 4 OR
d) 4 AND and 3 OR
Correct Answer: b

Detailed Solution:
𝑌1 = 𝐴̅ 𝐵̅ + 𝐵 𝐶 + 𝐴 𝐵 ; 𝑌2 = 𝐴 𝐶 + 𝐵 𝐶 + 𝐴 𝐵

QUESTION 9:
Given below are two statements: One is labeled as Assertion A abd the other is labeled as
Reason R:

Assertion (A): The biggest advantage of using a PROM as a programmable logic device that
it’s design can be changed and modified rapidly.
Reason (R) : the PROM can generate any possible logic function of input variables because
it generates every possible AND product term.
In the light of the above statements, choose the correct answer from the option given
below.

a) Both (A) and (R) are true and (R) is the correct explanation of (A).
b) Both (A) and (R) are true but (R) is not the correct explanation of (A).
c) (A) is true but (R) is false.
d) (A) is not false but (R) is true.

Correct Answer: b

Detailed Solution:

QUESTION 10:

A ROM is used to store the table for multiplication of two 8 bit unsigned integer, the size of
ROM required is.

a) 256 x 16
b) 64K x 16
c) 64K x 8
d) 256 x 8

Correct Answer: b

Detailed Solution:
QUESTION 11:
A seven-bit Hamming code is received as 1111101. Using the Hamming code error
detection and correction method, identify the correct original code by detecting and
correcting any single-bit error.

a) 1101111

b) 1011111

c) 1111111

d) 1111011

Correct Answer: c

Detailed Solution:

Step 1: Recall Hamming(7,4) layout

In a 7-bit Hamming code:

 Parity bits are at positions 1, 2, 4 (powers of 2).

 Data bits are at positions 3, 5, 6, 7.

So positions are:

Pos: 7 6 5 4 3 2 1
Bits: ? ? ? ? ? ? ?

Received = 1111101 → assign from left (MSB=pos7):

Pos: 7 6 5 4 3 2 1
Bits: 1 1 1 1 1 0 1
Step 2: Compute parity checks (even parity assumed)

 P1 (pos1) covers positions with LSB=1 → 1,3,5,7

= bits(1,3,5,7) = (1,1,1,1) → sum=4 (even). ✅no error in P1 check
 P2 (pos2) covers positions with binary index second bit=1 → 2,3,6,7
= bits(0,1,1,1) = 0+1+1+1=3 (odd) → ❌parity mismatch → error detected
 P4 (pos4) covers positions with third bit=1 → 4,5,6,7
= bits(1,1,1,1) = 4 (even) ✅no error

Step 3: Error syndrome

Syndrome = (P4 P2 P1) in binary = (0 1 0) = 2.

→ Error is in position 2.

Step 4: Correct the error

Received: 1111101
Pos2 bit = 0 → flip to 1.

Corrected code = 1111111

QUESTION 12:

The following steps are involved in the FPGA design flow:

1. HDL Coding / RTL Design

2. Synthesis
3. Static Timing Analysis
4. Place and Route
5. Programming File Generation

Which of the following represents the correct order of the FPGA design flow?

a) 1, 2, 3, 4, 5
b) 1, 2, 4, 3, 5
c) 2, 4, 3, 5, 1
d) 3, 1, 4, 5, 2

Correct Answer: b

Detailed Solution:

Stages of FPGA Design Flow:

1. HDL Coding / RTL Design (A)

o Write design in Verilog/VHDL.
 2. Synthesis (B)
o Converts HDL code into gate-level netlist.
3. Place and Route (D)
o Maps logic onto FPGA resources and places/routs connections.
4. Static Timing Analysis (C)
o Verifies timing constraints after P&R.
5. Programming file generation (E)
o Generates .bit or .sof file to program FPGA.

QUESTION 13:
Which type of memory needs to be regularly refreshed?

a) DRAM

b) ROM

c) SRAM

d) CMOS

Correct Answer: a

Detailed Solution:

QUESTION 14:

If the computer has 32K words, then this memory has ____________ memory locations?

a) 32768

b) 32769

c) 32767
 d) 32000

Correct Answer: a

Detailed Solution:

QUESTION 15:

Implement the following Boolean functions using a Programmable Logic Array (PLA):

F1 = 𝛴m (0, 3, 4, 7)

F2 = 𝛴m (1, 2, 5, 7)

Which of the following diagrams represents the correct PLA implementation of the given
functions?

(a)
(b)

(c)

(d)

Correct Answer: C

Detailed Solution:
 Digital Circuits
Assignment 10- Week 10
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:
What is the full form of VHDL in digital design?

A) Very High Special Integrated Circuits Hardware Description Language

B) Very Hard Description Language
C) Very High Speed Integrated Circuits Hardware Description Language
D) Verilog Hardware Description Language

Correct Answer: C
Detailed Solution:

QUESTION 2:
The code given below is a VHDL implementation of _________

ARCHITECTURE my_circuit OF my_logic IS

BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
x1 WHEN “01”;
x2 WHEN “10”;
x3 WHEN “11”;
END my_circuit;

a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX

Correct Answer: a
Detailed Solution:

1. ARCHITECTURE my_circuit OF my_logic IS

o Declares an architecture named my_circuit for an entity called my_logic.
 o The IS starts the declarative region (you could declare internal signals here).
It can be empty.
2. BEGIN
o Marks the start of the concurrent statements — the hardware description
that runs continuously.
3. WITH ab SELECT
o Starts a selected signal assignment (a concurrent multiplexer construct).
o ab is the select expression (should be a 2-bit discrete type, e.g.
std_logic_vector(1 downto 0)). Its current value chooses which RHS
expression is assigned to y.
o This is concurrent — it behaves like hardware that continuously drives y
based on ab and the inputs x0..x3.
4. y <= x0 WHEN "00",
o If ab = "00", then y is driven with the value of x0. The comma separates this
choice from the next.
5. x1 WHEN "01",
o If ab = "01", then y gets x1.
6. x2 WHEN "10",
o If ab = "10", then y gets x2.
7. x3 WHEN "11";
o If ab = "11", then y gets x3. The semicolon ends the entire WITH ... SELECT
statement.
8. END my_circuit;
o Closes the architecture block.

Important practical notes

 This models a 4-to-1 multiplexer: y outputs one of x0..x3 depending on the 2-bit
selector ab.
 Type/width must match: x0..x3 and y should be the same type/size (e.g. std_logic).
ab should be std_logic_vector(1 downto 0).
 All choices are covered here; if you didn’t cover every possible ab value, add a
WHEN OTHERS => clause to avoid simulation warnings.
 Equivalent (behavioral) implementation using a case inside a process is also
possible if you prefer sequential style.

ab y driven by
"00" x0
"01" x1
"10" x2
"11" x3
QUESTION 3:
Following entity may represent a ________ circuit.

ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC);
END my_circuit;

a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adder

Correct Answer: d
Detailed Solution:
Step 1: Inputs

 a and b are 4-bit input vectors (STD_LOGIC_VECTOR(3 DOWNTO 0)).

→ These are two binary numbers (each 4 bits wide).
→ Range = 0000 (0) to 1111 (15).

Step 2: Outputs

 x is a 4-bit output vector.

→ Likely holds the sum of a and b.
 y is a single-bit output.
→ Typically used as the carry out bit from the addition.

Step 3: Functionality

 The circuit takes two 4-bit inputs and produces:

o A 4-bit sum (x).
o A carry-out bit (y).
 Together, x and y represent a 5-bit result of the addition.

For example:

a = 1011 (11)
b = 0111 (7)
Sum = 10010 (18)
→ x = 0010 (2), y = 1 (carry out)

Step 4: Type of circuit

This matches the definition of a 4-bit Parallel Adder (implemented as 4 full adders
connected in series, aka ripple-carry adder).

 Each bit of a and b is added in parallel.

 The carry propagates through, and the final carry is given as y.

QUESTION 4:
In a 8085 microprocessor system with memory mapped I/O?

a) I/O device has 8 bit address

b) I/O devices are accessed using IN and OUT instructions.
c) There can be maximum 256 input and 256 output devices.
d) Arithmetic and logic operations can be directly performed with I/O data.

Correct Answer: d
Detailed Solution:
QUESTION 5:
8085 microprocessor can operate with _________ clock.

A) 3MHz

B) 8MHz

C) 3GHz

D) 8GHz

Correct Answer: A

Detailed Solution:
QUESTION 6:
Choose an incorrect statement from the following regarding pin number of 8085
microprocessor.

a) Reset out and CLK out are 3 and 37 respectively.

b) GD and VCC are 20 and 40 respectively.
c) INTR and TRAP are 10 and 6 respectively.
d) RST 6.5 and RST 7.5 are 7 and 8 respectively.

Correct Answer: d

Detailed Solution:

QUESTION 7:

What is the instruction set size of an 8085 microprocessor?

A) 74 instructions
B) 47 instructions
C) 128 instructions
D) 64 instructions

Correct Answer: A

Detailed Solution:
QUESTION 8:

Which component is responsible for converting assembly language code into machine
code?

A) Compiler
B) Linker
C) Assembler
D) Interpreter

Correct Answer: C

Detailed Solution:
QUESTION 9:

A microprocessor-based system uses a 2K × 8-bit RAM starting at address CC00H. What is

the last address of this RAM in the memory map?

a) D400H
b) C7FFH
c) D3FFH
d) CDFFH

Correct Answer: C

Detailed Solution:
QUESTION 10:

A microprocessor, by itself (without external components), internally contains which of the

following?

a) ALU, memory, and I/O

b) ALU, control circuits, and register circuits
c) CPU, memory, and I/O
d) CPU and I/O only

Correct Answer: b

Detailed Solution:

QUESTION 11:

Which of the following correctly lists the three main cycles in the instruction execution
model of a microprocessor, in order?
A) Write, Decode, Execute
B) Fetch, Decode, Execute
C) Decode, Fetch, Execute
D) Execute, Fetch, Decode

Correct Answer: b

Detailed Solution:

In a microprocessor, the instruction execution cycle generally follows three main steps:

1. Fetch – The instruction is fetched from memory into the instruction register.
2. Decode – The control unit decodes the fetched instruction to determine the
operation and addressing mode.
3. Execute – The instruction is carried out (ALU operation, data transfer, branching,
etc.).
QUESTION 12:

In the pin out configuration of the 8085 microprocessor, the sequential input data is
represented by,
a) Pin 35
b) Pin 7
c) Pin 5
d) Pin 30
Correct Answer: c

Detailed Solution:

QUESTION 13:

The ALE (Address Latch Enable) pin is primarily used to:

A) Control read and write operations
B) Enable external interrupts
C) Demultiplex the address/data bus
D) Provide power to the chip
Correct Answer: c

Detailed Solution:

In the 8085 microprocessor, the lower 8 bits (AD0–AD7) of the address bus are
multiplexed with the data bus.

 During the first clock cycle (T1), these lines carry the lower 8-bit address.
 In later cycles, they are reused for data transfer.

To separate (demultiplex) the address from the data, the microprocessor uses the ALE
(Address Latch Enable) signal.

 When ALE = 1, the address is latched into an external latch (like 74LS373).
 After latching, the lines are free to be used as a data bus
QUESTION 14:

A microprocessor with a 16-bit address bus is used in a linear memory selection

configuration (i.e. Address bus lines are directly used as chip selects of memory chips) with
4 memory chips. The maximum addressable memory space is
a) 64k
b) 16k
c) 8k
d) 4k

Correct Answer: a

Detailed Solution:

QUESTION 15:

The number of hardware interrupts (which require an external signal to interrupt) present
in an 8085 microprocessor are
a) 1
b) 4
c) 5
d) 13
Correct Answer: c
Detailed Solution:

The 8085 microprocessor has 5 hardware interrupts in total.

They are:

1. TRAP – Non-maskable, highest priority

2. RST7.5 – Maskable, edge-triggered
3. RST6.5 – Maskable, level-triggered
4. RST5.5 – Maskable, level-triggered
5. INTR – General purpose interrupt, lowest priority
 Digital Circuits
Assignment- Week -12
TYPE OF QUESTION: MCQ
Number of questions: 15​ ​ ​ ​ ​ Total mark: 15 X 1 = 15

QUESTION 1:
In a 8085 processor, which bit of flag register is reserved for Auxiliary Carry Flag?

a)​ Bit D7
b)​ Bit D4
c)​ Bit D6
d)​ Bit D2

Correct Answer: b
Detailed Solution:
Bit D7 D6 D5 D4 D3 D2 D1 D0
Flag S Z - AC - P - CY

QUESTION 2:
Which of the following is a two byte instruction in 8085 microcprocessor?

a)​ MOV
b)​ CMA
c)​ ADD
d)​ MVI

Correct Answer: d
Detailed Solution:
QUESTION 3:
An 8085 – microprocessor based system uses a 4K x 8 bit RAM whose starting address is
AA00 H. The address of the last byte in this RAM is:

a)​ 0FFF H
b)​ 1000 H
c)​ B9FF H
d)​ BA00 H

Correct Answer: c
Detailed Solution:

Step 1: Size of RAM

●​ RAM = 4K × 8
●​ 4K = 4096 bytes = 0x1000 (hex)

So the address span = 0x1000 locations.

Step 2: Starting address

●​ Given starting address = AA00H

Step 3: Ending address

●​ Number of locations = 0x1000 → addresses go from AA00H to (AA00H + 0x1000 –

1)

Now compute:

AA00H+0x0FFF=B9FFH

Step 4: Verify

●​ Range: AA00H … B9FFH

●​ That is exactly 4096 (4K) bytes.

QUESTION 4:
If chip select logic is chosen as 𝐴15 𝐴14 𝐴13 𝐴12 FOR A 4k ram IN 8085 for memory
interfacing, it’s memory range would be:

a)​ 6000 – 6FFF H

b)​ 6000 – 7FFFH
c)​ 6000 – 3FFFH
d)​ 5000 – 6FFFH

Correct Answer: a
Detailed Solution:
For memory interfacing of 8085 [4 k RAM]

Chip select logic : 𝐴15 𝐴14 𝐴13 𝐴12

4K RAM = 22 X 210 = 212

That means there are 12 address lines which can vary from lowest (0 0) to the highest
value.

Required memory range = 6000 H to 6FFF H

QUESTION 5:
 Identify the correct addressing mode for following instruction in 8085. STA 2300 H.

a)​ Direct Addressing Mode

b)​ Register Addressing Mode
c)​ Immediate Addressing Mode
d)​ Indirect Addressing Mode

Correct Answer: a
Detailed Solution:

QUESTION 6:
An index registers in a digital computer used for

a)​ Address modification

b)​ For indirect address
c)​ Storing one of the operands
d)​ Pointing to the stake address

Correct Answer: a
Detailed Solution:

QUESTION 7:
How many bit Program counter is available in 8085?

a)​ 8 bit
b)​ 16 bit
c)​ 32 bit
d)​ 4 bit

Correct Answer: b
Detailed Solution:

QUESTION 8:

How many 16K x 1 RAM chips are needed to provide a memory capacity of 128 K-bytes?

a)​ 8
b)​ 4
c)​ 16
d)​ 64
Correct Answer: d
Detailed Solution:

Required = 128 KB

QUESTION 9:

For the instructions inside a nested loop, which combination of instructions is repeated in
the inner loop of the sample code?
A) MVI C, FFH and DCR C
B) DCR C and JNZ LOOP1
C) MVI B, 10H and DCR B
D) JNZ LOOP2 and DCR B

Correct Answer: b
Detailed Solution:
In a typical nested delay loop using 8085, the outer loop loads a counter (e.g., MVI B, 10H)
and decrements it, while the inner loop handles the finer delay using another register (e.g.,
C). Inside the inner loop, the repeated instructions are:
●​ DCR C → decrements the inner counter (4 T-states)
 ●​ JNZ LOOP1 → jumps back if not zero (10 T-states when taken, 7 when not taken)
This pair executes repeatedly until register C reaches zero.

QUESTION 10:
A delay program is written for the 8085 microprocessor using nested loops.
●​ Inner loop instructions:
o​ DCR C → 4 T-states
o​ JNZ LOOP1 → 10 T-states when jump is taken, 7 T-states when jump is not
taken
o​ Register C is initialized with FFH (255 decimal).
o​ Total T-states for the inner loop = 3567 T-states
●​ Outer loop instructions:
o​ MVI C, FFH → 7 T-states
o​ Inner loop → 3567 T-states
o​ DCR B → 4 T-states
o​ JNZ LOOP2 → 10 T-states when jump is taken, 7 T-states when not taken
o​ Register B is initialized with 10H (16 decimal).
If the microprocessor clock has a T-state period of 0.5 μs, what is the total delay produced
by this program?
A) 1.0 mSec​
B) 28.702 mSec​
C) 57.412 mSec​
D) 35.674 mSec
Correct Answer: b
Detailed Solution:

Step 1: Outer loop iterations

●​ B = 16 (10H), so outer loop runs 16 times.

●​ For the first 15 iterations → JNZ LOOP2 is taken (10 T-states).
●​ For the last iteration → JNZ LOOP2 is not taken (7 T-states).

Step 2: T-states for one outer iteration

●​ MVI C, FFH = 7 T
 ●​ Inner loop = 3567 T
●​ DCR B = 4 T
●​ JNZ = 10 T (if taken) or 7 T (if not taken)

●​ Iterations 1–15 = 7 + 3567 + 4 + 10 = 3588 T

●​ Iteration 16 = 7 + 3567 + 4 + 7 = 3585 T

Step 3: Total T-states

●​ First 15 iterations = 15 × 3588 = 53,820 T

●​ Last iteration = 3585 T
●​ Total = 53,820 + 3585 = 57,405 T-states

Step 4: Convert T-states to time

●​ 1 T-state = 0.5 μs
●​ Total delay = 57,405 × 0.5 μs = 28,702.5 μs ≈ 28.706 ms

QUESTION 11:

What is the maximum addressing capability of Intel 8085?

a)​ 64 KB
b)​ 1 MB
c)​ 4 KB
d)​ 32 KB

Correct Answer: a
Detailed Solution:

QUESTION 12:
How many T states are required to execute STA 1234 instruction?
a)​ 7 T
b)​ 4 T
c)​ 10 T
d)​ 13 T
Correct Answer: d
Detailed Solution:
QUESTION 13:

What is the length of Stack Pointer (SP)?

a)​ 6 bits
b)​ 8 bits
c)​ 12 bits
d)​ 16 bits

Correct Answer: d
Detailed Solution:
●​ In the 8085 microprocessor, the Stack Pointer (SP) is a 16-bit register.
●​ It holds the address of the top of the stack in memory.
●​ Since memory addresses in 8085 are 16-bit wide (address range = 0000H to FFFFH),
the SP must also be 16 bits long.
So, the length of the Stack Pointer = 16 bits.
QUESTION 14:
The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an
instruction is 1.4 μs, what is the number of T-states needed for executing the instruction?

A) 1
B) 6
C) 7
D) 4
Correct Answer: C
Detailed Solution:

QUESTION 15:
In 8085 microprocessor, the address for ‘TRAP’ input is
a)​ 0024 H
b)​ 002C H
c)​ 0034 H
d)​ 003C H

Correct Answer: a
Detailed Solution: