ECE 431 Digital Circuit Design
Chapter 7 Combinational MOS
Logic Circuits
Lecture given by Qiliang Li
1
7.1 Introduction
Design Parameters:
Critical voltage points
e.g., VOL and Vth
dynamic transient response
7.2 MOS Logic Circuits with Depletion nMOS Loads
NOR gate
7.2 MOS Logic Circuits with Depletion nMOS Loads
Calculate VOH
VOH = VDD
Calculate VOL
I load ,saturation (VOL ,VDD − VOL ) = I drive,linear (VOH ,VOL )
kload
VOL = VOH − VT 0 − (VOH − VT 0 ) 2 − ( )⋅ | VT ,load (VOL ) |2
kdriver
Use VT0 (for VT,load (VOL)) to calculate VOL , iterate, use VOL to calculate VT,load
i. Va = VOH, Vb = VOL i and ii are Just like we discussed in chapter 6
ii. Va = VOL, Vb = VOH
iii. Va = VOH, Vb = VOH
7.2 MOS Logic Circuits with Depletion nMOS Loads
iii. Va = VOH, Vb = VOH
kload 2 kdriver , A 2 kdriver ,B 2
| VT ,load (VOL ) | = [2(VA − VT 0 )VOL − VOL ] + [2(VB − VT 0 )VOL − VOL ]
2 2 2
Generally VOH = VA = VB
Equivalent driver-to-load ratio
W W
kdriver , A + kdriver ,B kn' ,driver [( ) A + ( )B ]
kR = = L L
kload W
kn' ,load ( )load
L
kload
VOL = VOH − VT 0 − (VOH − VT 0 ) 2 − ( )⋅ | VT ,load (VOL ) |2
kdriver , A + kdriver ,B
7.2 MOS Logic Circuits with Depletion nMOS Loads
linear
µnCox W
ID = (∑( 2
) )[2(VGS − VT 0 )Vout − Vout ]
2 k ( on ) L k
saturation
µnCox W
ID = (∑( ) )(VGS − VT 0 ) 2
2 k ( on ) L k
7.2 MOS Logic Circuits with Depletion nMOS Loads
Transient analysis
The load capacitance at the output node
of the equivalent inverter corresponding
to a NOR gate is always larger than the
total lumped load capacitance of an
actual inverter with the same dimensions.
Two-input NAND gate
P282-283
kload
VOL ≈ 2(VOH − VT 0 − (VOH − VT 0 ) 2 − ( )⋅ | VT ,load (VOL ) |2 )
kdriver
kdriver 2
ID = [2(VGS − VT 0 )VDS − VDS ]
4
1 W
~~~~~~~ ( )
1 L
∑
k ( on ) W
L k
Transient analysis of NAND gate
The value of the lumped capacitance Cload depends on the input voltage conditions.
VA is equal to VOH , VB is swiching from VOH to VOL
VA is equal to VOH , VB is swiching from VOH to VOL
Cload = C gd ,load + C gd , A + C gd ,B + C gs , A + Cdb, A + Cdb,B + Csb, A + Csb,load + Cwire
VB is equal to VOH , VA is swiching from VOH to VOL
Cload = C gd ,load + C gd , A + Cdb, A + Csb,load + Cwire
7.3 CMOS logic circuits
CMOS NOR2
CMOS NOR2
Layout of simple CMOS logic Gate
7.4 Complex logic circuits
7.4 Complex logic circuits – AOI and OAI Gates
AND-OR-INVERT (AOI) –> sum-of-products realization
OR-AND-INVERT (OAI) –> product-of-sums realization
7.4 Complex logic circuits – AOI and OAI Gates
AND-OR-INVERT (AOI) –> sum-of-products realization
OR-AND-INVERT (OAI) –> product-of-sums realization
The pseudo-nMOS implementation of the OAI gate
Example 7.2
CMOS Full-Adder Circuit
Three inputs: A, B and C (carry_in)
sum _ out = A ⊕ B ⊕ C = ABC + ABC + ABC + AC B
carry _ out = AB + AC + BC
Transistor-leve schematic of the one-bit full-adder circuit
Optimized CMOS full adder
CMOS full-adder using minimum-size
transistors
Block diagram of a carry ripple adder chain consisting of full adders
7.5 CMOS Transmission Gates (Pass Gates)
(TG)
Bidirectional switch between the nodes A and B which is controlled by signal C
See figure
VDS ,n = VDD − Vout
VGS ,n = VDD − Vout
The nMOS transistor will be in
saturation for Vout < VDD – VT,n
turned off for Vout > VDD – VT,n
VDS , p = VDD − Vout
VGS , p = −VDD
ID = IDS,n + ISD,P
Equivalent resistance
VDD − Vout VDD − Vout
Req ,n = Req , p =
I DS ,n I SD , p
Region 1: Output voltage is smaller than the absolute value of pMOS
transistor threshold voltage, Vout < |VT, P|.
2(VDD − Vout )
Req ,n =
kn (VDD − Vout − VT ,n ) 2
2(VDD − Vout )
Req , p =
k p (VDD − | VT , p |)2
Region 2: |VT, P| < Vout < (VDD – VT,n ) .
2(VDD − Vout )
Req ,n =
kn (VDD − Vout − VT ,n ) 2
2(VDD − Vout )
Req , p =
k p [2(VDD − | VT , p |)(VDD − Vout ) − (VDD − Vout ) 2 ]
2
Req , p =
k p [2(VDD − | VT , p |) − (VDD − Vout )]
Region 3: Vout > (VDD – VT,n ) .
nMOS will be turned off, resulting in ann open-circuit equivalent.
2
Req , p =
k p [2(VDD − | VT , p |) − (VDD − Vout )]
Using TG for complex gate
Two-input multiplexer circuit implemented using two CMOS TGs
Eight-transistor CMOS TG implementation of the XOR function
Six-transistor CMOS TG implementation of the XOR function
Figure 7.40: (a) CMOS TG realization of a three-variable Boolean function. (b) All pMOS
transistors can be placed into one n-well to save area
layout
Complementary Pass-Transistor Logic (CPL)
The complexity of full-CMOS pass-gate logic circuit can be reduced dramatically by
adopting another circuit concept, call CPL.
The main idea behind CPL is to use a purely nMOS pass –transistor network for the
logic operations, instead of a CMOS TG network.
Disadvantages: “in CPL circuits, the threshold voltages of nMOS transistors in the
pass-gate network must be reduced to about 0 V through threshold-adjustment
implants, in order to eliminate the threshold-voltage drop. This, on the other
hand, reduces the overall noise immunity and makes the transistors more
susceptible to subthreshold conduction in the off-mode.”