SRN

3rd Semester [Link] CSE Semester End Examination June 2023

Course (Subject): Analog Digital Electronics
Course Code: B20CS0301 - 85141
Time: 3 Hours Max. Marks: 100
Note: Answer ONE FULL question from each unit. Marks
UNIT – I
1. a) Outline the basic behavior of a clamping circuit. With a neat circuit diagram, 9
sketch the behavior of an unbiased negative clamper built using ideal diodes.
b) State the condition for oscillations that an oscillator has to satisfy. Give the 9
block representation of an oscillator highlighting the function performed by
each block
c) Design a RC phase shift oscillator (LAG) that generates sinusoidal oscillations 0f 7
2.5 KHz. How many phase shifting networks are required for the given task?
OR
2. a) List the types of Clamping circuits that are possible to realize. Outline the 9
behavior of a Biased negative clamper with a neat diagram and waveforms
assuming ideal diodes
b) Outline the basic behavior of a clipping circuit. With a neat circuit diagram, 9
sketch the behavior of a series unbiased positive clamper built using ideal
diodes.
c) Design a Colpitts oscillator that produces oscillations of 50KHz. Draw the circuit 7
indicating the designed values.
UNIT – II
3. a) Outline the behavior of a Logarithmic amplifier and derive an expression for its 9
o/p voltage
b) Design a first order Low pass active filter to have a cutoff frequency of 3.5KHz 9
providing a pass band gain of 6. Draw its frequency response indicating roll off.
c) With a neat circuit diagram and waveforms illustrate the behavior of an 7
absolute value circuit built using opamp.
OR
4. a) Outline the behavior of an Instrumentation amplifier with a neat circuit 9
diagram. List its requirements and give its o/p voltage equation.
b) Outline the behavior of a peak detector built using opamp with a neat circuit 9
diagram and waveforms.
c) Design a first order High pass active filter to have a cutoff frequency of 5.5KHz 7
providing a pass band gain of 9. Draw its frequency response indicating roll off.
UNIT – III
5. a) A Logic circuit is to be designed that produces an o/p of ‘1’ for all the odd 9
numbers in the range 0 to 8 and even numbers in the range 9 to 15.
i. Draw the truth table of the circuit
ii. Corresponding SOP and POS expressions
iii. Simplified SOP expression using K-map
b) Simplify the given Logical expression using K-map and implement the 9

Page 1 of 2
 simplified expression using (i)Basic gates (ii) Only NAND (III) Only NOR
Y = ∑m(0, 2, 3) + don’t care(4, 7)
c) Simplify the given Logical expression using K-map and implement the 7
simplified expression using (i)Basic gates (ii) Only NAND (III) Only NOR
Y = ∏M ( 2, 5, 6) + don’t care(0)
OR
6. a) A digital system is to be designed in which the months of the year is given as 9
input in 4-bit form. The month January is represented as ‘0000’, February as
‘0001’ and so on. The output of the system is ‘0’ corresponding to the input of
the month containing 30 days or less otherwise it is ‘1’. Consider the excess
number in the input beyond ‘1011’ as don’t care conditions. For this systems of
4 variables (A, B, C, D) find the following
(i) Draw the truth table of the circuit
(ii) Corresponding SOP and POS expressions
(III) Simplified SOP expression using K-map
b) Simplify the given Logical expression using K-map and implement the 9
simplified expression using Basic gates
Y= ∏M(0, 2, 3, 8, 9, 10, 11) + don’t care(5, 13, 14, 15)
c) Simplify the given Logical expression using K-map and implement the 7
simplified expression using Basic gates
Y= ∑m (1, 4, 7, 8, 9 11, 13) + don’t care(3, 5, 6, 12,15)
UNIT – IV
7. a) Realize a 1:4 DE-MUX using basic gates starting from its basic behavior in the 9
truth table form.
b) With a neat diagram, give the behavior in the form of truth table, 9
Characteristic equation and excitation table.
c) Realize a 4-bit Johnson counter using D-ffs. Furnish the shift table that 7
demonstrates the circulation of data ‘1001’. Draw the timing diagram
OR
8. a) Draw the truth table of a full adder. Using the table entries, derive an 9
expression for its outputs and draw the circuit diagram
b) Realize a 4:1 MUX using basic gates starting from its basic behavior in the truth 9
table form.
c) Realize a 4-bit Ring counter using D-ffs. Furnish the shift table that 7
demonstrates the circulation of data ‘1001’. Estimate the time required to
circulate the data if the clock connected to it is 0.5µs.

***

Page 2 of 2
 SRN

3rd Semester [Link] CSE Semester End Examination June 2023

Course (Subject): Analog and Digital Electronics
Course Code: B20EF0301/B21EF0301 – 85531/85551
Time: 3 Hours Max. Marks: 100
Note: Answer ONE FULL question from each unit. Marks
UNIT – I
1. a) Explain the operation of a Positive biased Clipper circuit with neat diagrams. Assume 8
ideal diode.
b) Design a Colpitts oscillator that produces oscillations of 1MHz. Draw the circuit indicating 6
the designed values. Assume an inductor of 1mH and feedback factor of 0.25.
c) Draw the circuit of RC Phase shift oscillator and give the expression for frequency of 5
oscillations
d) Derive an expression for the transfer function of a positive feedback system and State 6
the conditions for oscillations.
OR
2. a) Sketch the behavior of a biased negative Clamper with a neat diagram and waveforms 8
assuming ideal diode
b) A crystal has the following parameters: L=0.5H, Cs=0.06pF; Cp=1pF; R=5kΩ. Find the 5
series and parallel resonant frequencies
c) Design a Wien bridge oscillator that generates a sinusoidal signal of 3 KHz 7
(Assume R or C).Draw the circuit diagram of the oscillator indicating the designed
component values
d) With the help of a neat circuit diagram and waveform explain the working of a double 5
ended clipper.
UNIT – II
3. a) With a neat circuit diagram and waveforms illustrate the behavior of an Absolute value 7
circuit built using op-amp.
b) Design a first order Active Low pass filter for a cut-off frequency of 159Hz and input 6
impedance of 10Kohms The pass band gain of the filter should be 10. What is its Roll-off?
c) It is desired to build a circuit that produces an output proportional to Logarithmic of its 7
input voltage. Propose a suitable circuit using Opamp that performs the required task.
Draw the circuit and derive an expression for its output voltage.
d) Identify the circuit detecting zero crossing of the input signal. Explain the working of the 5
identified circuit with waveforms
OR
4. a) Discuss the behavior of a peak detector built using op-amp with a neat circuit diagram. 7
b) A first order inverting active High pass filter has a pass band gain of 2 and a cutoff 8
frequency of 1 kHz. If input capacitor has a value of 10nF. Calculate the value of the
resistors used in the circuit. Draw the circuit indicating the component values.

Page 1 of 3
 c) Suggest an Opamp circuit used in Industrial applications to amplify the signals produced 10
by the Transducers. List the characteristics of the suggested Amplifier circuit and give its
implementation. What is the expression for its output voltage?
UNIT – III
5. a) A digital system is to be designed in which the months of the year is given as input in 4-bit 10
form. The month January is represented as ‘0000’, February as ‘0001’ and so on. The
output of the system is ‘1’ corresponding to the input of the month containing 30 days or
less otherwise it is ‘0’. Consider the excess number in the input beyond ‘1011’ as don’t care
conditions. For this systems of 4 variables (A, B, C, D) determine the following.
i) Truth table
ii) SOP expression
iii) Simplify SOP expression using K-Map.
iv) Implement the simplified expression using NOR-NOR gates

b) Simplify the given Logical expression using K-map and implement the 8
simplified expression using Basic gates
Y= ∏M(0, 2, 3, 7, 8, 9, 10, 11) + don’t care(5, 13, 14, 15)
c) Simplify the given Logical expression using K-map and implement the simplified expression 7
using (i) Only NAND (ii) Only NOR gates
Y = ∑m(0, 2, 3) + don’t care(4, 7)
OR
6. a) In the phrase “ALL THE BEST”, letter ‘A’ is represented as ‘000’ and ‘L’ as ‘001’ with no 10
repeating of letters. The vowel in the phrase has the output ‘0’ and the other letters have
‘1’as the output in the digital system. The remaining inputs if any are represented as do
not care terms. For such system specification
i) Write the truth table
ii) Give SOP and POS expressions
iii) Simplify the SOP expression using K-Map
iv) Implement the simplified expression using NAND gates.
b) The rain bow colors “VIBGYOR” are represented in binary form. Violet is represented as 10
‘000’, Indigo as ‘001’ and so on.. The output of the system is a ‘1’ if the color has the letter
‘O’ in it, otherwise it is ‘0’.The term ‘111’ is treated as do not care term. For this system,
i) Develop the truth table
ii) Give SOP and POS expression
iii) Do the K-map simplification
iv) Realize the simplified expression using NAND gates
c) Simplify the given Boolean expression using k-map. 5
ii) f2= ΠM (0,4,7,8,11) .dc (5,6,12,13)
UNIT – IV
7. a) With the help of truth table of a Full adder, derive an expression for its outputs and draw 8
the circuit diagram.
b) Realize a 1:4 DE-MUX using basic gates starting from its basic behavior in the truth table 8
form.
c) Analyze a 4-bit Ring counter using D-ffs. Furnish the shift table that demonstrates the 9
circulation of data ‘1100’. Estimate the time required to circulate the data if the clock
connected to it is 0.8µs
Page 2 of 3
 OR
8. a) Realize a 4:1 MUX using basic gates starting from its basic behavior in the truth table 8
form.
b) With the help of truth table of a Full subtractor, derive an expression for its outputs and 8
draw the circuit diagram.
c) Outline the Truth table, excitation table and characteristic equation of SR Flip Flop 6
d) Write the circuit of a 4-bit Johnson counter. How many clock cycles would be consumed 3
to repeat the pattern 1010?

***

Page 3 of 3
Exam Date & Time: 09-Jan-2023 (01:30 PM - 04:30 PM)

REVA UNIVERSITY

Analog and digital Electronics [B20EF0301]

Marks: 100 Duration: 180 mins.

UNIT I
Answer 1 out of 2 questions.

1 a Explain the features and working of Wien Bridge Oscillator with a circuit diagram. (10)

b Explain how diodes can be used as clippers and clampers with circuit diagrams. (10)

c Explain the principles of Oscillator and its operation. (5)

2 a Explain the features and working of Crystal Oscillator with a circuit diagram. (10)

b Explain the features and working of Phase Shift Oscillator with a circuit diagram. (10)

c Explain the functions of Tuned Oscillator circuits. (5)

UNIT II
Answer 1 out of 2 questions.

3 a Explain the characteristics of an Ideal Op Amp Model with a circuit diagram. (10)

b Explain in detail any 2 applications of Op Amp. (10)

c Define any 5 performance parameters for an Op Amp. (5)

4 a Explain the operation of high-pass filter with circuit diagram. (10)

b Explain the types of Phase Shifters with their operations. (10)

c Explain the features of an Instrumentation Amplifier. (5)

UNIT III
Answer 1 out of 2 questions.

5 a Explain the Sum-of-Products(SOP) and Product-of-Sum(POS) methods with its equation and logic (10)
circuit.

b (10)

c Explain how to convert from SOP to POS representation. (5)

6 a Using the Karnaugh map method obtain the minimal sum of the products and product of sums (10)
expressions for the functionF(A,B,C,D) = Σ (1, 5, 6, 7, 11, 12, 13, 15).

b Explain how we can draw and construct Karnaugh Maps for 3 and 4 variables with examples. (10)

c (5)

UNIT IV
Answer 1 out of 2 questions.

7 a Explain the design of Half Adder and Full Adder with its truth table and circuit diagrams. (10)

b Explain the working of RS Flip Flop with its logic diagram, truth table and characteristic equation. (10)
Page #1
 c Explain the design of a 4 bit Ring Counter. (5)

8 a Explain the design of Half Subtractor and Full Subtractor with its truth table and circuit diagrams. (10)

b Explain the working of JK Flip Flop with its logic diagram, truth table and characteristic equation. (10)

c Explain the design of a 4 bit Johnson Counter. (5)

-----End-----

Page #2
Exam Date & Time: 09-Jan-2023 (01:30 PM - 04:30 PM)

REVA UNIVERSITY

Analog and digital Electronics [B20EF0301]

Marks: 100 Duration: 180 mins.

UNIT I
Answer 1 out of 2 questions.

1 a Explain the features and working of Wien Bridge Oscillator with a circuit diagram. (10)

b Explain how diodes can be used as clippers and clampers with circuit diagrams. (10)

c Explain the principles of Oscillator and its operation. (5)

2 a Explain the features and working of Crystal Oscillator with a circuit diagram. (10)

b Explain the features and working of Phase Shift Oscillator with a circuit diagram. (10)

c Explain the functions of Tuned Oscillator circuits. (5)

UNIT II
Answer 1 out of 2 questions.

3 a Explain the characteristics of an Ideal Op Amp Model with a circuit diagram. (10)

b Explain in detail any 2 applications of Op Amp. (10)

c Define any 5 performance parameters for an Op Amp. (5)

4 a Explain the operation of high-pass filter with circuit diagram. (10)

b Explain the types of Phase Shifters with their operations. (10)

c Explain the features of an Instrumentation Amplifier. (5)

UNIT III
Answer 1 out of 2 questions.

5 a Explain the Sum-of-Products(SOP) and Product-of-Sum(POS) methods with its equation and logic (10)
circuit.

b (10)

c Explain how to convert from SOP to POS representation. (5)

6 a Using the Karnaugh map method obtain the minimal sum of the products and product of sums (10)
expressions for the functionF(A,B,C,D) = Σ (1, 5, 6, 7, 11, 12, 13, 15).

b Explain how we can draw and construct Karnaugh Maps for 3 and 4 variables with examples. (10)

c (5)

UNIT IV
Answer 1 out of 2 questions.

7 a Explain the design of Half Adder and Full Adder with its truth table and circuit diagrams. (10)

b Explain the working of RS Flip Flop with its logic diagram, truth table and characteristic equation. (10)
Page #1
 c Explain the design of a 4 bit Ring Counter. (5)

8 a Explain the design of Half Subtractor and Full Subtractor with its truth table and circuit diagrams. (10)

b Explain the working of JK Flip Flop with its logic diagram, truth table and characteristic equation. (10)

c Explain the design of a 4 bit Johnson Counter. (5)

-----End-----

Page #2
 REVA UNIVERSITY
School of Computer Science and Engineering
Sub: Analog and Digital Electronics (B22EF0304) AY: 2024-25 Sem: 03

Assignment – 2

1. With the help of a circuit diagram explain the functions of each component of CE amplifier
Draw its frequency response.
2. . Draw thw circuit of RC Coupled amplifier , elaborate on its frequency response and
applications
3. Draw the circuit of a RC phase shift Oscillator and give its expression for its frequency of
oscillations.
4. Design an RC phase shift oscillator to generate 5KHz sinusoidal Oscillations. The supply voltage
connected to the biasing circuit is +12V. Sketch the O/P waveform of the circuit.
5. Design a Colpitts oscillator that generates sinusoidal oscillations of 110KHz with an amplitude
of 12v.
6. List a few differences between an ideal and practical Operational amplifier. List the
characteristics of an ideal op-amp.
7. It is required to convert an alternating signal into pulsating DC during both the half cycles of the
i/p signal. Propose a suitable circuit that uses opamp to meet the requirement. With neat circuit
and waveforms, explain how the proposed circuit performs the job.
8. A transmitter transmits signals ranging from 20 HZ to 20 KHz. The receiver, receiving this
signal should remove frequency signals beyond 15 KHz and send for further processing. Suggest
a suitable opamp circuit and, design the circuit that removes the unwanted signals. Draw its
frequency indicating its roll off.
9. Design a first order active HPF having a cutoff frequency of 25 KHz and providing gain of 9.
Draw its frequency response indicating roll off.
10. A Temperature sensor o/p is connected to a transducer whose o/p is to be amplified and sent for
display. Propose a suitable circuit that uses an opamp to amplify. List all the characteristics of
the proposed circuit and give the expression for its o/p voltage.
11. Detail the behavior of circuits using opamp that produces an o/p that is proportional to
(i) Logarithmic and (ii) anti logarithmic of its i/p.
 SRN

3rd Semester [Link] CSE Semester End Examination January 2024

Course Title: Analog and Digital Electronics
Course Code: B20CS0301 - 85141
Time: 3 Hours Max. Marks: 100
Note:
1. Answer ONE FULL question from each unit.
2. Verify and ensure that question paper is completely printed before answering the question paper.
3. Any queries/discrepancies regarding the question paper, must be brought to the notice of the invigilator
4. Students must check the course title and course code before answering the question paper
UNIT – I Marks
1. a) Design a Wien bridge oscillator that generates a sinusoidal signal of 2KHz (Assume R or 10
C). Draw the circuit diagram of the oscillator indicating the designed component values
b) Design a colpitts oscillator that produces oscillations of 50KHz. Draw the circuit 10
indicating the designed values
c) Mention the classification of oscillators. 5
OR
2. a) State condition for Oscillations. Calculate the frequency of oscillations generated by RC 10
phase shift oscillator connected to RC networks wit R=10k and C=0.1uf. Draw the circuit
diagram of the oscillator indicating the given component values.
b) Outline the basic behavior of a clipping circuit. With a neat circuit diagram, sketch the 10
behavior of a series unbiased positive clamper built using ideal diodes.
c) Determine the frequency of oscillation generated by Hartley oscillator built with 5
L1=L2=1mh and C=1nF in the tank circuit.
UNIT – II
3. a) Outline the behavior of a peak detector built using opamp with a neat circuit diagram 9
and waveforms
b) Design a non-inverting amplifier using opamp to provide a voltage gain of 11. Sketch its 9
input and o/p waveforms for a 0.5v (peak) signal applied at its input.
c) Design a first order High pass active filter to have a cutoff frequency of 5.5KHz providing 7
a pass band gain of 9. Draw its frequency response indicating roll off.
OR
4. a) With a neat circuit diagram and waveforms illustrate the behavior of an absolute value 9
circuit built using opamp
b) Design a first order Low pass active filter to have a cutoff frequency of 3.5KHz providing 9
a pass band gain of 6. Draw its frequency response indicating roll off.
c) Outline the behavior of an Instrumentation amplifier with a neat circuit diagram. List its 7
requirements and give its o/p voltage equation
UNIT – III
5. a) a) A digital logic system accepts the phrase “AMYLOPECTINS” as input in four bit form 12
with A as ‘0000’, M as ‘0001’, Y as,‘0010’ and so on. The system produces an output of
‘0’ for all the vowels in the phrase and a ‘1’ for the others. Treat the unused inputs

Page 1 of 2
 ‘1100’ to ‘1111’ as don’t care. For the above system of 4 variables f (a, b, c, d) with
output Z, determine the following. (i) Truth table (ii) POS expression (iii) Simplified POS
expression using K-map (iv) Implementation of simplified expression using NAND gates
b) Design a 4:1 Multiplexer starting from its block diagram and Truth table. Implement the 7
design using basic gates.
c) Simplify the given Boolean expression using K-map and implement the simplified 6
expression using NOR gates. Y = f (a, b, c, d) = ∑m (0, 2, 6, 8, 10, 12) + dc (7,14,15)
OR
6. a) A digital logic system accepts the phrase “HYDROMAGNETIC” as input in four-bit form 12
with H as ‘0000’, Y as ‘0001’, D as ‘0010’, and so on. The system produces an output of
‘0’ for all the vowels in the phrase and a ‘1’ for the others. Treat the unused inputs
‘1101’ to ‘1111’ as don’t care. For the above system of 4 variables f (a, b, c, d) with
output Z, determine the following. (i) Truth table (ii) POS expression (iii) Simplified POS
expression using QM method (iv) Implementation of simplified expression using NAND
gates
b) Realize a Full Subtractor using a 3:8 decoder and give its appropriate Truth table. 7
c) Simplify the given Boolean expression using K-map. Implement the simplified expression 6
using Basic gates Y = f (a, b, c, d) = ∏M (0, 2, 5, 7, 8, 10, 11, 12, 14)
UNIT – IV
7. a) With the aid of a neat Logic diagram and Shift table, demonstrate the circulation of 4-bit 10
data ‘0110’ in a Ring counter built using SR-flip flops. Draw the timing diagram
embedding the above behavior.
b) Estimate the time required to circulate the data if the clock connected to it is 0.5µs in 5
the above register.
c) With a neat diagram, give the behavior of T flip flop in the form of truth table, 10
Characteristic equation, state transition diagram and excitation table.
OR
8. a) Analyze a 4-bit Johnson counter using D-ffs. Furnish the shift table that demonstrates the 10
circulation of data ‘1010’. Draw its timing diagram. Estimate the time required to
circulate the data if the clock connected to it is 5 MHz
b) With a neat Logic diagram and truth table outline the behavior of the Flip-flop that 10
eliminates race around. Derive an expression for its Characteristic equation. Draw its
State transition diagram.
c) Realize a 1:4 DE-MUX using basic gates starting from its basic behavior in the truth table 5
form.

***

Page 2 of 2
 SRN

3rd Semester [Link] CSE Semester End Examination January 2024

Course Title: Analog and Digital Electronics
Course Code: B20EF0301/ B21EF0301 – 85531/ 85551
Time: 3 Hours Max. Marks: 100
Note:
1. Answer ONE FULL question from each unit.
2. Verify and ensure that question paper is completely printed before answering the question paper.
3. Any queries/discrepancies regarding the question paper, must be brought to the notice of the invigilator
4. Students must check the course title and course code before answering the question paper
UNIT – I Marks
1. a) Explain the working of positive biased parallel clipper with aid of relevant circuit and 8
waveform.
b) Explain Barkhausen criteria for sustained oscillations. 5
c) Define Positive clamper with necessary diagram. 7
d) List different types of clippers. 5
OR
2. a) Discuss the working of Hartley oscillator with relevant circuit diagram and waveform. 8
b) In the Wien bridge oscillator circuit, if the RC network consists of resistors 200kΩ and 5
capacitors of 300pF, find its frequency of oscillation.
c) Contrast between Wein bridge oscillator and Phase shift oscillator 7
d) Explain Piezoelectric effect in oscillator operations. 5
UNIT – II
3. a) Identify the properties of an ideal Op amp and draw the equivalent circuit diagram of an Op 8
amp.
b) Explain Common Mode rejection Ration. 5
c) Discuss the first order low pass filter with necessary diagrams. 7
d) The differential voltage gain and CMRR of an Op amp when expressed in decibels are 110dB 5
and 100 dB, respectively. Apply the appropriate formula to obtain the common mode gain
expressed as a ratio.
OR
4. a) Describe the peak detector circuit using Op amp with necessary diagram. 8
b) Illustrate Virtual Ground in the context of Op amp. 5
c) Compare inverting and non-inverting Operational amplifier in details. 7
d ) Describe frequency of oscillations for RC phase shift oscillators. 5

Page 1 of 2
 UNIT – III
5. a) Find the Boolean algebra expression for the following system 8

b) Discuss the steps to minimize the following Boolean function using K-maps. 8
c) Discuss about 3 variable K-Map method with an example for minimizing Boolean functions. 9
OR
6. a) Write Boolean expression for the output of the below circuit and simply using Boolean laws 8

b) Minimize the following boolean function, 8

F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
c) Discuss about 4 variable K-Map method with an example for minimizing Boolean functions. 9
UNIT – IV
7. a) Outline the behavior of an edge-triggered SR-Flip-flop with the aid of a neat Logic diagram 8
and Truth table. Draw its state transition diagram.
b) Differentiate between Combinational circuit and Sequential circuit. 5
c) Describe the differences between a ring and a Switch tail counter. 7
d) Briefly discuss about the T flip-flop. 5
OR
8. a) Design a full adder starting from its truth table and block diagram. 8
b) Define Half Subtractor with a truth table. 5
c) Describe a flipflop which will eliminate the problem of racing. 7
d) Define (i) Clock (ii) Enable 5

***

Page 2 of 2
 SRN

3rd Semester [Link] CSE Semester End Examination January 2024

Course Title: Analog and Digital Electronics
Course Code: B22EF0304 - 22222308
Time: 3 Hours Max. Marks: 100
Note:
1. Answer ONE FULL question from each unit.
2. Verify and ensure that question paper is completely printed before answering the question paper.
3. Any queries/discrepancies regarding the question paper, must be brought to the notice of the invigilator
4. Students must check the course title and course code before answering the question paper
UNIT – I Marks
1. a) Outline the frequency response of CE amplifier, describing its amplifying behavior 7
b) Design a Wien bridge oscillator that generates a sinusoidal signal of 3 KHz (Assume R or 6
C). Draw the circuit diagram of the oscillator indicating the designed component values
c) A crystal has the following parameters: L=0.5H, Cs=0.06pF; Cp=1pF; R=5kΩ. Find the 6
series and parallel resonant frequencies
d) Draw the circuit of Hartley oscillator and give the expression for frequency of oscillations 6
OR
2. a) Outline the frequency response of RC coupled amplifier, describing its amplifying 7
behavior
b) Derive an expression for the transfer function of a positive feedback system and State the 6
conditions for oscillations.
c) Draw the circuit of RC Phase shift oscillator and give the expression for frequency of 6
oscillations
d) Design a Colpitts oscillator that produces oscillations of 1MHz. Draw the circuit indicating 6
the designed values. Assume an inductor of 1mH and feedback factor of 0.25
UNIT – II
3. a) Discuss the behavior of a peak detector built using op-amp with a neat circuit diagram 7
b) A first order inverting active High pass filter has a pass band gain of 2 and a cutoff 8
frequency of 1 kHz. If input capacitor has a value of 10nF. Calculate the value of the
resistors used in the circuit. Draw the circuit indicating the component values.
c) Suggest an Opamp circuit used in Industrial applications to amplify the signals produced 10
by the Transducers. List the characteristics of the suggested Amplifier circuit and give its
implementation. What is the expression for its output voltage?
OR
4. a) With a neat circuit diagram and waveforms illustrate the behavior of an Absolute value 7
circuit built using op-amp
b) Design a first order Active Low pass filter for a cut-off frequency of 159Hz and input 6
impedance of 10Kohms The pass band gain of the filter should be 10. What is its Roll-off?
c) Identify the circuit detecting zero crossing of the input signal. Explain the working of the 5
identified circuit with waveforms
d) It is desired to build a circuit that produces an output proportional to Logarithmic of its 7

Page 1 of 3
 input voltage. Propose a suitable circuit using Opamp that performs the required task.
Draw the circuit and derive an expression for its output voltage
UNIT – III
5. a) A digital system is to be designed in which the months of the year is given as input in 4-bit 10
form. The month January is represented as ‘0000’, February as ‘0001’ and so on. The
output of the system is ‘1’ corresponding to the input of the month containing 30 days or
less otherwise it is ‘0’. Consider the excess number in the input beyond ‘1011’ as don’t
care conditions. For this systems of 4 variables (A, B, C, D) determine the following.
i) Truth table
ii) SOP expression
iii) Simplify SOP expression using K-Map.
iv) Implement the simplified expression using NOR-NOR gates

b) Obtain the essential Prime Implicants using Quine Mc Clusky method and give the NAND 10
implementation for the reduced expression.
Y = Σm(0,1,2,3,10,11,12,13,14,15)
c) Simplify the given Logical expression using K-map and implement the simplified 5
expression using Only NAND gates
Y = ∑m(0, 2, 3) + don’t care(4, 7)
OR
6. a) The rain bow colors “VIBGYOR” are represented in binary form. Violet is represented as 10
‘000’, Indigo as ‘001’ and so on.. The output of the system is a ‘1’ if the color has the
letter ‘O’ in it, otherwise it is ‘0’.The term ‘111’ is treated as do not care term. For this
system,
i) Develop the truth table
ii) Give SOP and POS expression
iii) Do the K-map simplification
iv) Realize the simplified expression using NAND gates
b) The system has four inputs. The output will be high only when the majority of the inputs 10
(more than two bits) are high. Find the following
i) Truth table
ii) Boolean expression in Σm and ΠM forms
Simplified SOP expression using Quine Mc Clusky method
c) Simplify the following Boolean expression using K map 5
. F1= ΠM (0,1,2,3,6,9,11,13).dc (7,15)
UNIT – IV
7. a) Realize a Full Subtractor using a 3:8 decoder and give its appropriate Truth table. 6
b) Design a 8: 1 Multiplexer solution for the Boolean function 8
Y = ∑m(0,2,3,4,5,8,9,10,11,12,13,15) using VEM technique
c) Determine the characteristic equation, excitation table and state transition diagram of 6
Data flip flop giving its truth table

d) With a neat logic diagram, shift table, and timing diagram, demonstrate the circulation of 5
4-bit data ‘0011’ in a switch tail counter.

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 OR
8. a) Realize a 4:1 MUX using basic gates starting from its basic behavior in the truth table 8
form. Design a 4: 1 MUX using 2:1 MUX
b) Outline the Truth table, excitation table and characteristic equation of SR Flip Flop 6
c) With the aid of a neat Truth table, implement an Octal to binary Encoder using basic gates 5
d) With the aid of a neat Logic diagram and Shift table, demonstrate the circulation of 4-bit 6
data ‘0100’ in a Ring counter built using D-flip flops. Draw the timing diagram embedding
the above behavior.

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 SRN

3rd Semester [Link] CSE Semester End Examination January 2024

Course Title: Digital Logic and Design
Course Code: B22EH0301 - 22122308
Time: 3 Hours Max. Marks: 100
Note:
1. Answer ONE FULL question from each unit.
2. Verify and ensure that question paper is completely printed before answering the question paper.
3. Any queries/discrepancies regarding the question paper, must be brought to the notice of the invigilator
4. Students must check the course title and course code before answering the question paper
UNIT – I Marks
1. a) With k map being a method of simplification, apply k-map to simply the following 10
expressions
i) F=Σ m (0,1,2,5,8,9,10 ) ---get the simplified POS expression
ii) F=Σ m (0,1,2,4,5,6,8,9,12,13,14) ---get the simplified SOP expression
b) For a four variable input device is designed to output a logic high for all the even numbers 10
and logic low for all the odd numbers (zero,a even number).
i) Design the truth table
ii) Using K map obtain a simplified SOP expression
iii) Build the circuit for the simplified expression using NOR gate
c) Implement the function Σ m (0,6,7) using NAND gates and function Π M(1,5) using NOR 5
gate
OR
2. a) Simplify the below expressio using K-map 10
i) F=Σ m (7,8,9 ) +dc(10,11,12,13,14,15)
ii) F=(A’+B’+C+D)+(A+B’+C+D)+(A+B+C+D’)+(A+B+C’+D’)(A’+B+C+D’)(A+B+C’+D)
b) Using QM method simplify the expression 10
F=Σ m (0,1,3,7,8,9,11,15 )
c) i) Convert the following Boolean expression into standard SOP form: AB’C + A’B’ + ABC’D 5
ii) Convert the following Boolean expression into standard POS form:
(A’+B+C)(B’+C+D’)(A+B’+C’+D)
UNIT – II
3. a) Combinational logic circuits are the helpful data processing circuits explain the below two 10
circuits with required truth table, circuit and expression and explanation
i) Full Adder Circuit
ii) BCD Adder Circuit
b) With a block diagram explain the working of a multiplexer 10
i) Realize the expression Y=A’B +BC’ using 4:1 multiplexer
ii) Build a 32:1 Multiplexer using 2 16:1 mux and others if required
c) Explain What are Decoders ?Using a 3*8 decoder build a full subtractor circuit 5

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 OR
4. a) Illustrate a 10
i) Decimal to BCD encoder with truth table and appropriate circuit
ii) Full Subtractor
b) Adder /subtractor circuit is a circuit which performs both Addition and Subtraction with 10
the value being changed on a single line. Explain the circuit with a neat diagram and an
example.
c) Explain Demux with an example of 1:4 demultipleer 5
UNIT – III
5. a) Explain the working of JK flip-flop with its circuit diagram. Write its 10
i. Truth table
ii. Characteristic table
iii. Excitation table
iv. State transition diagram
b) Shift registers have either serial or parallel entry and exit of data, considering this explain 10
four types of shift register
c) Give the state transition diagram of D and T flip flop 5
OR
6. a) Explain the working of MS-JK flip flop with its circuit diagram. Write its 10
i. Truth table
ii. Characteristic table
iii. Excitation table
iv. State transition diagram
b) Show how a SR flip flop can be converted into D flip flop also explain D flip-flop 10
c) Explain the working of 4-bit Johnson counter with a neat circuit diagram and its working 5
UNIT – IV
7. a) Draw the state transition diagram and ASM chart for the sequence detector circuit that 15
detects the sequence 110 using both Moore and mealy model .Assume the bits enter
from left i.e the first bit to be identified is 0 second 1 and third bit 1 from the input
sequence.
b) Explain a 3 bit binary ripple up counter constructed using negative edge triggered JK flip 5
flops with a neat diagram and truth table.
c) Explain Moore and Mealy model of sequential logic design system 5
OR
8. a) Implement Moore model design for a sequence detector that receives binary data stream 15
at its input X and signals when a combination 011 arrives at the input by making its
output Y high, which otherwise remains low. Consider data is coming from left, i.e the
first bit to be identified is 1 second 1 and third bit 0 from the input sequence.
b) Illustrate the working of a 3 bit binary down counter with a neat diagram, waveforms and 5
count table
c) Synchronous sequential logic circuit can be designed using two distinct models. Outline 5
the working of a Moore and Mealy model of sequential logic design system

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