23ECE211- Microcontrollers and Interfacing

Lecture 4

Dr. Sreenidhi P R, Anjana G

Assistant Professors,
Department of Electronics and Communication Engineering, Amrita
Vishwa Vidyapeetham
February 1, 2026

1
Architectural Inheritance
RISC Precedents- Historical Context
At the time the first ARM chip was designed, the only examples of RISC
architectures were:

• Berkeley RISC I and II

• Stanford MIPS (Microprocessor without Interlocking
Pipeline Stages)
Earlier Machines with RISC Characteristics:
• Digital PDP-8
• Cray-1
• IBM 801
Note
These earlier machines predated the RISC concept but shared
many characteristics that later came to be associated with
RISCs. 2
Features Used from Berkeley RISC
Adopted Features
The ARM architecture incorporated several key features from Berkeley RISC
design:

1. Load-Store Architecture
• Only load and store instructions access memory
• All other operations work on registers
• Clean separation of memory and computation
2. Fixed-Length 32-bit Instructions
• Simplifies instruction decode
• Enables efficient pipelining
• Predictable instruction fetch
3. 3-Address Instruction Formats
• Two source operands, one destination
• All independently specified
• Maximum flexibility
3
Features Rejected: 1. Register Windows
Berkeley RISC Feature Not Adopted
Register Windows - A key Berkeley RISC feature that ARM designers chose
to reject.

How Register Windows Work:

• Register banks on Berkeley RISC had large number of
registers (32)
• Only 32 visible at any time
• Procedure entry and exit instructions move visible
”window”
• Gives each procedure access to new registers
• Reduces data traffic between processor and memory
• Reduces register saving and restoring overhead

4
Why ARM Rejected This:

• Large chip area occupied by large number of registers

• Feature was rejected on cost grounds
• Shadow registers for exceptions retained the concept

ARM’s Approach
ARM uses banked registers for different processor modes instead of register
windows. This provides mode-specific context without the overhead of full
register windows.

5
Features Rejected: 2. Delayed Branches

Berkeley RISC Feature Not Adopted

Delayed Branches - Another Berkeley RISC feature rejected by ARM
designers.

How Delayed Branches Work:

• Branches cause pipeline problems
• Interrupt smooth flow of instructions
• Most RISC processors ameliorate problem using delayed
branches
• Branch takes effect after the following instruction has
executed

6
Problem with Delayed Branches:

• Remove atomicity of individual instructions

• Work well on single issue pipelined processors
• Do not scale well to super-scalar implementations
• Can interact badly with branch prediction mechanisms
Why ARM Rejected Delayed Branches
Long-term Thinking
On the original ARM, delayed branches were not used because they made
exception handling more complex.

7
Wise Decision
In the long run this has turned out to be a good decision since it simplifies
re-implementing the architecture with a different pipeline.

Benefits of This Decision:

• Simpler exception handling
• Easier to implement different pipeline depths
• Better compatibility across ARM versions
• More flexible for future enhancements
• Supports branch prediction better

8
Features Rejected:3. Single-Cycle Execution
Not All Instructions Single-Cycle
Although ARM executes most data processing instructions in a single clock
cycle, many other instructions take multiple clock cycles.

The Rationale:
• With single memory for both data and instructions
• Even a simple load or store instruction requires at least
two memory accesses
• One for the instruction
• One for the data
ARM’s Approach
Single cycle operation of all instructions is only possible with separate data
and instruction memories, which were considered too expensive for
intended ARM application areas.

9
Optimizing Memory Access
Design Philosophy
Instead of single-cycle execution of all instructions, ARM was designed to
use the minimum number of cycles required for memory accesses.

Strategy:
• Where this was greater than one, extra cycles used where
possible
• Support useful features like auto-indexing addressing modes
• Reduces total number of ARM instructions required
• Improves performance and code density
Example: Array Processing
Auto-indexing allows pointer increment during load/store
operation, eliminating separate increment instruction and
improving both speed and code size.
10
Simplicity - Core Design Principle

Overriding Concern
An overriding concern of the original ARM design team was the need to
keep the design simple.

Team Background:
• First ARM was an Acorn designers’ first serious VLSI
project
• Acorn designers had experience only of gate arrays
• Complexities up to around 2,000 gates
• Full-custom CMOS design medium approached with respect

11
Where Simplicity Shows
Hardware vs. Software
The simplicity of the ARM may be more apparent in hardware
organization and implementation than in the instruction set architecture.

From Programmer’s Perspective:

• Perhaps more visible as conservatism in ARM instruction set
• Accepting fundamental precepts of RISC approach
• Less radical than many subsequent RISC designs
Hybrid Approach
The combination of simple hardware with an instruction set that
is grounded in RISC ideas but retains a few key CISC features,
thereby achieves significantly better code density than a pure
RISC, has given the ARM its power-efficiency and its small core
size.
12
The ARM Programmer’s Model
What is Programmer’s Model?
A processor’s instruction set defines the operations that the programmer can
use to change the state of the system incorporating the processor.

• This state is usually comprises the Values of data items in

processor’s visible registers and system memory.
Key Concept:
• Each instruction performs a defined transformation from
the state before the instruction is executed to state after it
has completed
• Processor has many invisible registers
• Values of invisible registers before and after are instruction
execution arenot significant
• Only visible registers have significance
13
ARM Visible Registers Overview
Register Organization
When writing user-level programs, only the 15 general-purpose 32-bit
registers (r0 to r14), the program counter (r15), and the current program
status register (CPSR) need be considered.

Register Categories:
1. General-Purpose Registers: r0 - r14
2. Program Counter: r15 (PC)
3. Status Register: CPSR
Additional Registers
The remaining registers are used only for:
• System-level programming
• Handling exceptions (interrupts, etc.)
14
ARM Register Organization Diagram

Complete Register Set Visualization

ARM has 37 total registers organized with mode-specific banking for
efficient context switching and exception handling.
15
Complete ARM Register Set
1. User Mode Accessible (17 registers):
• r0-r14: 15 general-purpose 32-bit registers
• r15 (PC): Program Counter
• CPSR: Current Program Status Register
[Link] Registers in FIQ Mode:
• r8 fiq through r12 fiq: 5 banked registers
• r13 fiq (SP fiq): FIQ Stack Pointer
• r14 fiq (LR fiq): FIQ Link Register
• SPSR fiq: Saved Program Status Register for FIQ

FIQ Advantage
FIQ mode has 7 banked registers (r8-r14) enabling fast interrupt handling
without stack operations.

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Complete ARM Register Set (Contd..)
3. Banked Registers in Other Modes:
Mode Banked SP (r13) Banked LR (r14)
Supervisor r13 svc (SP svc) r14 svc (LR svc)
Abort r13 abt (SP abt) r14 abt (LR abt)
IRQ r13 irq (SP irq) r14 irq (LR irq)
Undefined r13 und (SP und) r14 und (LR und)
4. Saved Program Status Registers (SPSR):
• SPSR svc: Supervisor mode SPSR
• SPSR abt: Abort mode SPSR
• SPSR irq: IRQ mode SPSR
• SPSR und: Undefined instruction mode SPSR
• SPSR fiq: FIQ mode SPSR
Total Count: 37 Registers
31 general-purpose + 1 PC + 1 CPSR + 5 SPSR = 37 registers 17
General-Purpose Registers (r0-r14)
Characteristics
All general-purpose registers are 32-bit wide and can hold:
• Data values
• Memory addresses
• No special hardware distinction between them

Register Typical Usage Explanation

r0-r3 Argument & Result Registers (Scratch)
• Used to pass parameters to functions (1st to 4th ar-
gument)
• r0 holds the return value from a function
• Can be freely modified - no need to preserve
• Example: ADD r0, r1, r2 uses r1, r2 as inputs, r0
for output
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Register Typical Usage Explanation
r4-r11 Variable Registers (Preserved)
• Used for local variables that need to survive across
function calls
• If a function uses these, it MUST save them first
(push to stack)
• Must restore original values before returning (pop
from stack)
• ”Callee-saved” = the called function is responsible
for preserving them
r12 (IP) Intra-Procedure Call Scratch (Temporary)
• IP = Intra-Procedure-call scratch register
• Used by linker for long jumps between functions (ve-
neers)
• Can be corrupted during function calls
• Don’t use it to store important values across function
calls
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Register Typical Usage Explanation
r13 (SP) Stack Pointer
• Points to the current top of the stack in memory
• Automatically updated by PUSH/POP and
STMFD/LDMFD instructions
• Used for storing local variables, saving registers,
return addresses
• Must always point to a valid stack location
r14 (LR) Link Register (Return Address)
• Automatically stores the return address stores the re-
turn address during function calls( when BL (Branch
with Link) is called)
• Contains the address to return to after function com-
pletes
• Simple leaf functions: just do MOV PC, LR to return
• Nested functions: must save LR to stack first

20
Stack Pointer (r13/SP)
Key Characteristics:
• Auto-updates with PUSH/POP operations
• Different SP for each processor mode
• Allows each mode to have separate stack
• Critical for exception handling
Banked SP Registers
• SP usr (User and System modes)
• SP fiq (Fast Interrupt mode)
• SP irq (Normal Interrupt mode)
• SP svc (Supervisor mode)
• SP abt (Abort mode)
• SP und (Undefined mode)

21
Link Register (r14/LR)
Operation:
• Automatically loaded by BL (Branch with Link) instruction
• BL copies (PC + 4) into LR before branching
• Return using: MOV PC, LR or BX LR
Banked LR:
• Like SP, each processor mode has its own LR
• Exception handlers can use LR without corrupting user’s
return address
• Critical for nested exception handling

Nested Calls
For nested function calls, LR must be saved to stack before
calling another function, as there is only one LR per mode.

22
Program Counter (r15/PC)
Purpose
The Program Counter (r15/PC) points to the current instruction address
being fetched.

Key Characteristics:
• Auto-increments by 4 for each 32-bit instruction
• Auto-increments by 2 for each 16-bit Thumb instruction
• Can be read like any other register
• Writing to PC changes program flow (branch)
Pipeline Effect - Critical! : Due to ARM’s 3-stage pipeline:
• Reading PC gives address of current instruction + 8 (ARM mode)
• Reading PC gives address of current instruction + 4 (Thumb mode)
• PC points to instruction being fetched, not executed

23
Current Program Status Register (CPSR)

Condition Flags [31:28]: Control Bits [7:0]:

• N: Negative (bit 31) • I: IRQ disable (bit 7)

• Z: Zero (bit 30) • F: FIQ disable (bit 6)

• C: Carry (bit 29) • T: Thumb state (bit 5)

• V: Overflow (bit 28) • Mode[4:0]: Processor

mode

Purpose
The CPSR stores condition codes and controls processor state and operating
mode.

24
CPSR Condition Flags - Detailed

Flag Description
N Negative: Set when result of operation is negative (bit 31 of
result = 1). Used for signed comparisons.
Z Zero: Set when result of operation is zero (all bits = 0). Used
for equality tests.
C Carry: Set when operation generates carry-out (unsigned
overflow) or borrow. Also set by shift operations.
V Overflow: Set when operation generates signed overflow (re-
sult doesn’t fit in sign bit representation).
Important Notes
• Not all instructions update flags
• Use ’S’ suffix to update flags: ADDS, SUBS, etc.
• CMP, CMN, TST, TEQ always update flags
• Conditional execution tests these flags 25
CPSR Control Bits

Bit Description
I IRQ Disable: When set (1), normal interrupts (IRQ)
are masked and will not be processed.
F FIQ Disable: When set (1), fast interrupts (FIQ) are
masked and will not be processed.
T Thumb State: When set (1), processor executes
Thumb (16-bit) instructions. When clear (0), executes
ARM (32-bit) instructions.
Mode[4:0] Processor Mode: 5 bits define current operating mode
(User, FIQ, IRQ, Supervisor, Abort, Undefined, Sys-
tem).
Privilege Levels Only privileged modes (not User mode) can
modify control bits directly. This protects system integrity.
26
Processor Modes
Mode Code Type Entry Condition
User 10000 Non-privileged Normal program execution
FIQ 10001 Exception Fast Interrupt Request
IRQ 10010 Exception Normal Interrupt Request
Supervisor 10011 Privileged Reset or Software Interrupt
(SWI)
Abort 10111 Exception Data or Prefetch Abort
Undefined 11011 Exception Undefined instruction
System 11111 Privileged Privileged user mode

Mode Categories
• User: Normal application code (non-privileged)
• System: Privileged tasks (OS) with user registers
• Exception Modes: FIQ, IRQ, Supervisor, Abort, Undefined
27
ARM Exceptions Overview

Exception Types
The ARM architecture supports a range of interrupts, traps and supervisor
calls, all grouped under the general heading of exceptions.

General Exception Handling:

1. Current state of PC ,CPSR need to be stored
2. Processor operating mode to be changed to appropriate
exception mode
3. PC forced to value depending on exception type

28
Saved Program Status Register (SPSR)
Purpose
SPSRs are used in ARM architecture to save the current program status
when switching to an exception mode.
- Preserve flags: Save flags (e.g., N, Z, C, V) and mode bits.
- Enable nesting: Allow nested exceptions without losing track of previous
state.
- Efficient context switch: Quickly save and restore processor state.

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SPSR contd...

• SPSR svc: Supervisor mode SPSR

• SPSR abt: Abort mode SPSR
• SPSR irq: IRQ mode SPSR
• SPSR und: Undefined instruction mode SPSR
• SPSR fiq: FIQ mode SPSR

30
Banked Registers by Mode - Part 1
Register Banking Concept
Each processor mode has its own copy of certain registers, enabling fast
context switching without explicit save/restore operations.

Register User System FIQ IRQ Svc Abt Und

r0-r7 Same physical registers across all modes

r8 r8 r8 r8 fiq r8 r8 r8 r8
r9 r9 r9 r9 fiq r9 r9 r9 r9
r10 r10 r10 r10 fiq r10 r10 r10 r10
r11 r11 r11 r11 fiq r11 r11 r11 r11
r12 r12 r12 r12 fiq r12 r12 r12 r12

Note on r8-r12
Only FIQ mode has banked versions of r8-r12. All other modes
share the same physical registers r8-r12 with User mode.

31
Banked Registers by Mode - Part 2
Register User System FIQ IRQ Svc Abt Und

r13 (SP) SP SP SP fiq SP irq SP svc SP abt SP und

r14 (LR) LR LR LR fiq LR irq LR svc LR abt LR und
r15 (PC) Same physical register across all modes
CPSR Same physical register across all modes
SPSR - - SPSR fiq SPSR irq SPSR svc SPSR abt SPSR und

Banking Benefits
• Fast context switching: No explicit save/restore of SP and LR needed
• Exception isolation: Each mode has separate stack (via banked SP)
• FIQ optimization: 7 banked registers (r8-r14) enable handling
without stack access
• SPSR preservation: Automatic CPSR save on exception entry

32
Memory System Organization
Address Space
An ARM system has memory state. Memory may be viewed as a linear array
of bytes numbered from zero up to 232 − 1.

Data Types:
• Byte: 8 bits
• Half-word: 16 bits
(aligned on even
boundaries)
• Word: 32 bits
(aligned on 4-byte
boundaries)

33
Memory Alignment - Part 1

Alignment Requirements
Data items must be aligned on their natural boundaries:

• Words (32-bit): Must start at addresses divisible by 4

(two least significant address bits are zero)
• Half-words (16-bit): Must start at even addresses (least
significant address bit is zero)
• Bytes (8-bit): No alignment restriction (any address)

34
Memory Alignment - Part 2

Valid Addresses
• Word: 0x00, 0x04, 0x08, 0x0C, 0x10, ...
• Half-word: 0x00, 0x02, 0x04, 0x06, 0x08, ...
• Byte: 0x00, 0x01, 0x02, 0x03, 0x04, ...

Misaligned Access
Accessing misaligned data can cause exceptions or unpredictable
behavior depending on ARM implementation.

35
Memory dump from ARM

First line : 0x00000000: 10 10 A0 E3 2A 20 A0 E3 02 00 81 E0

3B 30 A0 E3
Address Byte
0x00000000 → 10
0x00000001 → 10
0x00000002 → A0
0x00000003 → E3
Disassembly: 0x00000000 E3A01010 MOV R1,#0x00000010
MOV R1, #16
E3A0 → opcode for MOV immediate 36
1010 → immediate value (16) + destination register
Endianness - Byte Ordering in Memory
What is Endianness?
Endianness defines the order in which multi-byte data is stored in memory.

The Problem:
• A 32-bit word (0x12345678) occupies 4 bytes in memory
• But which byte goes in which address?
• Two different conventions exist!

Big-Endian Little-Endian
”Most significant byte first” ”Least significant byte first”
• Stores MSB at lowest address • Stores LSB at lowest address
• Human-readable order • Hardware-efficient
• Used by: Motorola, SPARC, • Used by: Intel x86, ARM
Network protocols (default)
37
Big-Endian vs Little-Endian - Visual Example
Storing 32-bit Value: 0x12345678

Memory Representation:
Big-Endian Little-Endian
(Most Significant Byte First) (Least Significant Byte First)
Address Address
0x1000 12 MSB 0x1000 78 LSB
0x1001 34 0x1001 56
0x1002 56 0x1002 34
0x1003 78 LSB 0x1003 12 MSB

Key Observation: Byte order is reversed between the two

formats!

38
ARM-Little endian: eg

Address Byte
0x00000000 → 10
0x00000001 → 10
0x00000002 → A0
0x00000003 → E3
Disassembly: 0x00000000 E3A01010 MOV R1,#0x00000010
MOV R1, #16
E3A0 → opcode for MOV immediate 1010 → immediate value
(16) + destination register

39
Endianness
Byte Ordering
ARM supports both little-endian and big-endian memory organizations.

Standard: Little-Endian
• Least significant byte at lowest address
• Most common ARM configuration
• Compatible with x86 systems

Configuration
Endianness can be configured in ARM
(implementation-dependent), but is typically set at power-up
and remains fixed.

40
Load-Store Architecture
Fundamental Principle
In common with most RISC processors, ARM employs a load-store
architecture.

What This Means: Memory Access:

• Instruction set only • Only operations applying
process (add, subtract, to memory are those that
etc.) values in registers copy memory values into
• Must specify values registers (load
directly within instruction instructions)
itself (immediates) • Or copy register values into
• Results always placed into memory (store
registers instructions)
• ARM does not support
such ’memory-to-memory’ 41
ARM Instruction Categories - Part 1

Three Main Categories

ARM instructions fall into one of the following three categories:

1. Data Processing Instructions

• Use and change only register values
• Examples: ADD, SUB, AND, ORR, MOV, CMP
2. Data Transfer Instructions
• Copy memory values into registers (load)
• Copy register values into memory (store)
• Additional form: exchange a memory value with a register
value

42
ARM Instruction Categories - Contd..
3. Control Flow Instructions
• Normal execution uses consecutive memory addresses
• Control flow instructions cause execution to switch to
different address
• Either permanently (branch instructions)
• Or saving return address (branch and link instructions)
• Or trapping into system code (supervisor calls)

Summary
These three categories cover all ARM instruction operations:
processing data in registers, transferring data between memory
and registers, and controlling program flow.

43
Supervisor Mode
Protected Operating Mode
The ARM processor supports a protected supervisor mode.

Protection Mechanism:
• Ensures user code cannot gain supervisor privileges without
appropriate checks
• Ensures code is not attempting illegal operations
Privileged Operations:
• System-level functions accessed through specified supervisor
calls
• Generally include:
• Accesses to hardware peripheral registers
• Widely used operations such as character input and output

44
User vs. Supervisor Programming - Part 1
User-Level Programmers
User-level programmers are principally concerned with devising algorithms to
operate on data ’owned’ by their programs.

User-Level Concerns:
• Algorithm design and implementation
• Data structures and manipulation
• Rely on operating system for external interactions

User Mode Characteristics

• Non-privileged execution
• Cannot directly access hardware
• Limited access to system resources
• Safe, isolated environment 45
User vs. Supervisor Programming - Part 2
System-Level Programming
Operating system handles all transactions with world outside their programs.

System-Level Functions:
• Hardware peripheral access
• Interrupt handling
• Memory management
• Process scheduling
• Resource allocation
Supervisor Mode Characteristics
• Privileged execution
• Full hardware access
• Complete system control
• Responsible for system stability and security 46
ARM Instruction Set Features
Key Characteristics
All ARM instructions are 32 bits wide (except compressed 16-bit Thumb
instructions) and aligned on 4-byte boundaries in memory.

Core Features:
1. Load-Store Architecture
• Only LDR/STR access memory
• All data processing uses registers
2. 3-Address Data Processing Instructions
• Two source operand registers
• Result register
• All independently specified
• Example: ADD r0, r1, r2
3. Conditional Execution of Every Instruction
• 16 condition codes (EQ, NE, GT, etc.)
• Eliminates many branch instructions
• Improves pipeline efficiency 47
ARM Instruction Set Features (Contd...)

Advanced Features:
4. Powerful Load and Store Multiple Register
Instructions
• LDM/STM transfer up to 16 registers
• Efficient context save/restore
• Stack operations (PUSH/POP)
5. Single-Cycle Shift and ALU Operation
• Shift operation combined with ALU in single instruction
• Executes in single clock cycle
• Example: ADD r0, r1, r2, LSL #2

48
Instruction Set Features (Contd...)
Additional Features:
6. Open Instruction Set Extension
• Through coprocessor instruction set
• Adding new registers and data types
7. Very Dense 16-bit Compressed Representation
• Thumb architecture
• Approximately 65% of 32-bit code size
• Useful for memory-constrained systems

Code Density vs. Performance

ARM instruction set may appear to have rather more formats
than other commercial RISC processors. While this leads to
more complex instruction decoding, it also leads to much better
code density.

49
Code Density Advantage
Performance Trade-off
For the same embedded systems that most ARM processors are used in, this
code density advantage outweighs the small performance penalty incurred by
the decode complexity.

Benefits:
• Smaller memory footprint
• Reduced memory costs
• Better cache utilization
• Lower power consumption (fewer memory accesses)
Thumb Extension
Thumb code extends this advantage to give ARM better code
density than most CISC processors, while maintaining RISC-like
performance and efficiency.
50
I/O System
Memory-Mapped I/O
The ARM handles I/O (input/output) peripherals (such as disk controllers,
network interfaces, etc.) as memory-mapped devices with interrupt
support.

How It Works:
• Internal registers in devices appear as addressable locations
within ARM’s memory map
• May be read and written using same (load-store)
instructions as any other memory locations
Interrupt Handling:
• Peripherals attract processor’s attention by making
interrupt request
• Using either normal interrupt (IRQ)
• Or fast interrupt (FIQ) input
51
Interrupt Sources
Interrupt Inputs
Both interrupt inputs are level-sensitive and maskable.

Characteristics:
• Normally most interrupt sources share the IRQ input
• Just one or two time-critical sources connected to
higher-priority FIQ input
DMA Support
Some systems may include direct memory access (DMA)
hardware external to the processor to handle high-bandwidth
I/O traffic.

Exception Form:
• Interrupts are a form of exception
• Handled as outlined in exception handling mechanism 52
ARM Exceptions Overview
Exception Types
The ARM architecture supports a range of interrupts, traps and supervisor
calls, all grouped under the general heading of exceptions.

General Exception Handling:

1. Current state saved by copying PC into r14 exc
2. CPSR copied into SPSR exc (where exc stands for
exception type)
3. Processor operating mode changed to appropriate exception
mode
4. PC forced to value between 0x00 and 0x1C (the vector
address)
• Particular value depends on exception type

53
Vector Table
The instruction at the location the PC is forced to (vector address) will
usually contain a branch to the exception handler.

Exception Vector Table

Address Exception Type Mode
0x00 Reset Supervisor
0x04 Undefined Instruction Undefined
0x08 Software Interrupt (SWI) Supervisor
0x0C Prefetch Abort Abort
0x10 Data Abort Abort
0x14 Reserved -
0x18 IRQ (Normal Interrupt) IRQ
0x1C FIQ (Fast Interrupt) FIQ
Each vector location typically contains:Branch instruction to
actual exception handler Or LDR instruction to load handler
address from nearby location 54
Exception Handler Operation
Handler Responsibilities
The exception handler will use r14 exc, which will normally have been
initialized to point to a dedicated stack in memory, to save some user
registers for use as work registers.

Return from Exception:

1. Restore user registers
2. Use instruction to restore PC and CPSR atomically
3. May involve adjustment of PC value saved in r14 exc
• Compensates for state of pipeline when exception arose

Pipeline Compensation
This adjustment is necessary because PC is always ahead of the executing
instruction by 8 bytes (ARM mode) or 4 bytes (Thumb mode) due to
pipelining.

55
Exception Entry Example
What Happens on IRQ
1. Current PC value copied to LR irq
2. CPSR copied to SPSR irq
3. CPSR mode bits set to IRQ mode (10010)
4. CPSR I bit set to disable further IRQs
5. PC loaded with 0x18 (IRQ vector address)
6. Instruction at 0x18 executed (typically: B irq handler)
7. IRQ handler executes:
• Saves registers to IRQ stack
• Determines interrupt source
• Services the interrupt
• Restores registers
• Returns: SUBS PC, LR, #4 (restores PC and CPSR)

56
FIQ - Fast Interrupt
Why FIQ is ”Fast”
FIQ has several features making it faster than IRQ:

1. Higher Priority
• FIQ vector at 0x1C (end of vector table)
• Handler can be placed directly at 0x1C
• No branch needed (saves cycles)
2. Additional Banked Registers
• FIQ mode has r8 fiq through r12 fiq
• Total of 7 banked registers (r8-r14)
• Often enough without saving to stack
• Faster entry and exit
3. Separate Disable Bit
• Can disable FIQ independently (F bit)
• FIQ can interrupt IRQ handler
• IRQ cannot interrupt FIQ handler
57
Key Takeaways - History

• ARM originated at Acorn Computers (1983-1985)

• Born from need for BBC Micro successor
• Small team achieved breakthrough design
• Inspired by Berkeley RISC research
• Adopted load-store architecture, fixed 32-bit instructions,
3-address format
• Rejected register windows and delayed branches
• Optimized for simplicity and efficiency
• Became foundation of modern embedded processors

Summary 58
Key Takeaways - Programmer’s Model
• 37 Total Registers: 31 general-purpose, 1 PC, 1 CPSR, 5
SPSR
• 16 Visible in User Mode: r0-r14, PC, CPSR
• Banked Registers: Each mode has own SP, LR, SPSR
• CPSR: N, Z, C, V flags + I, F, T bits + Mode[4:0]
• 7 Processor Modes: User, System, FIQ, IRQ, Supervisor,
Abort, Undefined
• Load-Store Architecture: Only LDR/STR access memory
• Memory: Byte, half-word, word with alignment
requirements
• Exceptions: 8 vectors at 0x00-0x1C with mode switching

Summary 59
Key Takeaways - Architectural Features

• Fixed 32-bit instructions (ARM mode), 16-bit (Thumb

mode)
• 3-address instruction format - maximum flexibility
• Conditional execution of every instruction
• Powerful load/store multiple register instructions
• Single-cycle shift + ALU operation
• Memory-mapped I/O with interrupt support
• Better code density than pure RISC
• Simple hardware with efficient implementation

Summary 60
Programming Model Best Practices
1. Follow Register Conventions
• r0-r3 for arguments/return values
• r4-r11 callee-saved (preserve in functions)
• r13 as stack pointer (don’t corrupt!)
2. Understand Pipeline Effects
• PC reads return address + 8
• Critical for PC-relative addressing
3. Use Banked Registers Effectively
• Each mode has separate SP, LR
• FIQ has extra banked r8-r12
4. Exception Handling
• Save context to mode-specific stack
• Adjust return PC for pipeline state
• Use SPSR to restore CPSR atomically

Summary 61