Tutorial-1

EEE/CS/ECE/INST F241-Microprocessor Programming & Interfacing

Q.1 How do you determine whether if a microprocessor is 8 bits or 16-bits or
32-bits?
Sol: Size of ALU (i.e. Maximum size of data on with the arithmetic or logical
operation can be performed)

Q.2 What is the order in which the microprocessors bus signals (Address, Data
and Control) are activated?
Sol: Address, Control, Data
Q3.

4- bit

How many bits are required to represent

registers in the machine code?
4- bit

(c) What type of architecture (RISC/CISC) does the processor implement?

RISC

2 bytes

16 address lines

Decoder, control logic, clocking circuitry

Q.4 What is the difference between control flags and the status
flags?
• A flag register stores the results produced by the execution of an instruction or controls certain
operations of the EU.
• In 8086, the Execution Unit (EU) contains a 16 bit flag register.
• Out of the 16 bits 9 are active flags and remaining 7 are Unused (U).
• Out of the 9 active flags
• 6 Status Flags – Sign Flag(SF), Zero Flag(ZF), Auxiliary Carry Flag(AC), Parity Flag(PF), Carry
Flag(CF), Overflow Flag (OF)
• 3 Control Flags – Direction Flag(DF), Interrupt Flag (IF), Trap Flag (TF)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF
Status Flags Control Flags
Flag Purpose Flag Purpose

Carry (CF) Holds the carry after addition or the borrow after Enables the trapping through an on-chip debugging
subtraction. Trap (TF) feature.
Also indicates some error conditions, as dictated by Permits operation of the processor in single step mode.
some programs and procedures . Controls the operation of the INTR (interrupt request)
Parity (PF) PF=0;odd parity, PF=1;even parity. Interrupt (IF) I=0; INTR pin disabled. I=1; INTR pin enabled.
Indicates whether external interrupts are being processed or
Auxiliary Holds the carry (half – carry) after addition or borrow ignored
(AF) after subtraction between bit positions 3 and 4 of the It selects either the increment or decrement mode for DI
result (for example, in BCD addition or subtraction.) Direction (DF) and /or SI registers during the string instructions.
Zero (ZF) Shows the result of the arithmetic or logic operation. Indicates left or right for moving or comparing string data.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic
instruction execution. S=1; negative, S=0 positive.
Overflow Overflow occurs when signed numbers are added or
(OF) subtracted. An overflow indicates the result has
exceeded the capacity of the Machine.
• Status Flags reflect properties of the last executed arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed

After any operation, if D[6] generates any carry and passes to D[7] OR if D[6] does not generates carry but D[7]
generates, overflow flag becomes set, i.e., 1. If D[6] and D[7] both generate carry or both do not generate any
carry, then overflow flag becomes reset, i.e., 0.
**If the XOR of carry-in and carry-out at D[7] comes to be 0 ,OF is set to zero.
• 97 + 48 Decimal 33
0110 0001 Binary 0010 0001

0011 0000 1’s

1101 1110
Complement
1001 0001 2’s
1101 1111
Complement

Decimal 99
• 99 – 33 Binary 0110 0011
0110 0011 1’s
1001 1100
Complement
1101 1111
2’s
0100 0010 1001 1101
Complement

• 33 - 99
0010 0001 Binary 1011 1110 Sign bit 1 indicates that the result is
1001 1101 1’s negative. Take 2’s complement to
0100 0001
Complement obtain the magnitude = 66.
1011 1110
2’s
0100 0010
Complement
 Binary 1100 0011 Decimal 29 Decimal 32
• -29 + -32 1’s
0011 1100 Binary 0001 1101 Binary 0010 0000
Complement
1’s 1’s
1110 0011 2’s 1110 0010 1101 1111
0011 1101 Complement Complement
Complement
1110 0000 2’s
1110 0011
2’s
1110 0000
Complement Complement
1100 0011
Sign bit 1 indicates that the
number is negative. Take
2’s complement to obtain
the magnitude = 61.

• -41 - 95 Decimal 41 Decimal 95

Binary 0010 1001 Binary 0101 1111
1101 0111 1’s 1’s
1101 0110 1010 0000
Complement Complement
1010 0001
2’s 2’s
0111 1000 1101 0111 1010 0001
Complement Complement
Q5. Is there a possibility of two’s complement overflow during
subtraction?

• Yes.
Eg:
Two’s Complement overflow was observed in case of -41-95
1101 0111
1010 0001 Decimal 41 Decimal 95

0111 1000 Binary 0010 1001 Binary 0101 1111

1’s 1’s
1101 0110 1010 0000
Complement Complement
2’s 2’s
1101 0111 1010 0001
Complement Complement