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SR Latch Implementation Using Proteus Simulation and Training Board

The lab report details the implementation and simulation of an SR Latch using NAND gates, focusing on understanding its operation and verifying its states. It outlines objectives, theoretical background, required components, procedures for both software simulation in Proteus and hardware implementation on a training board, and results from testing various input combinations. The successful implementation confirms the SR Latch's functionality as a basic memory element in digital electronics.

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7 views3 pages

SR Latch Implementation Using Proteus Simulation and Training Board

The lab report details the implementation and simulation of an SR Latch using NAND gates, focusing on understanding its operation and verifying its states. It outlines objectives, theoretical background, required components, procedures for both software simulation in Proteus and hardware implementation on a training board, and results from testing various input combinations. The successful implementation confirms the SR Latch's functionality as a basic memory element in digital electronics.

Uploaded by

technologistengineer077
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

LAB REPORT # 08

SR Latch Implementation using Proteus Simulation and Training Board


Objectives

1. To understand the working of a basic SR Latch using NAND gates.


2. To implement the SR Latch hardware-wise on a breadboard.
3. To simulate the SR Latch software-wise in Proteus.
4. To observe and verify the set, reset, and invalid states of the latch.
5. To learn the behavior of bistable circuits in digital electronics.

Theory

1. An SR Latch (Set-Reset Latch) is a bistable multivibrator that stores one bit of


information.
2. It has two inputs:
3. S (Set): sets the output Q = 1
4. R (Reset): resets the output Q = 0
5. It has two outputs: Q and Q’ (complement of Q)

Logic expressions (NAND gate implementation):

Q = S + Q’ (NAND) (1)
Q’ = R + Q (NAND) (2)

Implementation of circuit

(Fig.8.1)

Apparatus / Components Required

For Proteus Simulation

1. Proteus software
2. NAND gates (IC7402)
3. Virtual switches (S and R)
4. Virtual LEDs (Q and Q’)

For Training Board (Hardware)

1. Breadboard
2. 2 × NAND gates (or 7402 IC)
3. Switches for S and R
4. LEDs for outputs Q and Q’
5. Resistors (330Ω for LEDs)
6. 5V DC power supply

Procedure

Simulation in Proteus:

1. Open Proteus and create a new project.


2. Place NAND gates and connect them to form an SR Latch.
3. Connect virtual switches to inputs S and R.
4. Connect virtual LEDs to outputs Q and Q’.
5. Run the simulation and test all input combinations.
6. Observe the LED outputs and verify the latch operation.

Implementation on Training Board (Hardware)

1. Connect NOR gates on the breadboard to form an SR Latch.


2. Connect switches to inputs S and R.
3. Connect LEDs to outputs Q and Q’.
4. Apply all possible input combinations: (S=0,R=0), (S=0,R=1), (S=1,R=0), (S=1,R=1).
5. Observe and record output LEDs.

Circuit on proteus

(Fig.8.2)
(Fig.8.3)

Circuit on training board

(Fig.8.4)

Observations\Results

S R Q(t+1) Q̅(t+1) Condition


1 1 Q(t) Q̅(t) No change (Hold)
0 1 1 0 Set
1 0 0 1 Reset
0 0 1 1 Invalid / Not allowed

The SR latch using NAND gates was successfully implemented. The circuit stores one bit of
information and behaves according to the truth table. Hence, the operation of the SR latch is
verified.

Conclusion

SR Latch using NAND gates is a basic memory element and forms the foundation of flip-flops and
other sequential circuits.

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